六、發明說明： 【發明所屬之技術領域】 β本發明S有關於-種具有電容元件之晶片結構，且特別 是：關於一種利用銲接方式安裝具有高電容量之電容元件 於晶片上的結構，藉以改善適於打線製程之晶片的電性效 JU\r 月6 。 【先前技術】 科積體電路元件發展的趨勢，無不朝向高積集度、高 電!生政a、同散熱效率等方向發展，因此各半導體廢及各 電子封裝廠均不斷地開發出新型的晶片結構及電子構裝結 構’以達到上述目@。在半導體構裝技術上，大致可以分 成二種方式來達成晶片與基板間的電性連接，包括打線導 線連接、凸塊連接及貼帶自動接合技術（Tape Aut_ed Bonding，TAB)等。 資訊產品在工商社會所扮演的角色已愈來愈重要，隨著 資訊產品的推陳出新’新一代的資訊產品比前一代具有更 快的運算速度及更佳的省電性’為達到上述㈣，高頻電 路及低驅動電壓的設計理念，已應運而生。然而在高頻電 路及低驅動電壓的運作下1是晶片與基板間的傳輸是利 用打線導線，貞Π了線導線之寄生電感效應所造成電源匯流 排與接地匯流排的雜訊會特別明顯。而現今的技術係透過 覆S曰封裝的δχ 4概念’使得晶片與基板間電性傳輸所產生 之寄生電感可以減少。然而，覆晶封裝的技術並不如打線 製程成熟’因此在實際執行上有其限制：3外，由於經由 153494.doc 打線製程所形成之打線導線具有取代基板内線路之向外展 開（Fan-〇ut)的功能，因此相較於用於覆晶製程之基板，用 :丁線衣程之基板的繞線密度會比較低，故用於打線製程 之基板會比較便宜。 另種針對打線製程所設計之改善電源匯流排與接地匯 ^排之雜訊的方法’係利用半導體之薄膜製程形成去耗合 包令兀*件（decoupling capach〇r)於晶片内透過去耦合電 容元件作為缓衝，可以改善電源匯流排與接地匯流排之雜 =。然而利用半導體之薄膜製程（thin-film)所形成之去耦 〇電谷疋件並不能提供足夠大的電容量，使得改善電源匯 机排與接地匯流排之雜訊的效果有限；另外，利用半導體 之薄膜製程所形成之去輕合電容元件的成本很高。 【發明内容】 处因此本發明目的之_就是提供—種具有電容元件之晶片 、口構可以利用表面黏著技術安裝具有高電容量之電容元 件於B日片上，藉以改善適於打線製程之晶片的電性效能。 在敛述本發明之前’先對空間介詞的用法做界定，所謂 空間介詞「上」係指兩物之空間關係係為可接觸或不可接 觸句可舉例而吕’ A物在6物上，其所表達的意思係為A 物可以直接配置在8物上，A物有與B物接觸；或者A物係 配置在B物上的空間中，錄沒有與B物接觸。 -為達，本發明之上述及其他之目的提出—種具有電容 件之曰曰片結構，晶片結構係透過打線製程與多條打線導 接口曰曰片結構至少包括_基底、一積層、一保護層及 153494.doc 1359488 至少-電容元件，基底具有多個電子元件，配置在基底之 表層。積層位在基底上，積層具有一介電結構體及一線路 結構體’料結㈣係交錯於積層之介電結㈣巾，而線 路結構體與電子元件電性連接。保護層配置在積層上。 容元件配置在保護層上’並與線路結構體電性連接。 广達成本發明之上述及其他之目的，提出一種電容元件 =成於晶片上的方法’首先要提供一晶片及—已預先製作 几成的電容70件’其中晶片係適於與利用打線製程所形成 之多條打線導線電性連接’接著要將電容元件利用銲接的 方式接合於晶片上，並與晶片電性連接。 综上所述，本發明_料接方式或表面黏著技術裝設 已預先製作完成的電容元件於晶片上，如此藉由電容元件 可以作為外界電源端與電子元件之電源端之間的緩衝。換 言之，此電容元件具有去耦合（Dec〇upHng)之功能。因此 :-般狀態下’電容元件貯存有電荷量，#某一電子元件 突然間需要較大的電流，則透過電容元件可以立即地供應 電能給該電子元件，並且本發明可以接合上具有高電容量 的電容兀件於晶片上，故更可以避免電源匯流排與接地匯 :排之間突然產生大幅度地壓降；或是外界突然流入大電 時藉由电谷元件可以作為緩衝，避免電源匯流排與接 地匯Μ排之間突然產生大幅度地壓差，而損害到電子元 件。 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 153494.doc 1359488 明如下： 【實施方式】 第一實施例 請參照第1圖’其繪示依照本發明第一較佳實施例之具 有電容元件之晶片結構的剖面示意圖。晶片結構1 係透 過打線製程與多條打線導線190接合，在本實施例中晶片 結構1〇〇係包括一晶片11〇及至少一電容元件18〇，電容元 件180係配置在晶片110上’並與晶片11〇電性連接，藉以 改善透過打線導線19 0與外界電路電性連接之晶片效能。 一般而言’晶片110具有一基底12〇、一積層13〇及一保 濩層150。基底120具有多個電子元件122，比如是電晶體 或是金屬氧化半導體等，電子元件122係配置在基底12〇之 表層’其中基底120的材質比如是妙。 積層130係位在基底120上’積層13〇具有一介電結構體 13 1及一線路結構體13 5 ,線路結構體丨3 5係交錯於介電結 構體131中，而線路結構體135與電子元件122電性連接， 其中線路結構體13 5比如可以區分成多晶石夕線路丨3 6及金屬 線路137(斜線區域），多晶矽線路136係位在靠近基底ι2〇 處’而金屬線路137係位在遠離基底12〇處，而透過多晶矽 線路136作為金屬線路137與電子元件122之間電性連接的 媒介’可以具有良好的電性效能，其中金屬線路137的材 質比如是銅、鋁或鋁合金，而每一層之間的線路可以透過 導電插塞138電性連接。然而本發明的應用並不限於此， 線路結構體亦可以均由金屬所構成。線路結構體丨3 5具有 153494.doc 1359488 —電源匯流排139及一接地匯流排140，可以分別與外界電 路之電源端與接地端電性連接，而透過一區塊的電源匯流 排139及一區塊的接地匯流排140係可以提供多個電子元件 12 2電能。 保護層150係配置在積層130上，其中保護層150的結構 係為氮石夕化合物層、氧石夕化合物層、碟石夕玻璃層、該等之 部份組合所組成的複合層或該等之全部組合所組成的複合 層’而保護層150具有多個開口 152、154，暴露出線路結 構體135。. 電容元件180比如是由單顆的被動元件製造廠所提供。 電容元件180之二電極182、184可以藉由一銲料183、186 直接與暴露於保護層150之開口 154外的線路結構體135接 合，其中線路結構體135與銲料186接觸之表層的材質是可 銲性（solder wettab丨e)材質，比如是銅、金、錫、錫鉛合金 或是其他能夠與銲料186接合的材質，而銲料183、186的 材質比如是錫鉛合金或是其他無鉛銲料，比如是錫銀鋼合 金。 就製程而。可以利用表面黏著（Surface Mount)方式將 電谷7L件180接合於晶片11〇上。當被動元件廢在製作電容 兀件180時，可以先將銲料183形成於電容元件“ο之電極 182' 184上’如第1A圖所示，其繪示依照本發明之電容元 件的剖面示意圖；之後’要在將電容元件18〇接合到晶片 110上時ϋ要利用印刷的方式先將鲜料形成在暴露於 保護層150之開口 154外的線路結構體135上然後再將電 153494.doc 1359488 谷元件180置放到銲料186上，其中電容元件i8〇上的銲料 1 83係對準銲料1 %的位置，接著再透過迴銲（refl〇w)的步 驟，使得銲料183、186之間可以接合或融合，如此電容元 件1 80便可以與晶片i i 0穩固接合。6. Description of the Invention: [Technical Field of the Invention] β The present invention relates to a wafer structure having a capacitor element, and in particular, to a structure in which a capacitor element having a high capacitance is mounted on a wafer by soldering, In order to improve the electrical efficiency of the wafer suitable for the wire-making process JU\r. [Prior Art] The trend of the development of the circuit components of the ICIC is all toward the development of high integration, high power, health, and heat dissipation efficiency. Therefore, all semiconductor waste and various electronic packaging factories are constantly developing new types. The wafer structure and the electronic structure structure 'to achieve the above goal@. In the semiconductor packaging technology, the electrical connection between the wafer and the substrate can be roughly divided into two ways, including wire bonding, bump bonding, and Tape Aut_ed Bonding (TAB). The role of information products in the business community has become more and more important. With the introduction of information products, 'a new generation of information products has faster computing speed and better power saving than the previous generation'. To achieve the above (four), high The design concept of frequency circuit and low driving voltage has come into being. However, under the operation of the high-frequency circuit and the low driving voltage, the transmission between the wafer and the substrate is made by using the wire bonding wire, and the noise of the power busbar and the grounding busbar caused by the parasitic inductance effect of the wire wire is particularly obvious. Today's technology reduces the parasitic inductance generated by the electrical transfer between the wafer and the substrate through the δχ4 concept of the S-package. However, the flip chip packaging technology is not as mature as the wire bonding process's. Therefore, there are limitations in the actual implementation: 3, because the wire bonding wire formed by the 153494.doc wire bonding process has the outward expansion of the circuit inside the substrate (Fan-〇 The function of ut) is therefore lower than the substrate used for the flip chip process, and the substrate used for the wire-drawing process has a lower winding density, so that the substrate used for the wire-bonding process is relatively inexpensive. Another method for improving the noise of the power bus and the ground wiring for the wire-making process is to use the thin film process of the semiconductor to form a decoupling capacher to be decoupled in the chip. As a buffer, the capacitor element can improve the power bus and the ground bus. However, the decoupling of the electric valley element formed by the thin film of the semiconductor does not provide a sufficient capacitance, so that the effect of improving the noise of the power grid and the ground bus is limited; The cost of de-lighting capacitive components formed by semiconductor thin film processes is high. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer having a capacitor element, a mouth structure capable of mounting a capacitor element having a high capacitance on a B-chip using surface mount technology, thereby improving a wafer suitable for a wire bonding process. Electrical performance. Before the invention is condensed, the use of spatial prepositions is defined first. The spatial preposition "upper" refers to the spatial relationship between two objects being contactable or inaccessible, and the case of Lu's is on the six objects. The expression means that the A substance can be directly disposed on the 8th substance, and the A substance has the contact with the B substance; or the A substance is disposed in the space on the B object, and is not contacted with the B substance. - For the purpose of the above and other objects of the present invention, a chip structure having a capacitor member, the wafer structure is through a wire bonding process and a plurality of wire bonding interfaces, and the chip structure comprises at least a substrate, a laminate, and a protection. Layer and 153494.doc 1359488 At least - a capacitive element, the substrate having a plurality of electronic components disposed on the surface of the substrate. The laminate is on the substrate, and the laminate has a dielectric structure and a circuit structure. The junction (4) is interlaced with the dielectric junction (4) of the laminate, and the wiring structure is electrically connected to the electronic component. The protective layer is disposed on the laminate. The capacitive element is disposed on the protective layer and electrically connected to the circuit structure. To achieve the above and other objects of the present invention, it is proposed that a capacitor element = a method of forming on a wafer 'firstly provide a wafer and - 70 pieces of capacitors that have been pre-fabricated", wherein the wafer is suitable for use with a wire bonding process The plurality of wire bonding wires are electrically connected. Then, the capacitor component is soldered to the wafer and electrically connected to the wafer. In summary, the present invention has a pre-made capacitor element on the wafer, so that the capacitor element can serve as a buffer between the external power supply terminal and the power supply terminal of the electronic component. In other words, this capacitive element has the function of decoupling (Dec〇upHng). Therefore: in the normal state, the 'capacitor element stores a charge amount, # a certain electronic component suddenly needs a large current, the through-capacitance element can immediately supply electric energy to the electronic component, and the present invention can be coupled with high power. The capacity of the capacitor is on the wafer, so it can avoid the power bus and the grounding sink: a sudden large voltage drop between the rows; or when the outside suddenly flows into the large electricity, the electric valley component can be used as a buffer to avoid the power supply. A sudden large differential pressure is generated between the bus bar and the grounding busbar, which damages the electronic components. The above and other objects, features and advantages of the present invention will become more <RTIgt; 1 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a first preferred embodiment of the present invention. The wafer structure 1 is bonded to the plurality of wire bonding wires 190 through a wire bonding process. In the embodiment, the wafer structure 1 includes a wafer 11 and at least one capacitor component 18, and the capacitor component 180 is disposed on the wafer 110. The chip 11 is electrically connected to the wafer 11 to improve the performance of the wafer electrically connected to the external circuit through the wire bonding wire 19 . Generally, the wafer 110 has a substrate 12, a laminate 13 and a protective layer 150. The substrate 120 has a plurality of electronic components 122, such as a transistor or a metal oxide semiconductor, and the electronic component 122 is disposed on the surface layer of the substrate 12, wherein the material of the substrate 120 is as good. The build-up layer 130 is on the substrate 120. The build-up layer 13 has a dielectric structure 13 1 and a line structure 13 5 . The line structure 丨 3 5 is staggered in the dielectric structure 131 , and the line structure 135 is The electronic component 122 is electrically connected, wherein the circuit structure body 13 can be divided into a polycrystalline stone circuit 36 and a metal line 137 (hatched area), and the polysilicon line 136 is located near the substrate ι2 而 and the metal line 137 The structure is located away from the substrate 12〇, and the medium through the polysilicon line 136 as the electrical connection between the metal line 137 and the electronic component 122 can have good electrical performance, wherein the metal line 137 is made of copper, aluminum or The aluminum alloy, and the wires between each layer can be electrically connected through the conductive plugs 138. However, the application of the present invention is not limited thereto, and the line structures may each be composed of metal. The circuit structure body 3-5 has 153494.doc 1359488 - a power bus 139 and a ground bus 140, which can be respectively electrically connected to the power terminal and the ground terminal of the external circuit, and through a power supply bus 139 and a block The ground busbar 140 of the block can provide a plurality of electronic components 12 2 electrical energy. The protective layer 150 is disposed on the laminate 130, wherein the structure of the protective layer 150 is a composite layer of a Nitrogen compound layer, an Oxygen compound layer, a Sauvignon glass layer, a part of the combination, or the like. The composite layer consisting of all of the combinations' and the protective layer 150 has a plurality of openings 152, 154 exposing the line structure 135. The capacitive element 180 is for example provided by a single passive component manufacturer. The two electrodes 182, 184 of the capacitor element 180 can be directly bonded to the line structure 135 exposed outside the opening 154 of the protective layer 150 by a solder 183, 186. The surface layer of the line structure 135 in contact with the solder 186 is made of a material Solder solder (solder wettab丨e) material, such as copper, gold, tin, tin-lead alloy or other materials that can be bonded to solder 186, and solder 183, 186 material such as tin-lead alloy or other lead-free solder, For example, tin-silver steel alloy. As for the process. The valley 7L piece 180 can be bonded to the wafer 11 by a surface mount method. When the passive component is used to make the capacitor element 180, the solder 183 may be formed on the electrode 182' 184 of the capacitor element as shown in FIG. 1A, which is a schematic cross-sectional view of the capacitor element according to the present invention; Then, when the capacitor element 18 is bonded to the wafer 110, the fresh material is first formed on the wiring structure 135 exposed outside the opening 154 of the protective layer 150 by printing and then charged 153494.doc 1359488 The valley element 180 is placed on the solder 186, wherein the solder 1 83 on the capacitor element i8 is aligned with the solder 1% position, and then through the reflow process, so that the solder 183, 186 can be Bonding or fusing, such that capacitive element 180 can be securely bonded to wafer ii0.
在較佳的情況下，線路結構體丨35中與銲料i 86接觸部位 之下層的材質還必須要具有能夠防止銲料186與線路結構 體135之間產生擴散（diffusi〇n)反應的材質其材質比如是 欽、鈦鶴合金、絡、銅、絡銅合金或錄等。In a preferred case, the material of the layer below the contact portion of the solder structure i 86 in the line structure body 35 must also have a material capable of preventing diffusion between the solder 186 and the line structure 135. For example, Chin, Titanium alloy, complex, copper, copper alloy or recorded.
另外透過打線製程係可以形成多條打線導線190與暴 露於保護層150之開口 152外的線路結構體135接合，其中 線路結構體135與打線導線19〇接觸之表層的材質比如是 鋁鋁合金、銅、金或是其他與打線導線〗9〇接合性良好 的材質。㈣製程而纟，可以是先接合電纟元件18〇於晶 片110上之後，然後再進行打線製程；或者，亦可以是先 進行打線製程，然後再接合電容元件180於晶片110上。電 容元件可以透過線路結構體135與打線導線携電性連 接’比如是將電容元件180之二電極182、184分別與線路 結構體135之電源匯流排139及㈣匯流排14Q電性連接， 而電源匯流排139與接地匯流排14〇可以透過打線導線19〇 分別與外界之電源端或接地端電性連接。 如第1圖所示，由於本發明係利用表面黏著方式裝設電 容元件180於晶片110上，如此藉由電容元件⑽可以作為 外界電源端與電子元件122之電源端之間的緩衝。換言 此電合兀件180具有去雜合（Dec〇upling)之功能。因此 153494.doc 1359488 在一般狀態下’電容元件180貯存有電荷量，當某一電子 元件122突然間需要較大的電流，則透過電容元件180可以 立即地供應電能給該電子元件122，並且本發明可以接合 上具有高電容量的電容元件180於晶片11〇上，故更可以避 免電源匯流排139與接地匯流排140之間突然產生大幅度地 壓降’或是外界突然流入大電流時’藉由電容元件18〇可 以作為緩衝，避免電源匯流排139與接地匯流排14〇之間突 然產生大幅度地壓差，而損害到電子元件122。這就是一 般的去耗合電容之功能。 第二實施例 在則述的較佳實施例中，晶圓廠在製作晶圓時，在線路 結構體之表層線路便直接形成如前所示之可銲性材質及防 擴政材質，然而本發明的應用並不限於此。請參照第2 圖，其繪示依照本發明第二較佳實施例之具有電容元件之 晶片結構的剖面示意圖。一般而言，晶圓廠在製作晶圓 時透過保5蔓層250之開口 252所暴露出之線路結構體235 的材質係為鋁或鋁合金，然而鋁和錫鉛合金的接合性不 佳，因此必須要形成一銲料接合金屬288在保護層25〇之開 : 254所暴露出之線路結構體235上，藉以增加銲料286與 曰曰片210之間的接合性。—般而言辉料接合金屬㈣係具 有孟屬擴散阻絕層287，用以防止銲料286之金屬原子擴 政到、’泉路結構體235中，金屬擴散阻絕層287比如是由欽 層、銅層及鎳層所構成，其中銀層係直接形成在經由保護 層250之開口 252所暴露出之線路結構體235上，銅層係形 153494.doc -10- 1359488 成在鈦層上’鎳層係形成在銅層± ’而敛層亦可以欽鶴合 金層或絡層取代。而若是以鉻層取代欽層#，還可以形成 -鉻銅合金層於鉻層與銅層之間，藉以増加鉻層與銅層之 間的接合性。 如果銲料286是利用印刷的方式形成時，則還必須形成 一接合層289到金屬擴散阻絕層287上，亦即將接合層289 形成到鎳層上，其中接合層289必須要由能夠與鐸料施接 «的材質所構成，比如是金層、銅層、錫層、錫鉛合金層 或是無料㈣等，之後便可方式形成料 挪到接合層289上。另夕卜，如果銲料挪是利用電鍵的方 式形成時，則可以省去接合層289的製作，亦即可以將銲 料286直接形成在金屬擴散阻絕層287上，即為將銲料 直接形成在鎳層上。如此，將銲料286形成到晶片21〇上之 後’便可以利用迴銲的方式，使得位在電容元件28〇上之 銲料283與銲料286之間可以穩固地接合或融合。 第三實施例 請參照第3圖’其繪示依照本發明第三較佳實施例之具 有電容元件之晶片結構的剖面示意圖。在本實施例中，在 銲料3 8 6與線路結構體3 3 5之間配置有一銲料接合金屬 388，藉以增加銲料386與線路結構體335之間的接合性， 料料接合金屬388的結構、材質及製作方法如第二較佳 實施例所述，在此便不再贅述。 另外為使利用打線製程所形成之打線導線39〇與暴露 於保護層350之開口 352外的線路結構體335之間具有更佳 153494.doc 1359488 的接合性，則可以先形成一導線接合金屬392在暴露於保 濩層350之開口 352外的線路結構體335上，之後再利用打 線製程將打線導線390與導線接合金屬392接合。其中導線 接合金屬392由下到上的順序比如是鈦鎢合金層、金層， 八中钬鎢合金層係直接與暴露於保護層350之開口 352外的 線路結構體335接觸。由於一般打線導線39〇的材質係為 金’且可以直接與導線接合金屬392之金層接合，此乃是 相同金屬之間的接合，因此藉由導線接合金屬392的配 置’可以大幅提高打線導線39〇與晶片3 1〇之間的接合性。 另外，由於金與鋁之間亦具有甚佳的接合性，因此導線接 a金屬3 92亦可以是由鋁或鋁合金所構成，亦即材質為金 的打線導線390可以直接打在材質為鋁或鋁合金之導線接 合金屬392上。 第四實施例 在前述的較佳實施例中，係將電容元件直接配置在晶片 的保護層上’然而本發明的應用並不限於此，還可以先形 成另一積層於晶片之保護層上，然後再形成電容元件於該 另一積層上，如第4圖所示，其繪示依照本發明第四較佳 實施例之具有電容元件之晶片結構的剖面示意圖。其中晶 片41 0之結構係如前之較佳實施例所述，亦具有一基底 420、一積層430及一保護層4350。基底4320具有多個電子 元件422配置在基底420之表層。積層430係位在基底420 上’積層430具有一介電結構體431及一線路結構體435， 線路結構體435係交錯於積層43〇之介電結構體431中，而 153494.doc 12 1359488 線路結構體435與電子元件422電性連接。保護層450配置 在積層430上，且保護層450具有多個開口 452，暴露出晶 片410内的線路結構體435。 在提供晶片410之後，還要形成一積層460於晶片410之 保護層450上，積層460具有一介電層461及一線路層465， 線路層465係直接形成在晶片410之保護層450上，介電層 461係覆蓋於線路層465上及保護層450上，線路層465係透 過保護層450之開口 452與晶片410内之線路結構體435電性 連接，介電層46 1具有多個開口 462、463，暴露出線路層 465。其中介電層461的材質比如是聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質或彈性體等，而線路 層465比如是由紹層、鈦層、鈦鶴合金層、銅層、錄層、 金層、錫層及錫船合金層等之上述部份材質所組合而成的 複合層。 電容元件480比如是由單顆的被動元件製造廠所提供。 電容元件480之二電極482、484可以藉由一銲料483、486 直接與暴露於介電層461之開口 463外的線路結構體465接 合，其中線珞層465與銲料486接觸之表層的材質是可銲性 (solder wettable)材質，比如是銅、金、錫、錫錯.合金或是 其他能夠與銲料486接合的材質，而銲料483、486的材質 比如是錫鉛合金或是其他無鉛銲料，比.如是錫銀銅合金。 然而，本發明並不限於此，亦可以在形成線路層465之 後，便利用電鍍的方式直接形成銲料486到線路層465上， 此時銲料486並不限於要與可銲接性的材質接合，比如銲 153494.doc 13 1359488 料486亦可以直接與線路層465之鎳層接合。 就製程而言，可以利用表面黏著（Surface Mount)方式將 電容元件480接合於晶片410上。當被動元件廠在製作電容 元件480時，可以先將銲料483形成於電容元件480之電極 482、484上；之後，要在將電容元件480接合到晶片410上 時，還要利用印刷或是電鍍的方式先將銲料486形成在暴 露於介電層461之開口 463外的線路層465上，然後再將電 容元件480置放到銲料486上，其中電容元件480上的銲料 483係對準銲料486的位置，接著再透過迴銲（reflow)的步 驟，使得銲料483、486之間可以接合或融合，如此電容元 件480便可以與晶片410穩固接合。 在較佳的情況下，線路層465中與銲料486接觸部位之下 層的材質必須要具有能夠防止銲料486與線路層465之間產 生擴散（diffusion)反應的材質，其材質比如是鈦、鈦鶴合 金、鉻、銅、鉻銅合金或鎳等。 另外，透過打線製程係可以形成多條打線導線490與暴 露於介電層461之開口 462外的線路層465接合。而就製程 而言，可以是先接合電容元件480於積層460上之後，再進 行打線製程；或者，亦可以是先進行打線製程，然後再接 合電容元件480於積層460上。電容元件480可以透過線路 層465與打線導線490電性連接，比如是將電容元件480之 二電極482、484分別與線路層465之電源匯流排466及接地 匯流排467電性連接，而電源匯流排466與接地匯流排467 可以透過打線導線490分別與外界之電源端或接地端電性 153494.doc •14- 丄 連接。 第五實施例 :參照第5圖，其繪示依照本發明第五較佳實施例之具 有電容元件之晶片結構的剖面示意圖。如第5圖所示，其 結構係類似第四較佳實施例中具有電容元件之晶片結構， 而本實施例與第四較佳實施例之不同處係在於在鲜料 渴與線路層565之間還可以再配置—銲料接合金屬谓， 错以增加銲料586與線路層565之間的接合性。一般而言， 銲料接合金屬谓係具有-金屬擴散阻絕層587，用以:止 銲料㈣之金屬原子擴散到線路層565中，金屬擴散阻絕層 587比如是由鈦層、銅層及鎳層所構成，纟中敛層係直接 形成在經由介電層561之開口 563所暴露出之線路層泌 上’銅層係形成在欽層上，鎳層係形成在銅層i，而欽層 亦可以鈦鎢合金層或鉻層取代。而若是以鉻層取代鈦層 時，還可以形成一鉻銅合金層於絡層與銅層之間，藉以增 加鉻層與銅層之間的接合性。 曰 如果鲜料586是利用印刷的方式形成時，㈣必須形成 一接合層589到金屬擴散阻絕層58?上，亦即將接合層· 形成到鎳層上，其中接合屢589必須要由能夠與銲料5轉 。的材貝所構成，比如是金層、銅層 '錫層、錫鉛合金層 或是無料料層等，之後便可以利用印刷的方式形成料 5_接合層589上。另外，如果録料挪是利用電錢的方 式形成打’則可以省去接合層589的製作，亦即可以將銲 料586直接形成在金屬擴散阻絕層⑻上，即為將銲料㈣ 153494.doc 15 1359488 直接形成在鎳層上。如此，將銲料586形成到晶片510上之 後，便可以利用迴銲的方式，使得位在電容元件5go上之 銲料583與銲料586之間可以穩固地接合或融合。 第六實施例 請參照第6圖，其繪示依照本發明第六較佳實施例之具 有電容元件之晶片結構的剖面示意圖。其中積層66〇係形 成在晶片610上，積層660具有一介電層661及一線路層 665，線路層665係直接形成在晶片61〇之保護層65〇上介 電層661係覆蓋於線路層665上及保護層65〇上，線路層^“ 係透過保護層650之開口 654與晶片61〇内之線 電性連接，介電層⑹具有多個開口 663，暴露出:體路： 665。其他詳細說明可以參照第四較佳實施例，唯一差異 點係在於在本實施例令，積層66〇並未覆蓋暴露於保護層 650之開口 652外欲與打線導線69〇接合之線路結構體: 使得藉由打線製程，打線導線_可以直接與暴露於保護 層650之開口 652外的線路結構體635接合。電容元件咖 透過銲料、683、686直接接合在積層66〇上。 ’、 透過打線製程係可以形成多條打線導線與暴露於 蠖層650之開口 652外的線路結構體635接合，其 呆 構體635與打線導線_接觸之表層的材 ，、，，。 入、細 疋站、|g八 土 -5金或是其他能夠和打線導線690接合之八屈 就製程而言，可以曰止拉人泰— 孟屬。而 了以疋先接合電容元件680於積屛 後，然後再谁耔制 價層680上之 俊再進仃打線製程；或者，亦可以是 程，然後再桩入贲—_ a 适订打線製 茇丹接合電谷兀件68〇於積層68〇上。 _ 电令兀件68〇 153494.doc • 16 · 1359488 可以透過線路層665及線路結構體635與打線導線690電性 連接’比如是將電容元件680之二電極682、684分別與線 路層6 6 5及線路結構體6 3 5之電源匯流排及接地匯流排電性 連接，而線路結構體63 5之電源匯流排與接地匯流排可以 透過打線導線690分別與外界之電源端或接地端電性連 接。 第七實施例 凊參照第7圖’其繪示依照本發明第七較佳實施例之具 有電容元件之晶片結構的剖面示意圖。如第7圖所示，其 結構係類似第六較佳實施例中具有電容元件之晶片結構， 而本實施例與第六較佳實施例之不同處係在於，在銲料 786與線路層765之間還可以再配置一銲料接合金屬， 藉以增加銲料786與線路層765之間的接合性，而銲料接合 金屬788的結構及材質可以參照第五較佳實施例，在此便 不再贅述。 弟八實施例 凊參照第8圖，其繪示依照本發明第八較佳實施例之具 有黾谷疋件之晶片結構的剖面示意圖。其結構係類似第七 較佳實施例令具有電容元件之晶片結構，而本實施例與第 七較佳實施例之不同處,係在於，還配置一導線接合金屬 892在打線導線謂與暴露於保護層㈣之開口㈣卜的線路 結構體835之間，藉以增加打線導線89〇與晶片81〇間之接 合性。其中詳細導線接合金屬m之結構與材質可以參照 第三較佳實施例，在此便不再贅述。 153494.doc 1359488 第九實施例 請參照第9圖，其繪示依照本發明第九較佳實施例之具 有電容元件之晶片結構的剖面示意圖。在保護層950上亦 可以是僅形成一線路層965到保護層950上，而不形成介電 層到保護層950上，線路層965係透過保護層950之開口 952 與晶片910内之線路結構體935電性連接。電容元件980可 以透過銲料983、986直接與線路層965接合，而線路層965 比如是由紹層、鈦層、鈦鎢合金層、銅層、鎳層、金層、 錫層及錫錯合金層等之上述部份材質所組合而成的複合 層，其中線路層965與銲料986接觸之表層的材質比如是 銅、金、錫、鎳、錫鉛合金、無鉛銲料或是其他可以與銲 料986接合的金屬。其中銲料的材質及形成方法可以參照 第四較佳實施例，在此便不再贅述。 在較佳的情況下，線路層93 5與銲料986接觸之下層的材 質必須要具有能夠防止銲料986與線路層935之間產生擴散 (diffusion)反應的材質，其材質比如是欽、鈦鶴合金、 鉻、銅、鉻銅合金或錄等。 另外，透過打線製程係可以形成多條打線導線990與線 路層965接合。而就製程而言，可以是先接合電容元件980 於線路層965上之後，再進行打線製程；或者，亦可以是 先進行打線製程，然後再接合電容元件980於線路層9.65 上。電容元件980可以透過線路層965與打線導線990電性 連接，比如是將電容元件980之二電極982、984分別與線 路層965之電源匯流排966及接地匯流排967電性連接，而 153494.doc -18- 1359488 電源匯流排9 6 6與接地匯流排9 6 7可以透過打線導線9 9 〇八 別與外界之電源端或接地端電性連接。 第十實施例 請參照第1〇圖，其繪示依照本發明第十較佳實施例之具 有電容元件之晶片結構的剖面示意圖。其結構係類似第九 較佳貫加•例中具有電谷元件之晶片結構’而本實施例盘第 九較佳實施例之不同處係在於，在銲料1086與線路層1〇65 之間還可以再配置一銲料接合金屬1088，藉以增加鲜料 1086與線路結構體1065之間的接合性，其銲料接合金屬 1088的結構及材質如第五較佳實施例所述，在此便不再賛 述。 第十一實施例 請參照第11圖’其繪示依照本發明第十一較佳實施例之 具有電容元件之晶片結構的剖面示意圖。積層1160且有二 介電層1161a、1161b及一線路層1165，其中介電層1161b 係位在保護層1150上，線路層1165係位在介電層1161b 上，而介電層1161a係覆蓋線路層1165及介電層116丨b。介 電層1161b具有多個導通孔11 64，介電層116 lb之導通孔 1164係對準保護層115〇之開口1152，線路層1165可以經過 介電層1161b之導通孔1164及保護層1150之開口 1152與暴 露在保護層115 0之開口 11 5 2外的線路結構體1丨3 5電性連 接。在本實施例中，介電層1161b之導通孔1164可量測的 最大寬度係大於保護層1150之開口 1152可量測的最大寬 度’然而在實際應用上，介電層1164之導通孔1164可量測 153494.doc •19- !359488 的最大寬度亦可以小於或等於保護層1150之開口 1152可量 測的最大寬度。而介電層1161a具有多個開口 1162、 1163 ’係暴露出線路層1165。其中介電層丨i 6丨及線路層 11 6 5的材質係可以參照第四較佳實施例的說明。 電容元件1180可以透過銲料1183、1186直接與線路層 1165接合’而線路層1165比如是由链層、鈦層、鈦鎢合金 層、銅層、鎳層、金層、錫層及錫鉛合金層等之上述部份 材質所組合而成的複合層，其中線路層1165與銲料1186接 觸之表層的材質比如是銅、金、錫、錫鉛合金或是其他能 夠與銲料1186接合的材質。 “另外，透過打線製程係可以形成多條打線導線丨1與暴 露於介電層1161a之開口 1162外的線路層1165 製程而言，可以是先接合電容元件丨18。於積層二 後，再進行打線製程；或者，亦可以是先進行打線製程， 然後再接合電容元件118〇於積層116〇上。電容元件謂可 以透過線路層1165與打線導線㈣電性連接，比如是將電 容元件mo之二電極1182、1184分別與線路層ιΐ65之電源 匯流排1166及接地M流排1167電性連接，而電源匯流排 與接地匯流排1167可以透過打線導線⑽分別與外界 之電源端或接地端電性連接。 第十二實施例 請參照第12圖，复絡千分a3 + Λ „从 且有雷…曰本發明第十二較佳實施例之 Μ L曰片結構的剖面示意圖。其結構俜類似第 十-較佳實施例中具有電容 糸類㈣ 0曰乃、·Ό構，而本實施例 153494.doc •20· 1359488 與第十較佳實施例之不同處係在於，在銲料1286與線路 層1265之間還可以再配置一銲料接合金屬1288，藉以增加 銲料1286與線路結構體1265之間的接合性，其銲料接合金 屬1288的結構及材質如第五較佳實施例所述，在此便不再 贅述。 第十三實施例 在則述的較佳實施例中，形成在保護層上之積層係以一 層線路層為例，然而本發明的應用並不限於此，在保護層 上之積層亦可以是具有多層線路層，如第13圖所示，其繪 示依照本發明第十三較佳實施例之具有電容元件之晶片結 構的剖面示意圖。積層136〇比如具有二線路層n65a、 1365b及二介電層1361a、1361b，線路層136讣係位在晶片 1310之保護層135〇上，可以與晶片131〇之線路結構體1335 連接’介電層1361b係覆蓋線路層1365b及保護層1350，介 電層1361b具有多個導通孔1392，暴露出線路層1365b。而 線路層1365a係位在介電層i361b上，透過介電層13611?之 導通孔1391可以與線路層1365b連接，介電層n61a係覆蓋 線路層1365a及介電層i361b，介電層1361a具有多個開口 1362、13 63，暴露出線路層1365a。 另外’在銲料1386與線路層1365a之間還可以配置一銲 料接合金屬1388 ’藉以增加銲料1 386與線路層1365a之間 的接合性’而銲料接合金屬13 8 8的結構及材質可以參照第 五較佳實施例’在此便不再贅述。電容元件13 8 0可以透過 銲料1383、1386及銲料接合金屬1388穩固地接合在晶片 153494.doc •21· 1359488 1310 上。 此外’透過打線製程係可以形成多條打線導線139〇與線 路層1365a接合。而就製程而言，可以是先接合電容元件 1380於線路層1365a上之後，再進行打線製程；或者，亦 可以是先進行打線製程’然後再接合電容元件138〇於線路 層1365a上。 在本實施例中，位在保護層上之積層的配置係以兩層線 路層為例，然而本發明的應用並不限於此，亦可以是三 層、四層或是其他數目的線路層配置於位在保護層上之積 層中。 結論 綜上所述，本發明係利用銲接方式或表面黏著技術裝設 電容兀件於晶片上，如此藉由電容元件可以作為外界電源 端與電子元件之電源端之間的緩衝。換言之，此電容元件 具有去耦合（Decoupling)之功能。因此在一般狀態下，電 容兀件貯存有電荷量，當某一電子元件突然間需要較大的 電流’則透過電容元件可以立即地供應電能給該電子元 件，並且本發明可以接合上具有高電容量的電容元件於晶 片上’故更可以避免電源匯流排與接地匯流排之間突然產 生大幅度地壓降；或是外界突然流入大電流時，藉由電容 70件可以作為緩衝，避免電源匯流排與接地匯流排之間突 然產生大幅度地壓差，而損害到電子元件。 雖然本發明已以較佳實施例揭露如上’然其並非用以限 定本發明’任何熟習此技藝者，在不脫離本發明之精神和 153494.doc -22- 1359488 =内，當可作各種之更動㈣飾，因此本發明 圍‘視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示依照本發明第一較 平乂住貫施例之具有雷 之晶片結構的剖面示意圖。 第1A圖所不，其繪示依昭太欢。。 圖。 I、本發明之電容元件的剖面示意 第2圖繪示依照本發明第二 权彳土 Λ知例之具有電容元株 之日日片結構的剖面示意圖。 第3圖繪示依照本發明第二* s u 較佳實施例之具有電容元侔 之曰日片結構的剖面示意圖。 第4圖繪示依照本發明第^ ^ ^ ^ ^ ^ 乎乂乜λ把例之具有電容元 之晶片結構的剖面示意圖。 第5圖繪示依照本發明第 牙立早乂佳貫施例之具有雷 之晶片結構的剖面示意圖。 牛 第6圖繪示依照本發明第a — 月弟，、較佳實施例之具有 之晶片結構的剖面示意圖。 疋件 第7圖繪示依照本發明第七 子乂住貝粑例之具有電容 之晶片結構的剖面示意圖。 第8圖繪示依照本發明第八 平乂佳貫施例之具有電容 之晶片結構的剖面示意圖。 午 第9圖繪示依照本發明第九較佳實施例之具有電办_ 之晶片結構的剖面示意圖。 几件 第10圖繪示依照本發明第十較 τ平乂佳貝施例之具有電容元件 153494.doc -23- 1359488 之晶片結構的剖面示意圖。 第11圖繪示依照本發明第十一較佳實施例之具有電容元 件之晶片結構的剖面示意圖。 第12圖繪示依照本發明第十二較佳實施例之具有電容元 件之晶片結構的剖面示意圖。 第13圖繪示依照本發明第十三較佳實施例之具有電容元 件之晶片結構的剖面示意圖。 【主要元件符號說明】 100 晶片結構 110 晶片 120 基底 122 電子元件 130 積層 131 介電結構體 135 線路結構體 136 多晶矽線路 137 金屬線路 138 導電插塞 139 電源匯流排 140 接地匯流排 150 保護層 152 開口 154 開口 180 電容元件 153494.doc -24- 1359488In addition, a plurality of wire bonding wires 190 can be formed to be bonded to the circuit structure body 135 exposed outside the opening 152 of the protective layer 150 through a wire bonding process, wherein the surface layer of the wire structure body 135 contacting the wire bonding wire 19 is made of aluminum alloy, Copper, gold or other material with good bonding properties. (4) The process may be performed by first bonding the electrical component 18 onto the wafer 110 and then performing a wire bonding process. Alternatively, the wire bonding process may be performed before the capacitive component 180 is bonded to the wafer 110. The capacitive component can be electrically connected to the wire conductor through the line structure 135. For example, the two electrodes 182 and 184 of the capacitor component 180 are electrically connected to the power bus 139 and the (four) bus bar 14Q of the circuit structure 135 respectively, and the power supply is connected. The row 139 and the grounding busbar 14〇 can be electrically connected to the external power supply terminal or the grounding terminal through the wire bonding wires 19〇. As shown in Fig. 1, since the present invention employs a surface mount method to mount the capacitor element 180 on the wafer 110, the capacitor element (10) can be used as a buffer between the external power supply terminal and the power supply terminal of the electronic component 122. In other words, the electric fitting element 180 has the function of de-hybridization. Therefore, 153494.doc 1359488 In the normal state, the capacitive element 180 stores a charge amount, and when a certain electronic component 122 suddenly needs a large current, the transmitted capacitive element 180 can immediately supply power to the electronic component 122, and The invention can bond the capacitor element 180 having a high capacitance to the wafer 11A, so that a sudden large voltage drop between the power bus bar 139 and the ground bus bar 140 can be avoided, or when a large current flows suddenly. The capacitor element 18 can be used as a buffer to prevent a sudden large voltage difference between the power bus bar 139 and the ground bus bar 14A, thereby damaging the electronic component 122. This is the general function of consuming capacitors. Second Embodiment In the preferred embodiment described above, when the wafer fab is fabricated, the surface layer of the circuit structure directly forms the solderable material and the anti-expansion material as shown above. The application of the invention is not limited to this. Referring to Figure 2, there is shown a cross-sectional view of a wafer structure having a capacitive element in accordance with a second preferred embodiment of the present invention. Generally, the material of the line structure 235 exposed by the fab through the opening 252 of the vine layer 250 is aluminum or aluminum alloy, but the bonding property of the aluminum and the tin-lead alloy is not good. Therefore, it is necessary to form a solder bonding metal 288 on the wiring structure 235 exposed by the protective layer 25: 254, thereby increasing the bond between the solder 286 and the wafer 210. In general, the stellite bonding metal (4) has a Meng diffusion barrier layer 287 for preventing the metal atoms of the solder 286 from expanding into the 'spring structure 235, and the metal diffusion barrier layer 287 is, for example, a layer of copper and copper. The layer and the nickel layer are formed, wherein the silver layer is directly formed on the line structure body 235 exposed through the opening 252 of the protective layer 250, and the copper layer is formed on the titanium layer 153494.doc -10- 1359488 It is formed in the copper layer ± ' and the layer can also be replaced by the alloy layer or the layer. If the chrome layer is substituted for the smect layer #, a chrome-copper alloy layer may be formed between the chrome layer and the copper layer, whereby the entanglement between the chrome layer and the copper layer is added. If the solder 286 is formed by printing, a bonding layer 289 must also be formed on the metal diffusion barrier layer 287, that is, the bonding layer 289 is formed on the nickel layer, wherein the bonding layer 289 must be capable of being applied to the bonding layer. It is composed of a material such as a gold layer, a copper layer, a tin layer, a tin-lead alloy layer or a materialless material (four), and then the material can be transferred to the bonding layer 289. In addition, if the solder is formed by using a key, the fabrication of the bonding layer 289 can be omitted, that is, the solder 286 can be directly formed on the metal diffusion barrier layer 287, that is, the solder is directly formed on the nickel layer. on. Thus, after the solder 286 is formed on the wafer 21, it can be reflowed so that the solder 283 located on the capacitor 28 and the solder 286 can be firmly bonded or fused. THIRD EMBODIMENT Referring to Figure 3, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a third preferred embodiment of the present invention. In the present embodiment, a solder bonding metal 388 is disposed between the solder 386 and the wiring structure 335 to increase the bond between the solder 386 and the wiring structure 335, the structure of the material bonding metal 388, The materials and manufacturing methods are as described in the second preferred embodiment, and will not be described herein. In addition, in order to make the bonding wire 39 形成 formed by the wire bonding process and the wiring structure 335 exposed outside the opening 352 of the protective layer 350 have better bonding property of 153494.doc 1359488, a wire bonding metal 392 may be formed first. On the line structure 335 exposed outside the opening 352 of the protective layer 350, the wire bonding wire 390 is then bonded to the wire bonding metal 392 by a wire bonding process. The bottom-to-up order of the wire bonding metal 392 is, for example, a titanium-tungsten alloy layer, a gold layer, and the bazhong-tungsten-tungsten alloy layer is directly in contact with the wiring structure 335 exposed to the opening 352 of the protective layer 350. Since the material of the wire bonding wire 39 is generally made of gold and can be directly bonded to the gold layer of the wire bonding metal 392, which is the bonding between the same metal, the wire bonding wire can be greatly improved by the configuration of the wire bonding metal 392. The bond between 39〇 and the wafer 3 1〇. In addition, because of the good bonding between gold and aluminum, the wire connection a metal 3 92 can also be made of aluminum or aluminum alloy, that is, the wire 390 made of gold can be directly used in the material of aluminum. Or a wire of aluminum alloy is bonded to the metal 392. Fourth Embodiment In the foregoing preferred embodiment, the capacitive element is directly disposed on the protective layer of the wafer. However, the application of the present invention is not limited thereto, and another protective layer laminated on the wafer may be formed first. Then, a capacitor element is formed on the other layer. As shown in FIG. 4, a cross-sectional view of the wafer structure having the capacitor element in accordance with the fourth preferred embodiment of the present invention is shown. The structure of the wafer 41 0 has a substrate 420, a laminate 430 and a protective layer 4350 as described in the preferred embodiment. The substrate 4320 has a plurality of electronic components 422 disposed on the surface of the substrate 420. The build-up layer 430 is fastened on the substrate 420. The build-up layer 430 has a dielectric structure 431 and a line structure 435, and the line structure 435 is interleaved in the dielectric structure 431 of the laminate 43〇, and 153494.doc 12 1359488 line The structure 435 is electrically connected to the electronic component 422. The protective layer 450 is disposed on the buildup layer 430, and the protective layer 450 has a plurality of openings 452 that expose the line structures 435 within the wafer 410. After the wafer 410 is provided, a build-up layer 460 is formed on the protective layer 450 of the wafer 410. The build-up layer 460 has a dielectric layer 461 and a wiring layer 465 formed directly on the protective layer 450 of the wafer 410. The dielectric layer 461 is over the circuit layer 465 and the protective layer 450. The circuit layer 465 is electrically connected to the circuit structure 435 in the wafer 410 through the opening 452 of the protective layer 450. The dielectric layer 46 1 has a plurality of openings. 462, 463, exposing the circuit layer 465. The material of the dielectric layer 461 is, for example, polyimide, phenylcyclobutene, polyarylene ether, porous dielectric material or elastomer, and the circuit layer 465 is composed of a layer, a titanium layer and a titanium. A composite layer composed of the above-mentioned materials of a crane alloy layer, a copper layer, a recording layer, a gold layer, a tin layer, and a tin boat alloy layer. Capacitive element 480 is provided, for example, by a single passive component manufacturer. The two electrodes 482, 484 of the capacitive element 480 can be directly bonded to the line structure 465 exposed outside the opening 463 of the dielectric layer 461 by a solder 483, 486, wherein the surface layer of the layer 465 contacting the solder 486 is Solder wettable materials, such as copper, gold, tin, tin, alloy or other materials that can be bonded to solder 486, while solder 483, 486 is made of tin-lead alloy or other lead-free solder. Than. If it is tin-silver-copper alloy. However, the present invention is not limited thereto, and it is also possible to directly form the solder 486 onto the wiring layer 465 by electroplating after the formation of the wiring layer 465. At this time, the solder 486 is not limited to being bonded to a solderable material, such as Solder 153494.doc 13 1359488 material 486 may also be bonded directly to the nickel layer of wiring layer 465. In the case of the process, the capacitive element 480 can be bonded to the wafer 410 by a surface mount method. When the passive component factory is fabricating the capacitive component 480, the solder 483 may be first formed on the electrodes 482, 484 of the capacitive component 480; thereafter, when the capacitive component 480 is bonded to the wafer 410, printing or plating is also utilized. The solder 486 is first formed on the wiring layer 465 exposed outside the opening 463 of the dielectric layer 461, and then the capacitive element 480 is placed on the solder 486, wherein the solder 483 on the capacitive element 480 is aligned with the solder 486. The position, and then through the reflow step, allows solder 483, 486 to be bonded or fused, such that capacitive element 480 can be securely bonded to wafer 410. In a preferred case, the material of the layer below the contact portion of the solder layer 486 in the circuit layer 465 must have a material capable of preventing a diffusion reaction between the solder 486 and the wiring layer 465, such as titanium or titanium crane. Alloy, chromium, copper, chrome-copper alloy or nickel. In addition, a plurality of wire bonding wires 490 may be formed to be bonded to the wiring layer 465 exposed outside the opening 462 of the dielectric layer 461 through the wire bonding process. In the case of the process, the bonding component 480 may be bonded to the buildup layer 460 before the bonding process is performed. Alternatively, the bonding process may be performed first, and then the capacitive component 480 may be coupled to the buildup layer 460. The capacitor element 480 can be electrically connected to the wire bonding wire 490 through the circuit layer 465. For example, the two electrodes 482 and 484 of the capacitor component 480 are electrically connected to the power bus bar 466 and the ground bus bar 467 of the circuit layer 465, respectively, and the power source is connected. The row 466 and the grounding bus 467 can be respectively connected to the external power supply terminal or the ground terminal 153494.doc • 14- 透过 through the wire bonding wire 490. Fifth Embodiment: Referring to Fig. 5, there is shown a cross-sectional view showing a structure of a wafer having a capacitor element in accordance with a fifth preferred embodiment of the present invention. As shown in FIG. 5, the structure is similar to the wafer structure having the capacitor element in the fourth preferred embodiment, and the difference between this embodiment and the fourth preferred embodiment lies in the fresh material and the circuit layer 565. It is also possible to reconfigure the solder joint metal to increase the bond between the solder 586 and the wiring layer 565. In general, the solder joint metal has a metal diffusion barrier layer 587 for: the metal atoms of the solder (4) are diffused into the circuit layer 565, and the metal diffusion barrier layer 587 is made of, for example, a titanium layer, a copper layer, and a nickel layer. In the composition, the layer of the crucible is formed directly on the layer of the layer exposed by the opening 563 of the dielectric layer 561. The copper layer is formed on the layer of the layer, and the layer of nickel is formed on the layer of copper, and the layer can also be Replaced with a titanium tungsten alloy layer or a chromium layer. When the titanium layer is replaced by a chrome layer, a chrome-copper alloy layer may be formed between the layer and the copper layer to increase the bond between the chrome layer and the copper layer.曰If the fresh material 586 is formed by printing, (4) a bonding layer 589 must be formed on the metal diffusion barrier layer 58, that is, the bonding layer is formed on the nickel layer, wherein the bonding 589 must be made of solder. 5 turns. The material is made of, for example, a gold layer, a copper layer, a tin layer, a tin-lead alloy layer, or a material-free layer, and then can be formed by printing on the bonding layer 589. In addition, if the recording is made by means of electricity money, the fabrication of the bonding layer 589 can be omitted, that is, the solder 586 can be directly formed on the metal diffusion barrier layer (8), that is, the solder (4) 153494.doc 15 1359488 is formed directly on the nickel layer. Thus, after the solder 586 is formed on the wafer 510, it can be reflowed so that the solder 583 located on the capacitive element 5go and the solder 586 can be firmly joined or fused. Sixth Embodiment Referring to Figure 6, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a sixth preferred embodiment of the present invention. The build-up layer 66 is formed on the wafer 610. The build-up layer 660 has a dielectric layer 661 and a circuit layer 665. The circuit layer 665 is directly formed on the protective layer 65 of the wafer 61. The dielectric layer 661 covers the circuit layer. On the 665 and the protective layer 65, the circuit layer is electrically connected to the line inside the wafer 61 through the opening 654 of the protective layer 650. The dielectric layer (6) has a plurality of openings 663, exposing: body path: 665. For further detailed description, reference may be made to the fourth preferred embodiment, the only difference being that in the present embodiment, the build-up layer 66 is not covered by the line structure exposed to the opening 652 of the protective layer 650 to be bonded to the wire bonding wire 69: The wire bonding wire _ can be directly bonded to the wiring structure body 635 exposed outside the opening 652 of the protective layer 650 by the wire bonding process. The capacitor component is directly bonded to the laminate 66 through the solder, 683, 686. ', through the wire bonding process The plurality of wire bonding wires may be formed to be joined to the wiring structure body 635 exposed outside the opening 652 of the enamel layer 650, and the constituting body 635 and the wire bonding wire _ contact the surface layer of the material, and, into, fine 疋 station, | g eight -5 gold or other eight bends that can be joined to the wire conductor 690. In terms of the process, it is possible to stop the pull of the Thai-Meng, and then join the capacitive component 680 to build the product, and then the price layer. On the 680, Jun will enter the line-making process again; or, it can be a process, and then piled into the 贲-_ a 适 打 打 接合 接合 接合 接合 接合 接合 接合 接合 接合 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 68 68 68 68 68 68 〇 153494.doc • 16 · 1359488 can be electrically connected to the wire conductor 690 through the circuit layer 665 and the line structure body 635 ' For example, the two electrodes 682 and 684 of the capacitor element 680 and the circuit layer 6 6 5 and the line structure body 6 respectively The power bus and the ground bus are electrically connected to each other, and the power bus and the ground bus of the line structure 63 5 can be electrically connected to the external power source or the ground through the wire 690, respectively. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a seventh preferred embodiment of the present invention. As shown in FIG. 7, the structure is similar to that of the sixth preferred embodiment. Wafer structure, The difference between this embodiment and the sixth preferred embodiment is that a solder bonding metal can be further disposed between the solder 786 and the wiring layer 765, thereby increasing the bonding between the solder 786 and the wiring layer 765. The structure and material of the solder joint metal 788 can be referred to the fifth preferred embodiment, and will not be described herein. The eighth embodiment is referred to the eighth embodiment, which shows the valley in accordance with the eighth preferred embodiment of the present invention. A cross-sectional view of a wafer structure of a device. The structure is similar to that of the seventh preferred embodiment, and the difference between the present embodiment and the seventh preferred embodiment is that a wire bond is also disposed. The metal 892 is between the wire bonding wire and the wiring structure body 835 exposed to the opening (4) of the protective layer (4), thereby increasing the bonding property between the wire bonding wire 89A and the wafer 81. The structure and material of the detailed wire bonding metal m can be referred to the third preferred embodiment, and will not be described herein. 153494.doc 1359488 Ninth Embodiment Referring to Figure 9, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a ninth preferred embodiment of the present invention. On the protective layer 950, only one wiring layer 965 to the protective layer 950 may be formed without forming a dielectric layer to the protective layer 950. The wiring layer 965 is transmitted through the opening 952 of the protective layer 950 and the wiring structure in the wafer 910. Body 935 is electrically connected. The capacitive element 980 can be directly bonded to the wiring layer 965 through the solder 983, 986, and the wiring layer 965 is composed of, for example, a layer, a titanium layer, a titanium-tungsten alloy layer, a copper layer, a nickel layer, a gold layer, a tin layer, and a tin-alloy layer. And a composite layer formed by combining the above materials, wherein the surface layer 965 is in contact with the solder 986, such as copper, gold, tin, nickel, tin-lead alloy, lead-free solder or the like, which can be bonded to the solder 986. Metal. The material and formation method of the solder can be referred to the fourth preferred embodiment, and will not be described herein. In a preferred case, the material of the layer below the contact between the wiring layer 935 and the solder 986 must have a material capable of preventing a diffusion reaction between the solder 986 and the wiring layer 935, and the material thereof is, for example, a Chin, a titanium alloy. , chrome, copper, chrome-copper alloy or recorded. In addition, a plurality of wire bonding wires 990 can be formed to be bonded to the wiring layer 965 through the wire bonding process. For the process, the capacitor component 980 may be bonded to the circuit layer 965 before the wire bonding process. Alternatively, the wire bonding process may be performed first, and then the capacitor component 980 may be bonded to the circuit layer 9.65. The capacitor element 980 can be electrically connected to the wire bonding wire 990 through the circuit layer 965. For example, the two electrodes 982 and 984 of the capacitor component 980 are electrically connected to the power busbar 966 and the grounding busbar 967 of the circuit layer 965, respectively, and 153494. Doc -18- 1359488 The power busbar 9 6 6 and the grounding busbar 9 6 7 can be electrically connected to the external power supply terminal or grounding terminal through the wire bonding wire 9 9 〇8. Tenth Embodiment Referring to Figure 1, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a tenth preferred embodiment of the present invention. The structure of the ninth preferred embodiment is similar to that of the ninth preferred embodiment. The difference between the ninth preferred embodiment of the present embodiment is that between the solder 1086 and the circuit layer 1〇65. A solder bonding metal 1088 may be further disposed to increase the bonding between the fresh material 1086 and the wiring structure 1065. The structure and material of the solder bonding metal 1088 are as described in the fifth preferred embodiment, and no longer like this. Said. Eleventh Embodiment Referring to Figure 11, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with an eleventh preferred embodiment of the present invention. The laminate 1160 has two dielectric layers 1161a, 1161b and a wiring layer 1165, wherein the dielectric layer 1161b is on the protective layer 1150, the wiring layer 1165 is on the dielectric layer 1161b, and the dielectric layer 1161a is covered. Layer 1165 and dielectric layer 116丨b. The dielectric layer 1161b has a plurality of vias 164, the vias 1164 of the dielectric layer 116b are aligned with the openings 1152 of the protective layer 115, and the circuit layer 1165 can pass through the vias 1164 and the protective layer 1150 of the dielectric layer 1161b. The opening 1152 is electrically connected to the line structure 1 丨 3 5 exposed outside the opening 11 5 of the protective layer 115 0 . In the present embodiment, the maximum width that the vias 1164 of the dielectric layer 1161b can measure is greater than the maximum width that can be measured by the opening 1152 of the protective layer 1150. However, in practical applications, the vias 1164 of the dielectric layer 1164 can be The maximum width of the measurement 153494.doc •19-!359488 may also be less than or equal to the maximum width measurable by the opening 1152 of the protective layer 1150. The dielectric layer 1161a has a plurality of openings 1162, 1163' that expose the wiring layer 1165. The material of the dielectric layer 丨i 6丨 and the circuit layer 11 6 can be referred to the description of the fourth preferred embodiment. The capacitive element 1180 can be directly bonded to the wiring layer 1165 through the solders 1183, 1186, and the wiring layer 1165 is, for example, a chain layer, a titanium layer, a titanium-tungsten alloy layer, a copper layer, a nickel layer, a gold layer, a tin layer, and a tin-lead alloy layer. A composite layer in which the above-mentioned materials are combined, wherein the surface layer of the wiring layer 1165 in contact with the solder 1186 is made of copper, gold, tin, tin-lead alloy or other material capable of bonding with the solder 1186. In addition, the wiring layer 丨1 and the circuit layer 1165 exposed outside the opening 1162 of the dielectric layer 1161a may be formed by the wire bonding process, and the capacitive component 丨18 may be bonded first. The wire bonding process; or, the wire bonding process may be performed first, and then the capacitive component 118 is bonded to the buildup layer 116. The capacitor component may be electrically connected to the wire conductor (4) through the circuit layer 1165, for example, the capacitor component mo The electrodes 1182 and 1184 are respectively electrically connected to the power bus 1166 and the ground M row 1167 of the circuit layer ι 65, and the power bus and the ground bus 1167 can be electrically connected to the external power supply or the ground through the wire (10). The twelfth embodiment, referring to Fig. 12, is a cross-sectional view showing the structure of the 曰 L 曰 sheet of the twelfth preferred embodiment of the present invention. The structure is similar to that of the tenth embodiment - the preferred embodiment has a capacitance type (4), and the difference between the embodiment 153494.doc • 20·1359488 and the tenth preferred embodiment lies in A solder bonding metal 1288 may be further disposed between the solder 1286 and the wiring layer 1265 to increase the bonding between the solder 1286 and the wiring structure 1265. The structure and material of the solder bonding metal 1288 are as in the fifth preferred embodiment. As mentioned, it will not be repeated here. Thirteenth Embodiment In the preferred embodiment described above, the layer formed on the protective layer is exemplified by a layer of wiring layer. However, the application of the present invention is not limited thereto, and the layer on the protective layer may also have The multilayer wiring layer, as shown in Fig. 13, is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a thirteenth preferred embodiment of the present invention. The laminate 136 〇 has, for example, two wiring layers n65a, 1365b and two dielectric layers 1361a, 1361b, and the wiring layer 136 is on the protective layer 135 of the wafer 1310, and can be connected to the wiring structure 1335 of the wafer 131. The layer 1361b covers the wiring layer 1365b and the protective layer 1350. The dielectric layer 1361b has a plurality of via holes 1392 to expose the wiring layer 1365b. The circuit layer 1365a is located on the dielectric layer i361b, and the via hole 1391 of the dielectric layer 13611 is connected to the circuit layer 1365b. The dielectric layer n61a covers the circuit layer 1365a and the dielectric layer i361b. The dielectric layer 1361a has a dielectric layer 1361a. A plurality of openings 1362, 13 63 expose the circuit layer 1365a. In addition, 'a solder bonding metal 1388' may be disposed between the solder 1386 and the wiring layer 1365a to increase the bonding between the solder 1386 and the wiring layer 1365a. The structure and material of the solder bonding metal 13 8 8 may refer to the fifth The preferred embodiment 'will not be described again here. Capacitor element 138 can be firmly bonded to wafer 153494.doc • 21·1359488 1310 via solder 1383, 1386 and solder bond metal 1388. In addition, a plurality of wire bonding wires 139 形成 can be formed to be bonded to the wiring layer 1365a through the wire bonding process. In the case of the process, the bonding component 1380 may be bonded to the circuit layer 1365a before the bonding process is performed. Alternatively, the bonding process may be performed first, and then the capacitive component 138 may be bonded to the wiring layer 1365a. In this embodiment, the configuration of the layer on the protective layer is exemplified by two layers of circuit layers. However, the application of the present invention is not limited thereto, and may be three layers, four layers, or other numbers of circuit layer configurations. In the layer on the protective layer. Conclusion In summary, the present invention uses a soldering method or a surface bonding technique to mount a capacitor component on a wafer, so that the capacitor element can serve as a buffer between the external power supply terminal and the power supply terminal of the electronic component. In other words, this capacitive element has the function of decoupling. Therefore, in a general state, the capacitor element stores a charge amount, and when a certain electronic component suddenly needs a large current, the capacitor element can immediately supply power to the electronic component, and the present invention can be coupled with high power. The capacitor element of the capacity is on the wafer, so that a sudden large voltage drop between the power busbar and the ground busbar can be avoided; or when a large current flows suddenly, the capacitor 70 can be used as a buffer to avoid the power supply convergence. A large differential pressure suddenly occurs between the row and the ground busbar, which damages the electronic components. Although the present invention has been disclosed in its preferred embodiments, as described above, it is not intended to limit the invention to any skilled person, without departing from the spirit of the invention and 153494.doc -22- 1359488 = The invention is modified (4), and therefore the invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a wafer structure having a lightning according to a first comparative embodiment of the present invention. No. 1A is not shown, it shows Yi Zhao Tai Huan. . Figure. I. Cross-sectional view of a capacitive element of the present invention Fig. 2 is a cross-sectional view showing the structure of a solar cell having a capacitor element in accordance with a second embodiment of the present invention. FIG. 3 is a cross-sectional view showing a structure of a solar cell having a capacitor element according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a wafer having a capacitor element according to the first embodiment of the present invention. Fig. 5 is a cross-sectional view showing the structure of a wafer having a lightning according to a preferred embodiment of the present invention. Fig. 6 is a cross-sectional view showing the structure of a wafer having a preferred embodiment according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 7 is a cross-sectional view showing a structure of a wafer having a capacitance in accordance with a seventh embodiment of the present invention. Fig. 8 is a cross-sectional view showing the structure of a wafer having a capacitance in accordance with an eighth embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing a wafer structure having an electric office according to a ninth preferred embodiment of the present invention. Several pieces Fig. 10 is a cross-sectional view showing the structure of a wafer having a capacitive element 153494.doc -23- 1359488 according to the tenth embodiment of the present invention. Figure 11 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with an eleventh preferred embodiment of the present invention. Figure 12 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with a twelfth preferred embodiment of the present invention. Figure 13 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with a thirteenth preferred embodiment of the present invention. [Main component symbol description] 100 wafer structure 110 wafer 120 substrate 122 electronic component 130 laminate 131 dielectric structure 135 circuit structure 136 polysilicon line 137 metal line 138 conductive plug 139 power bus 140 ground bus 150 protective layer 152 opening 154 opening 180 capacitive element 153494.doc -24- 1359488
182 電極 183 銲料 184 電極 186 銲料 190 打線導線 210 晶片 235 線路結構體 250 保護層 252 開口 280 電容元件 283 銲料 286 銲料 287 金屬擴散阻絕層 288 銲料接合金屬 289 接合層 310 晶片 335 線路結構體 350 保護層 352 開口 386 銲料 388 銲料接合金屬 390 打線導線 392 導線接合金屬 410 晶片 153494.doc -25- 1359488 420 基底 422 電子元件 430 積層 431 介電結構體 435 線路結構體 450 保護層 452 開口 460 積層 461 介電層 462 開口 463 開口 465 線路層 466 電源匯流排 467 接地匯流排 480 電容元件 482 電極 484 電極 483 銲料 486 銲料 490 打線導線 561 介電層 563 開口 565 線路層 583 銲料 153494.doc -26 1359488182 electrode 183 solder 184 electrode 186 solder 190 wire conductor 210 wafer 235 line structure 250 protective layer 252 opening 280 capacitive element 283 solder 286 solder 287 metal diffusion barrier layer 288 solder joint metal 289 bonding layer 310 wafer 335 line structure 350 protective layer 352 opening 386 solder 388 solder bonding metal 390 wire bonding wire 392 wire bonding metal 410 wafer 153494.doc -25- 1359488 420 substrate 422 electronic component 430 laminate 431 dielectric structure 435 circuit structure 450 protective layer 452 opening 460 layer 461 dielectric Layer 462 Opening 463 Opening 465 Circuit Layer 466 Power Bus 467 Ground Bus 480 Capacitor 482 Electrode 484 Electrode 483 Solder 486 Solder 490 Wire 561 Dielectric Layer 563 Opening 565 Circuit Layer 583 Solder 153494.doc -26 1359488
586 銲料 587 金屬擴散阻絕層 588 銲料接合金屬 589 接合層 610 晶片 635 線路結構體 650 保護層 652 開口 654 開口 660 積層 661 介電層 665 線路層 680 電容元件 682 電極 683 銲料 684 電極 686 銲料 690 打線導線 765 線路層 786 銲料 788 銲料接合金屬 835 線路結構體 850 保護層 852 開口 -27- 153494.doc 1359488 860 積層 890 打線導線 892 導線接合金屬 910 晶片 935 線路結構體 950 保護層 952 開口 965 線路層 966 電源匯流排 967 接地匯流排 980 電容元件 982 電極 983 銲料 984 電極 986 銲料 990 打線導線 1065 線路結構體 1086 銲料 1088 銲料接合金屬 1110 晶片 1135 線路結構體 1150 保護層 1152 開口 1160 積層 153494.doc -28- 1359488586 solder 587 metal diffusion barrier layer 588 solder bonding metal 589 bonding layer 610 wafer 635 circuit structure body 650 protective layer 652 opening 654 opening 660 layer 661 dielectric layer 665 circuit layer 680 capacitive element 682 electrode 683 solder 684 electrode 686 solder 690 wire wire 765 circuit layer 786 solder 788 solder joint metal 835 line structure body 850 protective layer 852 opening -27- 153494.doc 1359488 860 laminated layer 890 wire conductor 892 wire bonding metal 910 wafer 935 line structure body 950 protective layer 952 opening 965 circuit layer 966 power supply Bus 967 Ground Bus 980 Capacitor 982 Electrode 983 Solder 984 Electrode 986 Solder 990 Wire Conductor 1065 Line Structure 1086 Solder 1088 Solder Bond Metal 1110 Wafer 1135 Line Structure 1150 Protective Layer 1152 Opening 1160 Stack 153494.doc -28- 1359488
1161a 介電層 1161b 介電層 1162 開口 1163 開口 1164 導通孔 965 線路層 1166 電源匯流排 1167 接地匯流排 1180 電容元件 1182 電極 1183 銲料 1184 電極 1186 銲料 1190 打線導線 1265 線路層 1286 銲料 1288 銲料接合金屬 1310 晶片 1335 線路結構體 1350 保護層 1360 積層 1361a 介電層 1361b 介電層 1362 開口 -29 153494.doc 1359488 1363 開口 1365a 線路層 1365b 線路層 1380 電容元件 1386 銲料 1388 銲料接合金屬 1390 打線導線 1392 導通孔 153494.doc -301161a Dielectric layer 1161b Dielectric layer 1162 Opening 1163 Opening 1164 Via 965 Line layer 1166 Power bus 1167 Ground bus 1180 Capacitance element 1182 Electrode 1183 Solder 1184 Electrode 1186 Solder 1190 Wire conductor 1265 Line layer 1286 Solder 1288 Solder joint metal 1310 Wafer 1335 Line Structure 1350 Protective Layer 1360 Laminate 1361a Dielectric Layer 1361b Dielectric Layer 1362 Opening -29 153494.doc 1359488 1363 Opening 1365a Circuit Layer 1365b Circuit Layer 1380 Capacitance Element 1386 Solder Bond 1388 Solder Bond Metal 1390 Wire Conductor 1392 Via 153494 .doc -30