TW201131728A - Chip structure with a capacitor and method for mounting a capacitor over a chip - Google Patents

Abstract

Discrete capacitors are surface-mounted on an IC chip. The discrete capacitors are connected to the metal interconnection scheme under the passivation layer and to conductive wires formed by a wire-bonding process. The capacitors can be served to decouple the noise and electrical fluctuation through the conductive wires.

Description

201131728 VI. Description of the Invention: [Technical Field] The present invention relates to a wafer structure having a capacitor element, and more particularly to a structure for mounting a capacitor element having a high capacitance on a wafer by soldering. In order to improve the electrical efficiency of the wafer suitable for the wire-bonding process [Prior Art] Nowadays, the trend of the development of integrated circuit components has progressed toward high integration, high-power efficiency, and heat dissipation efficiency. Therefore, various semiconductor factories And each electronic packaging factory continuously (4) issued a new type of crystal structure and electronic structure structure to achieve the above (4). In the semiconductor packaging technology, the electrical connection between the crystal > 1 and the substrate can be roughly divided into two ways, including wire bonding, bump bonding, and Tape Automated Bonding (TAB). The role of information products in the business community has become more and more important. With the innovation of information products, the new generation of information products has faster computing speed and better power saving than the previous generation. The design concept of frequency circuit and low driving voltage has come into being. However, under the operation of the high frequency circuit and the low driving voltage, if the transmission between the wafer and the substrate is made by using the wire bonding wire, the noise of the power busbar and the grounding busbar caused by the parasitic inductance effect of the wire bonding wire is particularly noticeable. Today's technology reduces the parasitic inductance generated by the electrical transfer between the wafer and the substrate through the design concept of the flip chip package. However, the flip chip packaging technology is not as mature as the wire bonding process's, so there is a limit in its actual implementation; in addition, the wire bonding wire formed by the 153494.doc 201131728 wire bonding process has the function of replacing the wires in the substrate (Fan-〇 The function of ut), therefore, the substrate used for the wire bonding process has a lower winding density than the substrate used for the flip chip process, so the substrate used for the wire bonding process is relatively inexpensive. Another improved power bus and grounding sink designed for the wire bonding process

The method of arranging noise is to use a semiconductor thin film process to form a decoupling capacitor in the wafer, and the decoupling capacitor is used as a buffer to improve the noise of the power bus and the ground bus. However, the decoupling capacitive element formed by the semiconductor thin film process (thin_film) does not provide a sufficient capacitance, so that the effect of improving the noise of the power bus and the ground bus is limited; in addition, the thin film process of the semiconductor is used. The cost of decoupling capacitive components is high. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a wafer structure having a capacitor element which can be mounted on a wafer by a surface mount technique to improve the electrical performance of a wafer suitable for a wire bonding process. Before describing the present invention, the use of spatial prepositions is defined first. The spatial preposition "upper" means that the spatial relationship between the two objects is contactable or inaccessible: For example, 'A substance is on B, which means that A can be directly disposed on (10), and A has contact with B to be placed in the space on B, and A is not in contact with B. . In order to achieve the above and other objects of the present invention, a wafer structure having a capacitor member is disclosed. The wafer structure is bonded to a plurality of wire bonding wires through a wire bonding process. The wafer structure includes at least a substrate, a buildup layer, a protective layer, and 153494. .doc 201131728 At least one capacitive element 'substrate has multiple electronic components arranged on the surface of the substrate. The layer is placed on the substrate, and the layer is formed by a combination of a dielectric structure and a line structure, and the line structure is staggered in the dielectric structure of the layer, and the line structure is electrically connected to the electronic component. The protective layer is disposed on the laminate. The capacitor element is disposed on the protective layer and electrically connected to the line structure body. In order to achieve the above and other objects of the present invention, it is proposed that a method of forming a capacitor element on a wafer 'firstly provides a wafer and - 70 parts of which have been pre-made 70 parts of the wafer." The plurality of wire-bonding wires formed by the process are electrically connected, and then the capacitor component is bonded to the wafer in a manner of being closely connected to the wafer and electrically connected to the wafer. In summary, the present invention uses a soldering method or a surface bonding technique to mount a pre-made capacitor element on a wafer, so that the capacitor element can serve as a buffer between the external power supply terminal and the power supply terminal of the electronic component. In other words, this capacitive element has the function of decoupling. Therefore, in a general state, the capacitor element stores a charge amount. When a certain electronic component suddenly needs a large current, the capacitor element can immediately supply power to the electronic component, and the present invention can be bonded with a high capacitance. 70 pieces of electricity valleys are placed on the wafer, so that a sudden large voltage drop between the power bus bar and the ground bus bar can be avoided; or when a large current flows suddenly, the capacitor element can be used as a buffer to avoid power supply convergence. A large differential pressure suddenly occurs between the row and the ground busbar, which damages the electronic components. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 1 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a first preferred embodiment of the present invention. The wafer structure 100 is bonded to the plurality of wire bonding wires 19 through the wire bonding process. In the embodiment, the wafer structure 100 includes a wafer i and at least one capacitor component 丨8〇, and the capacitor component 180 is disposed on the wafer 11 And electrically connected to the wafer 11 to improve the performance of the wafer electrically connected to the external circuit through the wire bonding wire 190. Generally, the wafer 110 has a substrate 12 〇, a laminate 13 〇, and a protective layer 150. The substrate 120 has a plurality of electronic components 22 such as a transistor or a metal oxide semiconductor, and the electronic component 122 is disposed on the surface layer of the substrate 12, wherein the material of the substrate 120 is, for example, germanium. The build-up layer 130 is located on the substrate 12, and the build-up layer 13 has a dielectric structure 131 and a line structure 135. The line structure 135 is staggered in the dielectric junction φ structure, and the line structure 135 and the electronic component 122 electrical connection, wherein the line structure 135 can be divided into a polysilicon line 136 and a metal line 137 (hatched area), for example, the polysilicon line 136 is located close to the substrate ία, and the metal line 137 is located away from the substrate 12〇. The polysilicon channel 136 can be used as a medium for electrically connecting the metal line 137 and the electronic component 122, and the material of the metal line ip is, for example, copper, aluminum or aluminum alloy, and between each layer. The lines can be electrically connected through the conductive plugs 138. However, the application of the present invention is not limited thereto, and the line structures may each be composed of metal. The circuit structure US has 153494.doc 201131728 a power bus 139 and a ground bus 丨40, which can be electrically connected to the power terminal and the ground terminal of the external circuit respectively, and through a block of power supply bus 139 and a region. The block's ground busbar 14 can provide multiple electronic components 122 electrical energy. The protective layer 150 is disposed on the laminate 13 , wherein the protective layer 15 is a nitride layer, an oxonium compound layer, a phosphorous glass layer, a composite layer composed of a part of the combination or the like The composite layer is composed of all of the combinations, and the protective layer 150 has a plurality of openings 152, 154 exposing the line structure 13 5 . Capacitive element 180 is provided, for example, by a single passive component manufacturer. The two electrodes 182, 184 of the capacitor element 180 can be directly bonded to the line structure body 135 exposed outside the opening 154 of the protective layer 150 by a solder Φ, 186. The surface layer of the line structure body 135 in contact with the solder 186 is Solderability (solder wettab 丨〇 material, such as copper, gold, tin, tin-lead alloy or other materials that can be bonded to the solder 186, and the material of the solder 183, 186 is, for example, (four) alloy or other non-materials, such as It is a tin-silver-copper alloy. In terms of the process, the surface of the capacitor can be bonded to the wafer 11 by the surface adhesion (Waee m.). When the passive component factory is making the capacitor (10), the solder can be first 183. Formed on the electrodes 182, 184 of the capacitive element (10) as shown, the green color shows a schematic cross-sectional view of the capacitive element according to the present invention; after that, when the capacitive element 18 is bonded to the wafer, 'printing is also used. The method first forms the solder 186 on the line structure 135 exposed outside the opening 154 of the protective layer 150, and then powers the 153494.doc 201131728

The capacitive element 180 is placed on the solder 186, and the solder 183 on the 18 〇 对准 „ , 对准 对准 对准 对准 对准 对准 对准 对准 对准 对准 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 183, 186 can be joined or fused, so that the capacitive element 180 can be firmly bonded to the wafer 11A.

In a preferred case, the material of the lower layer of the contact portion of the wiring structure 135 with the solder 186 must also have a material capable of preventing a diffusion reaction between the solder 186 and the wiring structure 135, such as titanium. , Titanium alloy, chromium, copper, chromium copper alloy or recorded. In addition, a plurality of wire bonding wires 19 are formed through the wire bonding process to be bonded to the wiring structure 135 exposed outside the opening 152 of the protective layer 150. The material ratio Z of the surface structure body 35 contacting the wire bonding wire 190 is aluminum. , aluminum alloy, copper, gold or other materials that are well bonded to the wire conductor 19〇. In the process, the bonding component 18 can be bonded to the wafer 110 before the bonding process is performed. Alternatively, the bonding process can be performed first, and then the capacitive component 18 is bonded to the wafer 11A. The electric valley element 180 can be electrically connected to the wire bonding wire 9 through the line structure i 35. For example, the two electrodes 182 and 184 of the capacitor element 180 and the power bus 139 and the ground bus 14 of the line structure body 135, respectively. The power bus bar 139 and the ground bus bar 140 can be electrically connected to the external power terminal or the ground terminal through the wire bonding wires i9. As shown in FIG. 1 , since the present invention uses the surface mount method to mount the electric valley element 18 on the wafer 11 ', the capacitive element 丨 8 〇 can be used as the external power supply terminal and the power supply end of the electronic component 122. Buffer. In other words, the electric grid element 18 has the function of decoupling. Therefore, 153494.doc 201131728 In the general state, the capacitive element 180 stores a charge amount, and when a certain electronic component 122 suddenly needs a large current, the transmitted capacitive element 180 can immediately supply power to the electronic component 丨22, and The present invention can bond the capacitor element 180 having a high capacitance to the wafer 110, so that a sudden large voltage drop between the power busbar 1 39 and the ground busbar 14 ' can be avoided or a large current flows suddenly. At this time, the capacitive element 18 can be used as a buffer to avoid a sudden large difference in voltage between the power bus 139 and the ground bus 140, thereby damaging the electronic component 122. This is the general function of decoupling capacitors. Second Embodiment In the foregoing preferred embodiment, when the wafer fab is fabricated, the surface of the circuit structure directly forms a solderable material and a non-diffusion material as shown in the foregoing, but the present invention The application is not limited to this. Referring to Figure 2, there is shown a cross-sectional view of a wafer structure having a capacitive element in accordance with a second preferred embodiment of the present invention. In general, the material of the line structure 235 exposed by the fab in the fabrication of the wafer temple through the opening 252 of the protective layer 250 is aluminum or aluminum alloy. However, the bonding property between the aluminum and the tin-lead alloy is poor. A solder bonding metal 288 must be formed over the wiring structure 235 exposed by the protective layer 250: 254 to increase the bond between the solder (10) and the corrugated sheet 210. In general, a solder bonding metal Mg device, a metal diffusion barrier layer 287, is used to prevent metal atoms of the solder 286 from expanding into the line structure body 235, such as a germanium layer, a steel layer, and a metal layer. The titanium layer is directly formed on the line structure w exposed by the opening σ 252 of the protective layer 250, and the copper layer is formed on the titanium layer. The nickel layer is formed on the copper layer. The titanium layer can also be replaced by a titanium layer or a chromium layer. If the chrome layer is used instead of the titanium layer, it can be smashed; the chrome-copper alloy layer is between the chrome layer and the steel layer, thereby increasing the bond between the road layer and the steel. θ If the solder 286 is formed by printing, it is also necessary to form a bonding layer 289 onto the metal diffusion barrier layer 287, that is, the bonding layer Mg is formed on the nickel layer 'where the bonding layer 289 must be capable of being soldered 2, such as a gold layer, a copper layer, a tin layer, a tin wrought gold layer or a non-error solder layer, etc., and then a fresh material 286 can be formed on the bonding layer 289 by means of a brush. 3, if the solder m is formed by means of electric ore, the fabrication of the bonding layer 289 can be omitted, that is, the fresh material 286 can be directly formed on the metal diffusion barrier layer 287, that is, the solder 286 is directly formed. On the nickel layer. As such, the solder 286 is formed to the wafer η. After that, the reflow can be used to firmly bond or fuse the solder 283 located on the capacitor element 28 and the solder 286. SECOND EMBODIMENT Referring to Figure 3, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a third preferred embodiment of the present invention. In the present embodiment, a solder bonding metal 388 is disposed between the solder 386 and the wiring structure 3 3 5, thereby increasing the bonding between the solder 386 and the wiring structure 335, the structure of the f solder bonding metal 388, The materials and manufacturing methods are as described in the second preferred embodiment, and will not be described herein. In addition, in order to make the wire bonding wire 390 formed by the wire bonding process and the wire structure body 335 exposed to the outside of the opening 352 of the protective layer 350 have a better connection property of 153494.doc 201131728, a wire bonding metal 3S can be formed first. 2 is exposed on the line structure 335 outside the opening 352 of the protective layer 350, and then the wire bonding wire 39 is bonded to the wire bonding metal 392 by a wire bonding process. The order in which the wire bonding metal 392 is from bottom to top is, for example, a titanium-tungsten alloy layer, a gold layer, wherein the titanium-tungsten alloy layer is in direct contact with the wiring structure 335 which is exposed outside the opening 352 of the protective layer 35A. Since the material of the common wire bonding wire 39 is gold and can be directly bonded to the gold layer of the wire bonding metal 392, this is the bonding between the same metals, so that the wire bonding wire can be greatly improved by the configuration of the wire bonding metal 392. The bond between 39〇 and the wafer 31〇. In addition, because of the good bonding between gold and aluminum, the wire bonding metal 392 can also be made of aluminum or aluminum alloy, that is, the wire 390 made of gold can be directly used in aluminum or aluminum. The wire of the alloy is bonded to the metal 392. Fourth Embodiment In the foregoing preferred embodiment, the capacitive element is directly disposed on the protective layer of the wafer. However, the application of the present invention is not limited thereto, and another protective layer laminated on the wafer may be formed first. Then, a capacitor element is formed on the other layer. As shown in FIG. 4, a cross-sectional view of the wafer structure having the capacitor element in accordance with the fourth preferred embodiment of the present invention is shown. The structure of the wafer 4 10 is as described in the prior preferred embodiment. The substrate 420 has a substrate 420, a buildup layer 430 and a protective layer 435. The substrate 4320 has a plurality of electronic components 422 ′ disposed on the surface layer of the substrate 420. The 430 is on the substrate 42. The buildup layer 430 has a dielectric structure 431 and a line structure 435, and the line structure 435 is interleaved in the dielectric structure 431 of the build-up layer 430, and 153494.doc •12·201131728 The circuit structure 435 is electrically connected to the electronic component 422. The protective layer 45A is disposed on the buildup layer 430, and the protective layer 45A has a plurality of openings 452 exposing the line structure 43 in the wafer 410. After the b-chip 410 is formed, a build-up layer 46 is formed on the protective layer 450 of the wafer 41. The build-up layer 46 has a dielectric layer 461 and a circuit layer village 5, and the circuit layer 465 is formed directly on the wafer 41. The protective layer 45 is disposed on the circuit layer 465 and the protective layer 45A. The circuit layer 465 is electrically connected to the circuit structure 435 in the wafer 410 through the opening 452 of the protective layer 450. The electrical layer 461 has a plurality of openings 462, such as exposed lines The material of the layer 8 &quot; electrical layer 46 1 is, for example, a polyimide, a phenylcyclobutene, a polyarylene ether, a porous dielectric material or an elastomer, and the circuit layer 465 is, for example, an aluminum layer. a composite layer composed of a titanium layer, a titanium-tungsten alloy layer, a copper &amp; a nickel layer, a gold layer, a tin layer, and a tin-lead alloy layer, etc. The capacitor is, for example, a single piece. Provided by the passive component manufacturer. The capacitor elements of the second electrode 482, 484 can be bonded by soldering directly to the line structure body exposed to the opening of the dielectric layer 461. The material of the surface layer of the 486 contact is the fresh-colored Cerwet Uble material. For example, copper, gold, tin-tin alloy bite is another material that can be bonded to the solder, and (4) such as ^ material such as tin boat alloy or other No _, such as tin silver copper alloy. ': However, the present invention is not limited thereto, and it is also possible to form a recording material directly on the wiring layer 465 after forming the wiring layer 465. In this case, the solder damage is not limited to the solderability. Material bonding, such as welding 153494.doc • 13- 201131728 Material 486 can also be directly bonded to the nickel layer of wiring layer 465. In the case of the process, the capacitive element 480 can be bonded to the wafer 410 by a surface mount method. When the passive component factory is fabricating the capacitive component 480, the solder 483 may be first formed on the electrodes 482, 484 of the capacitive component 480; thereafter, when the capacitive component 480 is bonded to the wafer 410, printing or plating is also utilized. The solder 486 is first formed on the wiring layer 465 exposed outside the opening 463 of the dielectric layer 461, and then the capacitive element 480 is placed on the solder 486, wherein the solder 483 on the capacitive element 480 is aligned with the solder 486. The position, and then through the re-welding (reHow) step, allows solder 483, 486 to be bonded or fused, such that capacitive element 480 can be securely bonded to wafer 410. In a preferred case, the material of the layer below the contact portion of the solder layer 486 in the circuit layer 465 must have a material capable of preventing a diffusion reaction between the solder 486 and the wiring layer 465, such as titanium or titanium tungsten. Alloy, chromium, copper, chrome-copper alloy or nickel. In addition, a plurality of wire bonding wires 490 may be formed to be bonded to the wiring layer 465 exposed outside the opening 462 of the dielectric layer 461 through the wire bonding process. In the case of the process, the bonding component 480 may be bonded to the buildup layer 460 before the bonding process is performed. Alternatively, the bonding process may be performed first, and then the capacitive component 480 may be coupled to the buildup layer 460. The capacitor element 480 can be electrically connected to the wire bonding wire 490 through the circuit layer 465. For example, the two electrodes 482 and 484 of the capacitor component 480 are electrically connected to the power bus bar 466 and the ground bus bar 467 of the circuit layer 465, respectively, and the power source is connected. The row 466 and the grounding busbar 467 can be connected to the external power source or grounding terminal 153494.doc -14-201131728 through the wire bonding wire 490, respectively. Fifth Embodiment Referring to Figure 5, there is shown a cross-sectional view of a wafer structure having a cell element in accordance with a fifth preferred embodiment of the present invention. As shown in FIG. 5, the structure is similar to the wafer structure having the capacitor element in the fourth preferred embodiment, and the difference between this embodiment and the fourth preferred embodiment is that the solder 586 and the wiring layer 565 are A solder bonding metal ms may be further disposed to increase the bond between the solder 586 and the wiring layer 565. Generally, the solder joint metal 588 has a metal diffusion barrier layer 587 for preventing metal atoms of the solder 586 from diffusing into the circuit layer 565. The metal diffusion barrier layer 587 is composed of a titanium layer, a copper layer and a nickel layer. Wherein the titanium layer is formed on the circuit layer %5 exposed through the opening 563 of the dielectric layer 561. The copper layer is formed on the titanium layer, and the recording layer is formed on the copper layer, and the titanium layer is also formed on the copper layer. It can be replaced by a titanium tungsten alloy layer or a chromium layer. When the titanium layer is replaced by a chrome layer, a copper alloy layer may be formed between the chrome layer and the steel layer, whereby the bond between the diatom layer and the copper layer is formed. If the solder 586 is printed by X, then a s layer 589 must be formed to the metal diffusion barrier, 邑 layer 587, that is, the bonding layer 589 is formed on the nickel layer, wherein the bonding layer 589 The person consists of a material that is connected to the solder 586, such as a gold layer, θ., Λ tin layer, tin-lead alloy layer or tantalum, ... lead solder layer, etc., and then 586 钊The solder is formed into a solder etch &amp; layer 589 by printing. In addition, if the soldering is formed, the bonding layer 589 U can be omitted, and the film can be formed on the metal (four) barrier layer (8), that is, the solder 586] 53494.doc 15 201131728 is directly formed. On the recording layer. Thus, after the solder 586 is formed on the wafer 5i, the reflow can be used to firmly bond or fuse the fresh material 583 and the solder 586 located on the capacitor. Sixth Embodiment Referring to Figure 6, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a sixth preferred embodiment of the present invention. Wherein the buildup layer is formed on the wafer 6U), the buildup layer 66 has a dielectric layer 661 and a wiring layer 665'. The wiring layer 665 is formed directly on the protective layer (4) of the wafer 61, and the dielectric layer (6) is covered by the wiring. On the layer "5" and the protective layer 65", the line sound "5 is transmitted through the opening 654 of the protective layer 650 to the line structure of the wafer 61". The dielectric layer 661 has a plurality of openings (6) to expose the line. The layer 665 / other detailed description can refer to the fourth preferred embodiment, the only difference is that in the embodiment, the layer _ does not cover the opening 652 exposed to the protective layer 65 〇 θ and is intended to be bonded to the wire bonding wire _ The line structure body 635, :: can be directly bonded to the line structure body 635 exposed to the protection through the two ports: 2 by the wire bonding process 'wire wire _. The capacitive element _ is directly bonded to the laminate 66 through zinc crucibles, 683, and 686. The it wire-making process can form a plurality of wire conductors 69° and a circuit structure body (4) exposed outside the opening σ 652 of the protective layer (4), and the material of the surface layer of the structure 635 and the wire bonding wire is, for example, a surface. To the copper or other process that can be joined to the wire bonding wire 69, the process can be performed after the bonding capacitor element 68 is placed on the laminate 68〇, and then the wire bonding process is performed; or Alternatively, it may be the first process, and then the capacitor element 680 is bonded to the laminate _, and the TL device 68 〇 153494.doc -16· 201131728 can be electrically connected through the circuit layer 665 and the line structure body 635 and the wire conductor 690. For example, the two electrodes 682 and 684 of the capacitor element 680 are electrically connected to the power bus and the ground bus of the circuit layer 665 and the line structure 635 respectively, and the power bus of the line structure 635 is connected. The grounding busbars can be electrically connected to the external power supply terminal or the grounding terminal through the wire bonding wires 690, respectively. Seventh Embodiment * Moon Referring to Figure 7, there is shown a cross-sectional view of a wafer structure having a cell element in accordance with a seventh preferred embodiment of the present invention. As shown in FIG. 7, the structure is similar to the wafer structure having the capacitor element in the sixth preferred embodiment, and the difference between this embodiment and the sixth preferred embodiment is that the solder 786 and the wiring layer 765 are A solder bonding metal 788 may be further disposed to increase the bonding between the solder 786 and the wiring layer 765. The structure and material of the solder bonding metal 788 may be referred to the fifth preferred embodiment, and will not be described herein. Eighth Embodiment Referring to Figure 8, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with an eighth preferred embodiment of the present invention. The structure is similar to the wafer structure having the capacitor element in the seventh preferred embodiment, and the difference between this embodiment and the seventh preferred embodiment is that a wire bond gold 892 is also disposed on the wire bonding wire 89G and exposed to the protection. (10) Between the line structures 835 outside the opening (10), thereby increasing the bonding between the green wire 890 and the wafer 8}. The detailed wire joints are now eight. The structure and material of the I 892 can be referred to the second preferred embodiment, and will not be described again. 153494.doc 17 201131728 Ninth Embodiment Referring to Figure 9, there is shown a cross-sectional view of a wafer structure having a cell element in accordance with a ninth preferred embodiment of the present invention. On the protective layer 95, only one wiring layer 965 to the protective layer 95 0 may be formed without forming a dielectric layer to the protective layer 950. The wiring layer 965 is transmitted through the opening 952 of the protective layer 95 and the inside of the wafer 910. The line structure body 935 is electrically connected. The capacitor element 98 can be directly bonded to the circuit layer 965 through the solder 983, 986, and the circuit layer 965 is composed of, for example, an aluminum layer, a titanium layer, a titanium-tungsten alloy layer, a copper layer, a nickel layer, a gold layer, a tin layer, and a tin-lead alloy. a composite layer of a combination of the above materials, wherein the surface layer 965 is in contact with the solder 986, such as copper, gold, tin, nickel, tin-lead alloy, lead-free solder or other solder 986 Bonded metal. The material and formation method of the solder can be referred to the fourth preferred embodiment, and will not be described herein. In a preferred case, the material of the layer below the contact between the wiring layer 935 and the solder 986 must have a material capable of preventing a diffusion reaction between the solder 986 and the wiring layer 935, such as titanium, titanium alloy, and road. , copper, chrome-copper alloy or nickel. In addition, a plurality of wire bonding wires 99 can be formed to be joined to the wiring layer 965 through the wire bonding process. In the case of the process, the bonding process may be performed after the capacitor element 98 is bonded to the circuit layer 965. Alternatively, the wire bonding process may be performed, and then the capacitor element 98 may be bonded to the circuit layer 965. The electric grid element 980 can be electrically connected to the wire bonding wire 99 through the circuit layer 965. For example, the two electrodes 982 and 984 of the capacitor element 980 are electrically connected to the power bus 966 and the grounding bus 967 of the circuit layer 965, respectively. And 153494.doc 201131728 power bus 966 and ground busbar %., β 』 is connected to the power supply terminal or ground terminal of the outside through the wire 990. Tenth embodiment

Referring to Figure _, there is shown a cross-sectional view of a wafer structure having an electric grid member in accordance with a tenth preferred embodiment of the present invention. The structure is similar to the structure of the capacitor having the capacitance (4) in the ninth embodiment, and the difference between this embodiment and the ninth preferred embodiment is that a solder joint can be further disposed between the solder _86 and the circuit layer. The metal 1〇88 is used to increase the bond between the solder 1086 and the wiring structure 1〇65. The structure and material of the solder bonding metal 1088 are as described in the fifth preferred embodiment, and the tenth is not described here. 1 is a cross-sectional view showing a wafer structure having a cell element according to a tenth preferred embodiment of the present invention. The build-up layer has two dielectric layers 1161a, 1161b and a circuit layer 11 65, wherein the dielectric layer 1161b is on the protective layer 50, and the circuit layer 1165 is on the dielectric layer U61b' and the dielectric layer 1161a The circuit layer 1165 and the dielectric layer 1161b are covered. The dielectric layer 1161b has a plurality of vias η 64, the vias 116 of the dielectric layer 1161b are aligned with the openings 11 52 of the protective layer 115, and the wiring layer 165 can pass through the vias 1164 of the dielectric layer 1161b and protect The opening 1152 of the layer 1150 is electrically connected to the line structure 1135 exposed outside the opening 1152 of the protective layer 1150. In the present embodiment, the maximum width that the vias 1164 of the dielectric layer 116 lb can measure is greater than the maximum width that can be measured by the opening 1152 of the protective layer 1150. However, in practical applications, the vias 1164 of the dielectric layer 1164 can be The maximum width of the measurement 153494.doc •19-201131728 may also be less than or equal to the maximum width measurable by the opening 1152 of the protective layer 115〇. The dielectric layer u 6丨a has a plurality of openings 丨丨62, 1163 that expose the circuit layer 丨165. The materials of the dielectric layer 1161 and the circuit layer 1165 can be referred to the description of the fourth preferred embodiment. The electric valley element 1180 can be directly bonded to the wiring layer 1165 through the solders 1183, 1186, and the wiring layer 65 is made of, for example, an aluminum layer, a titanium layer, a titanium-tungsten alloy layer, a copper layer, a nickel layer, a gold layer, a tin layer, and tin. a composite layer composed of the above-mentioned partial materials such as a lead alloy layer, wherein the surface layer of the wiring layer 1165 in contact with the solder Η% is made of copper, gold, tin, tin-lead alloy or the like which can be bonded to the solder 1186. Material. In addition, a plurality of wire conductors 119 are formed by the wire bonding process to be bonded to the wiring layer 1165 exposed outside the opening 1162 of the dielectric layer 1161a. In the case of the process, the bonding component 118 may be bonded to the layer ΐ6〇 before the wire bonding process is performed. Alternatively, the wire bonding process may be performed first, and then the capacitor element 1180 is bonded to the buildup layer 116. The capacitor element ιΐ8〇 can be electrically connected to the wire bonding wire 1190 through the circuit layer 1165. For example, the two electrodes 1182 and 1184 of the capacitor component 1180 are electrically connected to the power busbar 1166 and the ground busbar 1167 of the circuit layer u65, respectively. The bus bar 1166 and the ground bus bar 1167 can be electrically connected to the external power supply terminal or the ground terminal through the wire bonding wires 119 。 respectively. Twelfth Embodiment Referring to Figure 12, there is shown a cross-sectional view of a wafer structure having a capacitor element in accordance with a twelfth preferred embodiment of the present invention. The structure is similar to the wafer structure having the capacitor element in the tenth preferred embodiment, and the difference between the present invention and the eleventh preferred embodiment lies in the solder 1286 and the circuit layer 1265. A solder bonding metal 1288 may be further disposed to increase the bonding between the solder 1286 and the wiring structure 1265. The structure and material of the solder bonding metal 1288 are as described in the fifth preferred embodiment. Let me repeat. Twelfth Embodiment In the preferred embodiment described above, the layer formed on the protective layer is exemplified by a layer of wiring layer. However, the application of the present invention is not limited thereto, and the layer on the protective layer may also have The multilayer wiring layer, as shown in Fig. 3, shows a cross-sectional view of a wafer structure having a capacitor element according to the twelfth preferred embodiment of the present invention. The laminate 136 〇 has, for example, two wiring layers U65a, 1365b and two dielectric layers i361a, 1361b, and the wiring layer 13655 is positioned on the protective layer 1350 of the wafer 1310. The wiring structure 1335 can be connected to the wafer 131, the dielectric layer 1361b. Covering the circuit layer 1365b and the protective layer 135A, the dielectric layer 1361b has a plurality of vias 1392, exposing the circuit layer 1365b°, and the circuit layer 1365a is located on the dielectric layer 1361]3, through the dielectric layer 1361 The via 1391 can be connected to the wiring layer 1365b, the dielectric layer 1361&amp; covers the wiring layer 1365a and the dielectric layer 1361b, and the dielectric layer U61a has a plurality of openings 1362, 1363' exposing the wiring layer! 365a. In addition, a solder bonding metal 1388 may be disposed between the solder 1386 and the wiring layer 1365a, thereby increasing the bonding between the solder 1386 and the wiring layer n65a, and the structure and material of the solder bonding metal 1388 may refer to the fifth rut. The case of 'Bei' will not be repeated here. Capacitor element 83 8 稳 can be firmly bonded to wafer 153494.doc 21 201131728 1310 via solder 1383, 1386 and solder bond metal 1388. In addition, a plurality of wire bonding wires 139 形成 can be formed to be bonded to the wiring layer 1365a through the wire bonding process. For the process, the capacitor component 1380 may be bonded to the circuit layer 1365&amp; and then the wire bonding process may be performed; or the wire bonding process may be performed first, and then the capacitor element 138 is bonded to the circuit layer 1365a. In the present embodiment, the laminate layer # erected on the protective layer is exemplified by two layers of circuit layers. However, the application of the present invention is not limited thereto, and three or four layers or a plurality of other circuit layers may be disposed. Positioned in the layer on the protective layer. Conclusions The present invention utilizes a solder joint or surface mount technology to mount a dielectric chip on the wafer, so that the capacitive component can serve as a buffer between the external power supply terminal and the power supply terminal of the electronic component. In other words, this capacitive element has the function of decoupling. Therefore, in a general state, the capacitive element stores a charge amount. When a certain electronic component suddenly needs a large current, the capacitive element can immediately supply power to the electronic component, and the present invention can be bonded with a high capacitance. The capacitive component is on the wafer, so that a sudden large voltage drop between the power busbar and the ground busbar can be avoided; or when a large current flows suddenly, the capacitor can be used as a buffer to avoid the power busbar. A sudden large differential pressure is generated between the grounding busbar and the grounding busbar, which damages the electronic components. Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and any person skilled in the art can make various kinds without departing from the spirit of the invention and 153494.doc -22-201131728. The scope of the invention is defined by the scope of the appended patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a first preferred embodiment of the present invention. Fig. 1A is a cross-sectional view showing a capacitor element in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a structure of a solar cell having a capacitor element in accordance with a second preferred embodiment of the present invention. Fig. 3 is a cross-sectional view showing the structure of a day sheet having a capacitor element in accordance with a third preferred embodiment of the present invention. Figure 4 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a fourth preferred embodiment of the present invention. Figure 5 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a fifth preferred embodiment of the present invention. Figure 6 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a sixth preferred embodiment of the present invention. Figure 7 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a seventh preferred embodiment of the present invention. Figure 8 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with an eighth preferred embodiment of the present invention. Figure 9 is a cross-sectional view showing a wafer structure having a capacitor element in accordance with a ninth preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer structure having a capacitor element 153494.doc • 23-201131728 in accordance with a tenth preferred embodiment of the present invention. Figure 11 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with an eleventh preferred embodiment of the present invention. Figure 12 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with a twelfth preferred embodiment of the present invention. Fig. 13 is a cross-sectional view showing the structure of a wafer having a capacitor element in accordance with a thirteenth preferred embodiment of the present invention. [Main component symbol description] 100 wafer structure 110 wafer 120 substrate 122 electronic component 130 laminate 131 dielectric structure 135 circuit structure 136 polysilicon line 137 metal line 138 conductive plug 139 power bus 140 ground bus 150 protective layer 152 opening 154 opening 180 capacitor element

153494.doc -24- 201131728

182 electrode 183 solder 184 electrode 186 solder 190 wire conductor 210 wafer 235 line structure 250 protective layer 252 opening 280 capacitive element 283 solder 286 solder 287 metal diffusion barrier layer 288 solder joint metal 289 bonding layer 310 wafer 335 line structure 350 protective layer 352 opening 386 solder 388 solder bonding metal 390 wire bonding wire 392 wire bonding metal 410 wafer 153494.doc -25- 201131728 420 substrate 422 electronic component 430 laminate 431 dielectric structure 435 circuit structure 450 protective layer 452 opening 460 layer 461 dielectric Layer 462 Opening 463 Opening 465 Circuit Layer 466 Power Bus 467 Ground Bus 480 Capacitor 482 Electrode 484 Electrode 483 Solder 486 Solder 490 Wire 561 Dielectric Layer 563 Opening 565 Circuit Layer 583 Solder

153494.doc -26- 201131728

586 solder 587 metal diffusion barrier layer 588 solder bonding metal 589 bonding layer 610 wafer 635 circuit structure body 650 protective layer 652 opening 654 opening 660 layer 661 dielectric layer 665 circuit layer 680 capacitive element 682 electrode 683 solder 684 electrode 686 solder 690 wire wire 765 circuit layer 786 solder 788 solder joint metal 835 line structure body 850 protective layer 852 opening 153494.doc •27- 201131728 860 laminated layer 890 wire conductor 892 wire bonding metal 910 wafer 935 line structure body 950 protective layer 952 opening 965 circuit layer 966 power supply Bus 967 Ground Bus 980 Capacitor 982 Electrode 983 Fresh Material 984 Electrode 986 Solder 990 Wire Conductor 1065 Line Structure 1086 Solder 1088 Solder Bond Metal 1110 Wafer 1135 Line Structure 1150 Protective Layer 1152 Opening 1160 Laminated • 28- 153494.doc 201131728

1161a Dielectric layer 1161b Dielectric layer 1162 Opening 1163 Opening 1164 Via 965 Line layer 1166 Power bus 1167 Ground bus 1180 Capacitance element 1182 Electrode 1183 Solder 1184 Electrode 1186 Solder 1190 Wire conductor 1265 Line layer 1286 Solder 1288 Solder joint metal 13 10 Wafer 1335 Line Structure 1350 Protective Layer 1360 Laminate 1361a Dielectric Layer 1361b Dielectric Layer 1362 Opening 153494.doc -29 201131728 1363 Opening 1365a Circuit Layer 1365b Circuit Layer 1380 Capacitor Element 1386 Solder 1388 Solder Bond Metal 1390 Wire Conductor 1392 Via Hole 153494.doc •30

Claims (1)

201131728 VII. Patent application scope: 1. A circuit component, comprising: a structure comprising a substrate, a dielectric structure, a line junction layer, wherein the dielectric structure is located on the substrate, and the circuit The structure is located in the dielectric junction 4, the protective layer is located in the dielectric body and the circuit junction, and a first doorway and a second opening in the protective layer. - the first „ open ^ , , the brother - the opening and the fourth opening are respectively located in the first line of the 哕 line structure - and only the connection, the ά, the second contact, the third contact 詉 - At the four contacts, the bottom end of the first opening of the first opening, the second end of the first opening, the bottom end of the opening, the third end is located at the bottom end of the opening: The fourth pile A _ 禾 禾 four joints are located at the bottom end of the fourth opening; a circuit layer is located on the 鳟 bf layer, and the circuit layer includes a first line and a second line 匕栝 first protection On the layer, the first line is located at the second line, and the first line is connected via the first opening A point, the first "! The second contact, the first contact is connected to the second field via the first line, and the second connection is connected to the third connection via the third opening and the fourth connection (4) The fourth contact is connected by the first line: = polymer W material: material, and the pre-made capacitor element capacitive element is passed through #篦„A on the &quot;海日曰片, The circuit is connected to the first contact. 2. If the scope of the patent application includes copper, the circuit is a component, wherein the circuit is connected to the electric circuit device as described in the scope of the patent application, wherein the protection The layer 153494.doc 201131728 includes a layer of a nitrogen compound. The protective layer wherein the circuit junction is 4. The circuit component as recited in claim 3 includes an oxonium compound layer. The circuit component comprises an aluminum alloy. 6. 7. 8. The circuit component of claim 1, comprising a copper layer, such as the circuit component of claim i, including an aluminum Such as applying for a patent Shu circuit elements of the item, the gold layer comprising a β where s § Hai Xuan wiring layers wherein the circuit layer wiring layers wherein 9. The circuit component of claim </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; . 11. The circuit component of claim i, wherein the polymer layer comprises phenylcyclobutene. 12. A circuit component comprising: - a wafer comprising a substrate, a dielectric structure, a wiring structure, and a protective layer, wherein the dielectric structure is on the substrate, the wiring structure being located in the dielectric In the structure, the protective layer is located on the dielectric structure and the circuit structure, and a first opening '-second opening and a third opening σ in the protective layer are respectively located in the first part of the line structure a contact, a second contact and a third contact, the first contact 153494.doc -2- 201131728 at the bottom end of the first opening, the second contact being located at the second bottom The second contact is located at the bottom end of the third opening; the _-circuit layer is located on the protective layer, and the circuit layer includes a first line and a second line, the first line and the second line The first line is connected to the first connection via the first opening and the second connection is connected via the second opening, the first contact is connected to: the first line is connected to the second a contact, the second line is connected to the third contact via the third port; $ - a polymer layer on the first bit line and the second line; and - pre-finished capacitive element, the capacitive element is located above the upper wafer is connected to the first line through the first contact. X η. The circuit component of claim 12, wherein the circuit structure comprises copper. 14. The circuit (IV) of claim 12, wherein the protective layer comprises a layer of a ruthenium compound. 15. The circuit component of claim 12, wherein the protective layer comprises a layer of a oxysulfide compound. The circuit component of claim 12, wherein the polymer layer comprises a polynymine. Wherein the polymer comprises a circuit layer of a circuit element as described in claim 12, which comprises phenylcyclobutene. 1. The circuit component according to claim 12, which comprises the aluminum alloy. 19. The circuit component 153494.doc 201131728 as claimed in claim 12 includes a gold layer. 20. The circuit component of claim 12, wherein the circuit layer comprises a copper layer. 21. The circuit component of claim 12, wherein the circuit layer comprises a layer of a layer. 22. The circuit component of claim 12, wherein the substrate comprises ί夕. 153494.doc -4-