九、發明說明： 【發明所屬之技術領域】 本發明係關於一種基板及基板之加工方法，詳言之係 關於一種電路基板及電路基板之加工方法。 【先前技術】 參考圖1至圖7，顯不習知電路基板之加工方法之示意 圖。首先，參考圖1，提供一電路基板丨，該電路基板！具 有一芯層π、複數個第一接點12、複數個第二接點13 '一 第一防銲層】4及一第二防銲層15。該芯層u係為雙層結 構，其具有一第一表面111及一第二表面112。該等第一接 點12係為凸塊墊（Bump Pad)，其材質為銅且位於該第一 表面111。該等第一接點12係用以與一晶片之凸塊（圖中未 不）電性連接，以形成軟焊接點（S〇lder J〇int)。該等第二接 點13係為植球墊（Bau pad)，其材質為銅，且位於該第二 表面112。該第一防銲層丨4係位於該芯層丨丨之該第一表面 111，該第一防銲層14具有複數個不連續區段，以顯露出 。玄等第一接點12。該第二防銲層丨5係位於該芯層丨丨之該第 —表面112，該第二防銲層15具有複數個不連續區段，以 顯露出該等第二接點13。 接著，參考圖2，分別形成一第一化學錫層（Immersi〇n Tm Layer)21及一第二化學錫層22於該等第一接點12及該 等第二接點13上。接著，參考圖3，以濺鍍方式形成一金 屬化層23於該第二化學錫層22及該第二防銲層15上，該金 屬化層23之材質係為銅。接著，參考圖4，形成一保護膜 129565-1001116 24於s玄金屬化層23上，該伴罐胳1IX. Description of the Invention: [Technical Field] The present invention relates to a substrate and a substrate processing method, and more particularly to a method of processing a circuit substrate and a circuit substrate. [Prior Art] Referring to Figs. 1 to 7, a schematic view of a method of processing a circuit board is not known. First, referring to FIG. 1, a circuit substrate 丨, the circuit substrate is provided! There is a core layer π, a plurality of first contacts 12, a plurality of second contacts 13' a first solder mask layer 4 and a second solder resist layer 15. The core layer u is a two-layer structure having a first surface 111 and a second surface 112. The first contacts 12 are Bump Pads made of copper and located on the first surface 111. The first contacts 12 are used to electrically connect bumps (not shown) of a wafer to form solder joints. The second contacts 13 are Bau pads, which are made of copper and are located on the second surface 112. The first solder mask layer 4 is located on the first surface 111 of the core layer, and the first solder mask layer 14 has a plurality of discontinuous sections to be exposed. Xuan and other first contacts 12. The second solder mask layer 5 is located on the first surface 112 of the core layer, and the second solder mask layer 15 has a plurality of discontinuous sections to expose the second contacts 13. Next, referring to FIG. 2, a first chemical tin layer (Immersi〇n Tm Layer) 21 and a second chemical tin layer 22 are formed on the first contacts 12 and the second contacts 13 respectively. Next, referring to Fig. 3, a metallization layer 23 is formed on the second chemical tin layer 22 and the second solder resist layer 15 by sputtering, and the material of the metallization layer 23 is copper. Next, referring to FIG. 4, a protective film 129565-1001116 24 is formed on the s-metallization layer 23, the companion tank 1
这保。蔓獏24係為一乾臈（D FUm)。接著，參考圖5，以電 式开>成一金屬電鍍層25 於該第一化學錫層21上，該今屬雷 4金屬電鍍層25之材質係為錫。 接著，參考圖6,移除該保護膜24。最後，參考圖7，以姓 刻方式移除該金屬化層23’以得到—加工後之電路基板 該“電路基板之加工方法之缺點如下。在該等第一接 點12上’係先形成該第一化學錫層幻，之後再形成該金眉 電鍍層25。因此，該金屬電鍍層25之材質受限於該第一化 子錫層2 1，只能為錫。亦即，該第一化學錫層2丨上只能再 電鍍錫。如此導致該電路基板！在表面處理（Mdd Finishing)時材質之選擇性較少。 因此，有必要提供一種創新且具進步性的電路基板及電 路基板之加工方法’以解決上述問題。 【發明内容】 本發明提供一種電路基板之加工方法，其包括以下步 驟：（a)提供一電路基板，該電路基板包括一芯層、複數個 第一接點及複數個第二接點，該芯層具有一第一表面及一 第二表面’該等第一接點係位於該第一表面，該等第二接 點係位於該第二表面；（b)形成一金屬化層於該芯層之該第 二表面上’以覆蓋該等第二接點；形成一保護膜於該金 屬化層上；（d)形成一金屬電鍍層於該等第一接點上；（e) 移除該保護膜；（f)形成一可剝膠（Peelable Solder Mask)於 該芯層之該第—表面上，以覆蓋該金屬電鍍層；（g)移除該 129565-1001Π6 -8 - 金屬化層，（h)形成一化學錫層（j_ersi〇n 丁^ Layer)於該 等第一接點上，及⑴移除該可剝膠，以得到一加工後之電 路基板。 本發明另提供-種電路基板，其包括一芯層、複數個第 接點複數個第二接點、一金屬電鍍層及一化學錫層。 該芯層具有一第一表面及一第二表面。該等第一接點係位 於該芯層之第-表面。該等第二接點係位於該3層之第二 表面。該金屬電鍍層係位於該等第一接點上。該化學錫層 係位於該等第二接點上。 藉此，該金屬電鍍層係直接形成於該等第一接點上，而 非在省等第一接點上形成一化學錫層後才形成一金屬電 鍍層，此一設計之目的是因為該等第一接點之材質通常為 銅，而在銅的表面所能進行的表面處理較化學錫來得多樣 化且可選用的材質也較多，因此本發明有助於使該電路 基板具有較多樣化之表面處理。 【實施方式】 參考圖8至圖16，顯示本發明電路基板之加工方法之示 思圖。首先，參考圖8,提供一電路基板3，該電路基板3 包括一芯層3 1、複數個第一接點32及複數個第二接點33。 在本實施例中，該電路基板3更包括一第一防銲層34及一 第二防銲層3 5。 在本實施例中，該電路基板3係為BT(Bismaieimide Triacine)基板。然而在其他應用中，該電路基板3係可為 環氧玻璃（Glass Epoxy)基板。該芯層3丨具有一第一表面 129565-1001116 -9- 1358108This guarantee. The vine 24 is a dry 臈 (D FUm). Next, referring to FIG. 5, a metal plating layer 25 is electrically formed on the first chemical tin layer 21, and the material of the current metal plating layer 25 is tin. Next, referring to FIG. 6, the protective film 24 is removed. Finally, referring to FIG. 7, the metallization layer 23' is removed by a surname to obtain a processed circuit substrate. The disadvantages of the "processing method of the circuit substrate are as follows. On the first contacts 12, the system is formed first. The first chemical tin layer is formed, and then the gold eyebrow plating layer 25 is formed. Therefore, the material of the metal plating layer 25 is limited to the first chemical tin layer 2 1, which can only be tin. Only one tin can be electroplated on a chemical tin layer. This results in a circuit substrate! The material selectivity is less in the case of surface treatment (Mdd Finishing). Therefore, it is necessary to provide an innovative and progressive circuit substrate and circuit. The present invention provides a method for processing a circuit substrate, comprising the steps of: (a) providing a circuit substrate comprising a core layer and a plurality of first connections a plurality of second contacts, the core layer having a first surface and a second surface, wherein the first contacts are located on the first surface, and the second contacts are located on the second surface; b) forming a metallization On the second surface of the core layer to cover the second contacts; forming a protective film on the metallization layer; (d) forming a metal plating layer on the first contacts; Removing the protective film; (f) forming a peelable solder (Peelable Solder Mask) on the first surface of the core layer to cover the metal plating layer; (g) removing the 129565-1001Π6 -8 - a metallization layer, (h) forming a chemical tin layer (j_ersi〇n) layer on the first contacts, and (1) removing the strippable glue to obtain a processed circuit substrate. A circuit substrate is provided, comprising: a core layer, a plurality of second contacts, a plurality of second contacts, a metal plating layer and a chemical tin layer. The core layer has a first surface and a second surface. The first contact is located on the first surface of the core layer. The second contacts are located on the second surface of the third layer. The metal plating layer is located on the first contacts. The chemical tin layer is located The second contact is formed. Thereby, the metal plating layer is directly formed on the first contacts, instead of the first connection A metal plating layer is formed on the surface of a chemical tin layer. The purpose of this design is because the material of the first contact is usually copper, and the surface treatment on the surface of copper is more diversified than that of chemical tin. Moreover, the material used is also more, so the present invention helps to make the circuit substrate have a variety of surface treatments. [Embodiment] Referring to FIG. 8 to FIG. 16, a schematic diagram of a processing method of the circuit substrate of the present invention is shown. First, referring to FIG. 8, a circuit substrate 3 is provided. The circuit substrate 3 includes a core layer 31, a plurality of first contacts 32, and a plurality of second contacts 33. In this embodiment, the circuit substrate 3 Further, a first solder resist layer 34 and a second solder resist layer 35 are included. In the embodiment, the circuit board 3 is a BT (Bismaieimide Triacine) substrate. However, in other applications, the circuit substrate 3 may be a Glass Epoxy substrate. The core layer 3 has a first surface 129565-1001116 -9- 1358108
3 11及苐—表面3 12，在本實施例中，該芯層3〗係為雙層 結構，然而在其他應用中，該芯層3 1係可為單層或三層以 上之結構。該等第一接點32係位於該第一表面3〗}。在本 實施例中，該等第一接點32係為凸塊墊（Bump Pad)，且材 質係為鋼。該等第一接點32係用以與一晶片之^塊（圖令 未7電性連《’以形成軟焊接點（Soldei· ]〇int)。該等第二 接點33係位於該第二表面3 12。在本實施例中該等第二 接點33係為植球塾伽丨IPad)，且材質係為銅。 在本實施例中，s亥第一防鲜層34係位於該芯層3 1之該第 -表面311 ’該第一防銲層34具有複數個不連續區段以 顯露出該等第一接點32。在本實施例中，該第二防辉層35 係位於該芯層31之該第二表面312，該第二防鲜心具有 複數個不連續區段，以顯露出該等第二接點33。 接著，參考圖9，形成一金屬化層41於該芯層31之該第 二表面312上，以覆蓋該等第二接點”。在本實施例中' 該金屬化層“更覆蓋該第二防銲㈣，該金屬化層4ι係利 用減鑛（S_ter)方切成，且材質係為鋼。 接著’參考圖形成—保護膜42於該金屬化層Ο上。 =本實施例中，該保護膜42係為—乾膜⑼y Fnm)。接 著參考圖11，以電鑛方式形成—金屬電錢層^於該等第 -接點32上。在本實施例中，該金屬電鍍層43之材料 錫。然而在其他應用中’該金屬電鍵層43之材料係可為錫 錯、錫銀、錄金或㈣金1著，參考_，移除該 膜42 〇 129565-1001116 -10- 1358108 接著，參考圖13，形成一可剝膠（peeiabje Solder Mask)44於該芯層31之該第一表面311上，以覆蓋該金屬電 鍍層43。在本實施例中，該可剝膠44係購於阿牦科技公司 (ATOTECH Deutschland GmbH)，型號為 SD2990T。在本實3 11 and 苐 - surface 3 12, in the present embodiment, the core layer 3 is a two-layer structure, however, in other applications, the core layer 31 may be a single layer or more than three layers. The first contacts 32 are located on the first surface 3]. In the present embodiment, the first contacts 32 are Bump Pads and the material is steel. The first contacts 32 are used to be electrically connected to a wafer (the figure is not electrically connected to 'to form a solder joint (Soldei·] 〇int). The second contacts 33 are located at the first Two surfaces 3 12. In the present embodiment, the second contacts 33 are ball-gathered 丨 丨 IPad), and the material is copper. In this embodiment, the first anti-friction layer 34 is located on the first surface 311 of the core layer 31. The first solder resist layer 34 has a plurality of discontinuous sections to reveal the first connections. Point 32. In this embodiment, the second anti-glaze layer 35 is located on the second surface 312 of the core layer 31, and the second anti-fresh core has a plurality of discontinuous sections to expose the second contacts 33. . Next, referring to FIG. 9, a metallization layer 41 is formed on the second surface 312 of the core layer 31 to cover the second contacts. In the embodiment, the metallization layer further covers the Second, the anti-welding (four), the metallization layer 4ι is cut by the ore reduction (S_ter) square, and the material is steel. Next, a reference pattern is formed - a protective film 42 on the metallization layer. In the present embodiment, the protective film 42 is a dry film (9) y Fnm). Next, referring to Fig. 11, a metal electric money layer is formed by electro-minening on the first-contact 32. In this embodiment, the material of the metal plating layer 43 is tin. However, in other applications, the material of the metal key layer 43 may be tin-tin, tin-silver, gold-plated or (iv) gold, reference _, the film is removed 42 〇 129565-1001116 -10- 1358108 Next, reference figure 13. A peeling adhesive (peeiabje Solder Mask) 44 is formed on the first surface 311 of the core layer 31 to cover the metal plating layer 43. In the present embodiment, the strippable adhesive 44 is commercially available from ATOTECH Deutschland GmbH under the model number SD2990T. In this reality
施例中’該可剝膠44更覆蓋該第一防銲層34，該可剝谬係 利用塗佈（Coating)方式形成於該芯層3 1之該第一表面3 11 上。接著’參考圖14 ’移除該金屬化層41。在本實施例 中’該金屬化層41係利用蝕刻方式移除。接著，參考圖 1 5 ’形成一化學錫層（lmmersi〇n Tin Layer)45於該等第二 接點3 3上。最後’參考圖16，移除該可剝膠44，以得到一 加工後之電路基板4。 在本加工方法中，該可剝膠44可抵擋形成該化學錫層Μ 之高溫強酸環境，故用以覆蓋且保護該金屬電鍍層43。此 外，該可剝膠44移除後不會殘留在該金屬電鍍層“上，故 不影響該電路基板4之後續處理。In the embodiment, the strippable adhesive 44 further covers the first solder resist layer 34, and the strippable strip is formed on the first surface 3 11 of the core layer 31 by a coating method. The metallization layer 41 is then removed with reference to Figure 14'. In the present embodiment, the metallization layer 41 is removed by etching. Next, a chemical tin layer 45 is formed on the second contacts 3 3 with reference to FIG. Finally, referring to Fig. 16, the peelable adhesive 44 is removed to obtain a processed circuit substrate 4. In the processing method, the strippable adhesive 44 can withstand the high temperature and strong acid environment forming the chemical tin layer, so as to cover and protect the metal plating layer 43. Further, the peelable adhesive 44 does not remain on the metal plating layer after removal, so that the subsequent processing of the circuit substrate 4 is not affected.
此外，該金屬電鍍層43係直接形成於該等第一接點32 上，而非在該等第一接點32上形成一化學錫層後，才形成 該金屬電鍍層43，此一設計之目的是因為該等第一接點32 之材質大多為鋼，而在銅的表面所能進行的表面處理較化 學錫來得多樣化’且可選料材質也較多，因此本發明之 方法有助於使該電路基板4具有較多樣化之表面處理。 再參考圖16，顯示本發明加工後之電路基板之示意圖。 該電路基板4包括一芯層31、複數個第一接點32、複數個 第二接點33、-金屬電鍵層43及—化學錫層心在本實施 129565-1001116 -11- 1358108 ♦ » 例中，該電路基板4更包括—第—防銲層34及—第二防鲜 層35。 。玄心層3〗具有一第一表面311及一第二表面312。在本實 把例中’該心層31之材質係為Βτ。然而在其他應用中該 心層3 1之材貝係可為環氧玻璃。在本實施例中該芯層w 係為雙層結構，然而在其他應用中，該芯層3 1係可為單層 或三層以上之結構。該等第一接點32位於該芯層31之該第 一表面311。在本實施例中，該等第一接點“係為凸塊 墊’且材質係為銅。該等第—接點32係用以與—晶片之凸 塊（圖中未示）電性連接，以形成軟焊接點（Solder J〇lnt)。 。亥等第一接點3 3位於該芯層3 1之該第二表面3丨2。在本實 施例中，該等第二接點33係為植球塾，且材f係為鋼。該 金屬電鍍層43位於該等第一接點32上，且該金屬電鍵層43 係接觸該等第一接點32。在本實施例中，該金屬電鍵層^ 之材料係為錫，其係直接電鍍於該等第一接點32上。然而 在其他應用申，該金屬電鍍層43之材料可為錫鉛、錫銀、 鎳金或鎳鈀金。該化學錫層45位於該等第二接點33上。 在本實施例中，該第一防銲層34係位於該芯層31之該第 表面311，忒第一防銲層34具有複數個不連續區段，以 負路出該等第一接點32。在本實施例中，該第二防銲層35 係位於該芯層31之該第二表面312，該第二防銲層^具有 複數個不連續區段，以顯露出該等第二接點33。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，f於此技術之人士對上述實施例進 129565-100]] 16 -12- 1358108 本發明之權利範圍應 之加工方法之示意圖；及 方法之示意圖。In addition, the metal plating layer 43 is directly formed on the first contacts 32, instead of forming a chemical tin layer on the first contacts 32, the metal plating layer 43 is formed. The purpose is that the material of the first contact 32 is mostly steel, and the surface treatment that can be performed on the surface of the copper is more diversified than that of the chemical tin, and the material of the material is also more, so the method of the invention is helpful. The circuit substrate 4 is provided with a more diverse surface treatment. Referring again to Figure 16, a schematic diagram of the processed circuit substrate of the present invention is shown. The circuit substrate 4 includes a core layer 31, a plurality of first contacts 32, a plurality of second contacts 33, a metal key layer 43 and a chemical tin layer in the present embodiment 129565-1001116 -11- 1358108 ♦ » The circuit substrate 4 further includes a first-pre-solder layer 34 and a second anti-fresh layer 35. . The mysterious layer 3 has a first surface 311 and a second surface 312. In the present example, the material of the core layer 31 is Βτ. However, in other applications, the shell of the core layer 31 may be epoxy glass. In the present embodiment, the core layer w is a two-layer structure, however, in other applications, the core layer 31 may be a single layer or a structure of three or more layers. The first contacts 32 are located on the first surface 311 of the core layer 31. In this embodiment, the first contacts are “bump pads” and the material is copper. The first contacts 32 are used to electrically connect with the bumps (not shown) of the wafer. To form a soft solder joint (Solder J〇lnt). The first contact 3 3 such as Hai is located on the second surface 3丨2 of the core layer 31. In this embodiment, the second contacts 33 The material is f. The metal plating layer 43 is located on the first contacts 32, and the metal key layer 43 is in contact with the first contacts 32. In this embodiment, The material of the metal key layer is tin, which is directly plated on the first contacts 32. However, in other applications, the material of the metal plating layer 43 may be tin-lead, tin-silver, nickel-gold or nickel. The first solder resist layer 34 is located on the first surface 311 of the core layer 31, and the first solder resist layer 34 is disposed on the second contact 33. And having a plurality of discontinuous sections to negatively exit the first contacts 32. In this embodiment, the second solder resist layer 35 is located on the second surface 312 of the core layer 31, the second weld The layer has a plurality of discontinuous sections to reveal the second contacts 33. However, the above embodiments are merely illustrative of the principles of the present invention and its effects, and are not intended to limit the present invention. A schematic diagram of a processing method to which the above-described embodiments are directed to 129565-100]] 16 -12- 1358108, and a schematic diagram of the method.
行修改及變化仍不脫本發明之精神 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1至圖7顯示習知電路基板 圖8至圖16顯示本發明電路基板之加工 【主要元件符號說明】 1 電路基板 2 習知電路基板 3 電路基板 4 本發明電路基板 11 芯層 12 第一接點 13 第二接點 14 第一防銲層 15 第二防銲層 21 第一化學錫層 22 第二化學錫層 23 金屬化層 24 保護膜 25 金屬電鍍層 31 K層 32 第一接點 33 第二接點 34 第一防銲層 129565-1001116 13 1358108 35 第二防銲層 41 金屬化層 42 保護膜 43 金屬電鍍層 44 可剝膠 45 化學錫層 111 第一表面 112 第二表面 311 第一表面 312 第二表面 129565-1001116 -14The modifications and variations of the present invention are not limited to the scope of the invention as set forth in the appended claims. 1 to 7 show a circuit board of the present invention. FIG. 11 core layer 12 first contact 13 second contact 14 first solder resist layer 15 second solder resist layer 21 first chemical tin layer 22 second chemical tin layer 23 metallization layer 24 protective film 25 metal plating layer 31 K Layer 32 First Contact 33 Second Contact 34 First Solder Mask 129565-1001116 13 1358108 35 Second Solder Mask 41 Metallization Layer 42 Protective Film 43 Metal Plating Layer 44 Strippable 45 Chemical Tin Layer 111 First Surface 112 second surface 311 first surface 312 second surface 129565-1001116 -14