1355724 ASEK1996 25035twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種覆晶封裝結構及其製作方法，且 特別是有關於一種適用於降低基板翹曲之覆晶封裝結構及 其製作方法。 【先前技術】 覆晶封裝為目前最廣泛使用之半導體封裝技術。在覆 曰b封裝技術_，通常會形成一底膠(underfill)填充於覆晶晶 片與基板之間。而在進行烘烤製程使底膠熟化時，由於基 板與底膠之熱膨脹係數不同，因此，會導致基板發生赵曲 的情形。此外，在回焊(reflow)製程後，晶粒與基板之熱膨 脹係數差異（CTEdismatch)也是造成基板翹曲的原因。為 防止基板發生翹曲的情形，通常會在基板上設置散熱片及 散熱環，以降低基板勉曲之程度。 圖1繪示為習知之一種覆晶封裝結構之剖面示意圖。 請參考圖1所示，此覆晶封裝結構100主要包含一基板 110、一覆晶晶片120、一底膠130以及一散熱板14〇。其 中，基板110具有一上表面111以及一下表面112，而覆 晶晶片120係位於基板11〇之上表面1U。此覆晶晶片12〇 具有一主動面121以及一背面122。主動面121上形成有 多個凸塊123，以接合覆晶晶片120與基板11〇。底膠13〇 係填充於覆晶晶片120與基板110之間。而散熱板140係 藉由一導熱介面物質124熱耦合於覆晶晶片12〇之背面 122 ’以加強覆晶晶片120之散熱效果。且散熱板14〇具有 1355724 ASEK1996 25035twf.doc/n 一結合部141，此結合部14l係以一黏著膠113結合於基 板110之上表面111的周圍。最後，於基板110之下表面 * 112設置多個銲球150，以供外接一電路板。 雖然在基板110上設置具有結合部M1之散熱板14〇 *可降低基板110之起曲現象，然而，散熱板之使用對於大 尺寸產品的翹曲狀況之改善有限，且亦會導致生產成本的 增加。此外’在封裝製程中需將散熱板14〇之結合部141 • 平整地貼附於基板之上表面ill亦增加製程之困難度。 【發明内容】 本發明之目的是提供一種降低基板翹曲之覆晶封裝 • 結構及其製作方法’以解決覆晶封裝結構中基板翹曲之問 題。 為達上述或是其他目的，本發明提出一種降低基板翹 曲之覆Bg封裝結構，其包括一基板、一晶片（reai die)、多 個第凸塊、一虛晶片（dummy die)以及多個第二凸塊。基 板具有一第一表面以及與其相對之一第二表面。晶片是位 於基板之第一表面上，且具有一主動面。這些第一凸塊是 配置於晶片之主動面與基板之第一表面之間，使晶片藉由 运二第凸塊電性連接於基板之第一表面。虛晶片是位於 基板之第二表面上，且對應於晶片。多個第二凸塊是配置 於虛晶片與基板的第二表面之間，使虛晶片藉由這些第二 凸塊連接於基板之第二表面。 在本發明之一實施例中’虛晶片之尺寸係小於晶片之 尺寸。 1355724 ASEK1996 25035twf.doc/n 在本發明之一實施例中，降低基板翹曲之覆晶封裝結 構更包括-第-底膠以及一第二底膠。第一底膠係填^ 晶片與基板的第一表面之間，並包覆上述第一凸塊。而此 第二底膠係填充於虛晶片與基板的第二表面之間，且包覆 * 上述第二凸塊。 - /在本發明之一實施例中，第二底膠之玻璃化轉換溫度 係大於第一底膠之玻璃化轉換溫度。 • 為達上述或是其他目的，本發明另提出一種降低基板 龜曲之覆晶封裝結構，其包括一基板、—晶片、多數個第 一凸塊、一第一底膠以及一第二底膠。基板具有一第一表 • 面以及與其相對之一第二表面。晶片是位於基板之第一表 • 面上，且具有一主動面。這些第一凸塊是配置於晶片之主 動面與基板的第一表面之間，使晶片藉由這些第一凸塊電 性連接於基板之第一表面。第一底膠係填充於晶片及基板 之第一表面，且包覆上述第一凸塊。第二底膠係設置於基 板之第二表面，且對應於第一底膠。其中，第二底膠之玻 璃化轉換溫度係大於第一底膠之玻璃化轉換溫度。 在本發明之一實施例中，降低基板翹曲之覆晶封裝結 構更包括一虛晶片以及多個第二凸塊。其中，虛晶片位於 基板之第二表面上’且對應於晶片。而這些第二凸塊配置 於虛晶片與基板的第二表面之間，使虛晶片藉由這些第二 凸塊連接於基板之第二表面。 在本發明之一實施例中，虛晶片之尺寸係小於晶片之 尺寸。 1355724 ASEK1996 25035twf.doc/n 為達上述或是其他目的，本發明再提出一種降低基板 翹曲之覆晶封裝結構的製作方法，包括下列步驟。首先， 提供一基板、一晶片以及一虛晶片。其中，此基板具有一 弟一表面以及與其相對之一第二表面，該晶片具有一主動 面以及多數個配置於主動面上之第一凸塊，且虛晶片之一 表面上配置有多個第二凸塊。之後，將晶片之主動面與基 板之第一表面相對’並回焊這些第一凸塊，使晶片藉由這 些第一凸塊而以覆晶接合的方式配置於基板之第一表面 上。最後，將虛晶片配置於基板的第二表面上，並回焊這 些第一凸塊，使虛晶片藉由這些第二凸塊而以覆晶接合的 方式配置於基板之第二表面上。 在本發明之一實施例中，覆晶封裝結構的製作方法更 包括下列步驟。首先，填充一第一底膠於晶片與基板的第 —表面之間，以使第一底膠包覆這些第一凸塊。之後， 進行一加熱製程’以固化第—底膠。 在本發明之一實施例中，覆晶封裝結構的製作方法更 包括下列步驟。首先’填充_第二底#於虛晶片與基板的 第二表面之間，以使第二底膠包覆這些第二凸塊。之後， 進行一加熱製程’以固化第二底膠。 /在本發明之-實施例中，第二底膠之玻璃化轉換溫度 係大於第一底膠之玻璃化轉換溫度。 在本發明之一實施例中，虛晶片之尺寸係小於晶片之 尺寸。 為達上述或是其他目的，本發明更提出一種降低基板 ASEKI996 25035twf.d〇c/n 趣曲之覆晶封裝結構的製作方法，包括下列 2=以及一晶片。其中，此基板具有-第-上 一 /、目、之第一表面；此晶片具有一主動面以及多數 主動面上之第—凸塊。之後’將晶片之主動面盥 =第-表面相對’並回焊這些第一凸塊，使晶片藉由 k二苐-凸塊而以覆晶接合的方式配置於基板的第一表面 ^。接下來’填充-第-底膝於晶片與基板的第一表面之 :曰’以使第-底勝包覆這些第—凸塊。之後，進行一加敎 ΐ!二第一底膠。接著，於基板之第二表面上形成 對應於第-底膠之第二底膠。最後， 以固化第二底膠。 …^ 在^發明之-實施例中，第二底膠之玻璃化轉換溫度 係大於弟一底膠之玻璃化轉換溫度。 本發明之降低基板趣曲之覆晶封裝結構及其製作方 ^主要是在基板的背面設置—與其覆晶接合之虚晶片及/ 或進行底紅填充、簡㈣，絲板產纽向的翹曲， 以抑制基板在經過回焊及點膠製域所產生喃曲，進而 解決習知之覆晶塊結構巾基她曲的問題。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易Jt下文特舉較佳實施例，並合所附圖式，作詳細說 明如下。 【實施方式】 圖2A〜2H繪示為根據本發明之一實施例的一種降低基 板輕曲之覆晶骑結構的製作方法之流程剖面示意圖。肯 1355724 ASEK1996 25035twf.doc/n 先，請參考圖2A所示，提供一基板210、一晶片220以及 一虚晶片230。此基板210具有一第一表面210a以及與其 相對之一第二表面210b ;此晶片220具有一主動面220a 以及多個配置於主動面220a上之第一凸塊222 ;而虛晶片 230之表面230a上配置有多個第二凸塊232。 之後，如圖2B所示，將晶片220的主動面220a與基 板210的第一表面210a相對，並回焊這些第一凸塊222， 使晶片220藉由這些第一凸塊222而以覆晶接合的方式配 置於基板210之第一表面210a上。如圖2B所示，由於基 板210與晶片220之熱膨脹係數不同，因此，基板21〇在 經過回焊製程後會有向下翹曲的現象。 為改善基板210在經過回焊製程後所產生之向下翹曲 的現象，如圖2C所示，本發明先將基板21〇倒置，之後， 將虛晶片230配置於基板210的第二表面210b上，且回焊 這些苐一凸塊232，使虛晶片230藉由這些第二凸塊232 而以覆晶接合的方式配置於基板21〇之第二表面2i〇b上。 如圖2D所示，由於基板21〇與虛晶片23〇之熱膨脹係數 不同，所以，基板210在經過回焊製程後同樣會有向下翹 曲的現象，而即可藉此克服先前圖中基板所產生 的翹曲，並將基板210扳平。如此，即完成本發明之降低 基板翹曲之覆晶封裝結構的製作方法的大致流程◊更進一 步而言，虛晶片230配置於基板21〇之第二表面21〇b上的 位置係對應於晶片220配置於基板21〇之第一表面應 上的位置，且虛晶片230的尺寸最好是小於晶片22〇之尺 1355724 ASEK1996 25035twf.doc/n 寸，以有助於將基板210原先所產生的翹曲扳平。 為保護連接於基板210與晶片220之間的第一凸塊 222免於受損及受潮，在完成圖2D所示之步驟後，如圖 2E所示，可於晶片220與基板21〇的第一表面21〇a之間 - 填充一第一底膠240，以使第一底膠240包覆這些第一凸 塊222。之後，請參考圖π所示，進行一加熱製程，以固 化此第一底膠240。 鲁然而，第一底膠240在經過加熱製程後，如圖2F所 示，基板210會再度產生向下翹曲的現象。因此，請參考 圖2G所示，可先將基板21〇倒置’並於虛晶片23〇與基 • 板210的第二表面21〇b之間填充一第二底膠25〇,以使第 . 二底膠25〇包覆這些第二凸塊232。之後，如圖2ίί所示， 進行一加熱I程，以固化此第二底膠250。由於第二底膠 250在經過加熱製程後，基板21〇會再度產生向下翹曲的 現象，所以，可藉此克服先前圖2F中基板21〇所產生的 翹曲，並將基板210扳平。由於所選用之第二底膠25〇其 • 材料特性會影響到基板210翹曲之程度，所以，使用者^ 選用具有不同玻璃化轉換溫度之第二底膠25〇，以改善並 控制基板210翹曲之程度。在本發明之一實施例中，^二 底膠250的玻璃化轉換溫度最好是大於第—底膠24〇之玻 璃化轉換溫度。如此，在第二底膠250經過點膠、加熱的 製程後，基板210所產生之翹曲程度可抑制第一底膠 供烤後所產生之基板210翹曲的現象，進而將基板2\〇扳 平0 (S ) 11 1355724 ASEK1996 25035twf.doc/n 圖3A〜3F繪示為根據本發明之另一實施例的一種降 低基板翹曲之覆晶封裝結構的製作方法之流程剖面示意 圖。首先，請參考圖3A所示，提供一基板21〇以及一晶 片220。此基板210具有一第一表面2i〇a以及與其相對之 一第二表面210b ;而此晶片220具有一主動面220a以及 多個配置於主動面220a上之第一凸塊222。之後，請參考 圖3B所示，將晶片220的主動面220a與基板210的第一 表面210a相對，並回焊這些第一凸塊222，.使晶片22〇藉 由這些第一凸塊222而以覆晶接合的方式配置於基板21〇 '之弟一表面210a上。如圖3B所示，由於基板210與晶片 220之熱膨脹係數不同，因此，基板21〇在經過回焊製程 後會有向下翹曲的現象。 為保護連接於基板210與晶片220之間的第一凸塊 222免於受損及受潮’在完成圖3B所示之步驟後，如圖 3C所示，在晶片220與基板210的第一表面210a之間填 充一第一底膠240，以使第一底膠240包覆這些第一凸塊 222。之後’ s青參考圖3D所示’進行一加熱製程，以固化 此第一底膠240。如圖3D所示，在經過第一底膠240之填 充及加熱製程後，基板210向下翹曲的程度更為明顯。 接下來’請參考圖3E所示，於基板210的第二表面 210b上形成一對應於第一底膠24〇之第二底膠25〇，。最 後，請參考圖3F所示，進行一加熱製程，固化此第二底 膠250’ ’以藉此第二底膠25〇,之填充及加熱製程克服先前 圖3D之步驟中所造成之基板21〇翹曲的現象，進而將基 板210板平。 12 1355724 ASEK1996 25035twf.doc/n 综上所述’本發明之降低基板翹曲之覆晶封裝結構及 其製作方法主要是在基板的背面設置一與其覆晶接合之虛 晶片及/或進行底膠之填充、烘烤製程，使基板產生反向的 翹曲，以抑制基板在經過回焊及點膠製程後所產生的翹 ' =，進而將基板扳平。此外，使用者可選擇不同尺寸之虛 晶片以及具有不同破璃化轉換溫度的底膠，以控制基板反 向翹曲之程度，進而將基板扳平。 • 雖然本發明已以較佳實施例揭露如上，然其並非用以 =本發明、:任何熟習此技藝者，在频離本發明之精神 乾圍内’胃可作些許之更動與潤飾，因此 -_當視後附之申請專利範圍所界定者為準。之保5隻 . .【圖式簡單說明】 】為，之一種覆晶封裝結構之剖面示意圖。 圖2Α〜2Η繪示為根據本發明之 基板鍾曲之覆晶封裝結構的製作方. 土降低 _ 3Α〜3F綠示為根據本發 。 •:一覆晶封裝結構的製作1: = = 【主要元件符號說明】 100 覆晶封裝結構 110 基板 111 上表面 112 下表面 113 黏著膠 < S ) 13 1355724 ASEK1996 25035twf.doc/n1355724 ASEK1996 25035twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip package structure and a method of fabricating the same, and more particularly to a flip chip package suitable for reducing substrate warpage Structure and its making method. [Prior Art] Flip chip packaging is currently the most widely used semiconductor packaging technology. In the overlay b package technique, an underfill is usually formed to fill the flip chip and the substrate. When the baking process is performed to make the primer mature, the thermal expansion coefficient of the substrate and the primer is different, which may cause the substrate to sway. In addition, the difference in thermal expansion coefficient between the die and the substrate (CTEdismatch) is also responsible for the warpage of the substrate after the reflow process. In order to prevent the substrate from warping, a heat sink and a heat dissipation ring are usually disposed on the substrate to reduce the degree of distortion of the substrate. FIG. 1 is a schematic cross-sectional view showing a conventional flip chip package structure. Referring to FIG. 1 , the flip chip package structure 100 mainly includes a substrate 110 , a flip chip 120 , a primer 130 , and a heat dissipation plate 14 . The substrate 110 has an upper surface 111 and a lower surface 112, and the flip chip 120 is located on the upper surface 1U of the substrate 11A. The flip chip 12A has an active surface 121 and a back surface 122. A plurality of bumps 123 are formed on the active surface 121 to bond the flip chip 120 and the substrate 11A. The primer 13 is filled between the flip chip 120 and the substrate 110. The heat sink 140 is thermally coupled to the back surface 122' of the flip chip 12 by a thermally conductive interface material 124 to enhance the heat dissipation effect of the flip chip 120. And the heat dissipating plate 14 has a joint portion 141 of 1355724 ASEK1996 25035 twf.doc/n, and the joint portion 14l is bonded to the periphery of the upper surface 111 of the substrate 110 with an adhesive 113. Finally, a plurality of solder balls 150 are disposed on the lower surface *112 of the substrate 110 for externally connecting a circuit board. Although the provision of the heat dissipation plate 14〇* having the joint portion M1 on the substrate 110 can reduce the phenomenon of the deflection of the substrate 110, the use of the heat dissipation plate has limited improvement in the warpage condition of the large-sized product, and also causes production cost. increase. In addition, it is necessary to attach the bonding portion 141 of the heat dissipation plate 14 to the upper surface ill of the substrate in the packaging process, which also increases the difficulty of the process. SUMMARY OF THE INVENTION An object of the present invention is to provide a flip chip package structure and a fabrication method thereof for reducing warpage of a substrate to solve the problem of substrate warpage in a flip chip package structure. To achieve the above or other objects, the present invention provides a Bg package structure for reducing warpage of a substrate, comprising a substrate, a reai die, a plurality of bumps, a dummy die, and a plurality of Second bump. The substrate has a first surface and a second surface opposite thereto. The wafer is on the first surface of the substrate and has an active surface. The first bumps are disposed between the active surface of the wafer and the first surface of the substrate, such that the wafer is electrically connected to the first surface of the substrate by the second bump. The dummy wafer is on the second surface of the substrate and corresponds to the wafer. The plurality of second bumps are disposed between the dummy wafer and the second surface of the substrate, and the dummy wafers are connected to the second surface of the substrate by the second bumps. In one embodiment of the invention, the size of the dummy wafer is less than the size of the wafer. 1355724 ASEK1996 25035 twf.doc/n In one embodiment of the invention, the flip chip package structure for reducing substrate warpage further comprises a - primer and a second primer. The first primer is filled between the wafer and the first surface of the substrate and covers the first bump. The second primer is filled between the dummy wafer and the second surface of the substrate, and is coated with the second bump. - / In one embodiment of the invention, the glass transition temperature of the second primer is greater than the glass transition temperature of the first primer. For the above or other purposes, the present invention further provides a flip chip package structure for reducing substrate tort, comprising a substrate, a wafer, a plurality of first bumps, a first primer, and a second primer. . The substrate has a first surface and a second surface opposite thereto. The wafer is located on the first surface of the substrate and has an active surface. The first bumps are disposed between the active surface of the wafer and the first surface of the substrate, and the wafers are electrically connected to the first surface of the substrate by the first bumps. The first primer is filled on the first surface of the wafer and the substrate, and covers the first bump. The second primer is disposed on the second surface of the substrate and corresponds to the first primer. Wherein, the glass transition temperature of the second primer is greater than the glass transition temperature of the first primer. In an embodiment of the invention, the flip chip package structure for reducing the warpage of the substrate further comprises a dummy wafer and a plurality of second bumps. Wherein the dummy wafer is on the second surface of the substrate' and corresponds to the wafer. The second bumps are disposed between the dummy wafer and the second surface of the substrate, such that the dummy bumps are connected to the second surface of the substrate by the second bumps. In one embodiment of the invention, the size of the virtual wafer is less than the size of the wafer. 1355724 ASEK1996 25035twf.doc/n To achieve the above or other objects, the present invention further provides a method of fabricating a flip chip package structure for reducing substrate warpage, comprising the following steps. First, a substrate, a wafer, and a dummy wafer are provided. The substrate has a surface and a second surface opposite thereto. The wafer has an active surface and a plurality of first bumps disposed on the active surface, and a plurality of surfaces are disposed on one surface of the dummy wafer. Two bumps. Thereafter, the active surface of the wafer is opposed to the first surface of the substrate and the first bumps are reflowed so that the wafer is disposed on the first surface of the substrate by flip chip bonding by the first bumps. Finally, the dummy wafer is disposed on the second surface of the substrate, and the first bumps are reflowed, and the dummy wafer is disposed on the second surface of the substrate by flip chip bonding by the second bumps. In an embodiment of the invention, the method of fabricating the flip chip package structure further comprises the following steps. First, a first primer is filled between the wafer and the first surface of the substrate such that the first primer covers the first bumps. Thereafter, a heating process is performed to cure the first primer. In an embodiment of the invention, the method of fabricating the flip chip package structure further comprises the following steps. First, the 'filler_second bottom # is between the dummy wafer and the second surface of the substrate such that the second primer covers the second bumps. Thereafter, a heating process is performed to cure the second primer. / In the embodiment of the invention, the glass transition temperature of the second primer is greater than the glass transition temperature of the first primer. In one embodiment of the invention, the size of the virtual wafer is less than the size of the wafer. In order to achieve the above or other purposes, the present invention further provides a method for fabricating a flip chip package structure for reducing the substrate ASEKI996 25035 twf.d〇c/n, including the following 2 = and a wafer. Wherein, the substrate has a first surface of a first-first/mesh, and the wafer has an active surface and a first bump on a plurality of active surfaces. Thereafter, the active surface of the wafer is 盥 = the first surface is opposite and the first bumps are reflowed so that the wafer is disposed on the first surface of the substrate by flip chip bonding by k 苐-bump. Next, the 'fill-first-bottom knee is on the first surface of the wafer and the substrate: 曰' so that the first-bottom wins the first bumps. After that, carry out a twisting ΐ! Two first primer. Next, a second primer corresponding to the first primer is formed on the second surface of the substrate. Finally, to cure the second primer. In the embodiment of the invention, the glass transition temperature of the second primer is greater than the glass transition temperature of the primer. The flip chip package structure for reducing the substrate of the present invention and the manufacturing method thereof are mainly disposed on the back surface of the substrate - the dummy wafer with the flip chip bonding and / or the bottom red filling, the simple (four), the wire plate production orientation The curved sheet is used to suppress the problem of the substrate being subjected to reflow and dispensing, thereby solving the problem of the conventional flip-chip structure. The above and other objects, features, and advantages of the present invention will become more apparent. 2A to 2H are schematic cross-sectional views showing a process of fabricating a flip-chip structure for reducing a light curve of a substrate according to an embodiment of the present invention. Ken 1355724 ASEK1996 25035twf.doc/n First, referring to FIG. 2A, a substrate 210, a wafer 220, and a dummy wafer 230 are provided. The substrate 210 has a first surface 210a and a second surface 210b opposite thereto. The wafer 220 has an active surface 220a and a plurality of first bumps 222 disposed on the active surface 220a. The surface 230a of the dummy wafer 230 A plurality of second bumps 232 are disposed on the upper portion. Thereafter, as shown in FIG. 2B, the active surface 220a of the wafer 220 is opposed to the first surface 210a of the substrate 210, and the first bumps 222 are reflowed to cause the wafer 220 to be flipped by the first bumps 222. The bonding is disposed on the first surface 210a of the substrate 210. As shown in Fig. 2B, since the thermal expansion coefficients of the substrate 210 and the wafer 220 are different, the substrate 21 has a downward warpage after the reflow process. In order to improve the phenomenon of downward warpage of the substrate 210 after the reflow process, as shown in FIG. 2C, the present invention first inverts the substrate 21, and then disposes the dummy wafer 230 on the second surface 210b of the substrate 210. The bumps 232 are soldered back, and the dummy wafers 230 are disposed on the second surface 2i〇b of the substrate 21 by flip chip bonding by the second bumps 232. As shown in FIG. 2D, since the thermal expansion coefficients of the substrate 21 and the dummy wafer 23 are different, the substrate 210 also has a downward warping after the reflow process, thereby overcoming the substrate in the previous figure. The resulting warpage and the substrate 210 are flattened. Thus, the general flow of the method for fabricating the flip chip package structure for reducing the warpage of the substrate of the present invention is further completed. The position of the dummy wafer 230 disposed on the second surface 21b of the substrate 21 corresponds to the wafer. The 220 is disposed at a position on the first surface of the substrate 21, and the size of the dummy wafer 230 is preferably less than the size of the wafer 22〇1555724 ASEK1996 25035twf.doc/n to help the substrate 210 be originally produced. Warping is equalized. In order to protect the first bump 222 connected between the substrate 210 and the wafer 220 from damage and moisture, after completing the step shown in FIG. 2D, as shown in FIG. 2E, the wafer 220 and the substrate 21 may be Between a surface 21A - a first primer 240 is filled to cause the first primer 240 to cover the first bumps 222. Thereafter, referring to the figure π, a heating process is performed to cure the first primer 240. However, after the first primer 240 is heated, as shown in Fig. 2F, the substrate 210 will again be warped downward. Therefore, referring to FIG. 2G, the substrate 21 can be inverted ' and a second primer 25 填充 is filled between the dummy wafer 23 〇 and the second surface 21 〇 b of the base plate 210 to make the first. The second primer 25 〇 covers the second bumps 232. Thereafter, as shown in FIG. 2, a heating step is performed to cure the second primer 250. Since the second primer 250 is subjected to a heating process, the substrate 21 is again warped downward, so that the warpage generated by the substrate 21 in the previous FIG. 2F can be overcome and the substrate 210 can be flattened. Since the second primer 25 is selected to affect the degree of warpage of the substrate 210, the user selects a second primer 25 having a different glass transition temperature to improve and control the substrate 210. The degree of warpage. In one embodiment of the invention, the glass transition temperature of the primer 200 is preferably greater than the glass transition temperature of the first primer. In this way, after the second primer 250 is subjected to the process of dispensing and heating, the degree of warpage generated by the substrate 210 can suppress the warpage of the substrate 210 generated after the first primer is baked, and then the substrate 2 〇 Leveling 0 (S) 11 1355724 ASEK1996 25035 twf.doc/n FIGS. 3A to 3F are schematic cross-sectional views showing a method of fabricating a flip chip package structure for reducing substrate warpage according to another embodiment of the present invention. First, referring to FIG. 3A, a substrate 21A and a wafer 220 are provided. The substrate 210 has a first surface 2i〇a and a second surface 210b opposite thereto. The wafer 220 has an active surface 220a and a plurality of first bumps 222 disposed on the active surface 220a. Thereafter, referring to FIG. 3B, the active surface 220a of the wafer 220 is opposed to the first surface 210a of the substrate 210, and the first bumps 222 are soldered back. The wafers 22 are etched by the first bumps 222. It is disposed on the surface 210a of the substrate 21'' by a flip chip bonding. As shown in Fig. 3B, since the thermal expansion coefficients of the substrate 210 and the wafer 220 are different, the substrate 21 has a downward warpage after the reflow process. To protect the first bump 222 connected between the substrate 210 and the wafer 220 from damage and moisture, after completing the step shown in FIG. 3B, as shown in FIG. 3C, on the first surface of the wafer 220 and the substrate 210. A first primer 240 is filled between the 210a so that the first primer 240 covers the first bumps 222. Thereafter, a heating process is performed as shown in Fig. 3D to cure the first primer 240. As shown in Fig. 3D, after the filling and heating process of the first primer 240, the substrate 210 is warped downward more significantly. Next, as shown in FIG. 3E, a second primer 25A corresponding to the first primer 24 is formed on the second surface 210b of the substrate 210. Finally, referring to FIG. 3F, a heating process is performed to cure the second primer 250'', thereby using the second primer 25, the filling and heating process to overcome the substrate 21 caused by the previous step of FIG. 3D. The phenomenon of warping is caused, and the substrate 210 is flattened. 12 1355724 ASEK1996 25035twf.doc/n In summary, the flip-chip package structure for reducing substrate warpage of the present invention and the manufacturing method thereof are mainly provided on the back surface of the substrate with a dummy wafer bonded to the crystal and/or a primer. The filling and baking process causes the substrate to have a reverse warpage to suppress the warpage generated by the substrate after the reflow and dispensing process, thereby leveling the substrate. In addition, the user can select different sizes of virtual wafers and primers with different glass transition temperatures to control the degree of reverse warpage of the substrate, thereby flattening the substrate. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to be used in the present invention. Anyone skilled in the art can make some changes and refinements in the stomach within the spirit of the present invention. -_ shall be subject to the definition of the scope of the patent application attached. 5 guarantees. [Simplified description of the diagram] 】 is a schematic diagram of a flip-chip package structure. 2A to 2D are diagrams showing the fabrication of the flip chip package structure of the substrate clock according to the present invention. The soil reduction _ 3 Α 3F green is shown in accordance with the present invention. •: Fabrication of a flip chip package structure 1: = = [Key component symbol description] 100 Flip chip package structure 110 Substrate 111 Upper surface 112 Lower surface 113 Adhesive < S ) 13 1355724 ASEK1996 25035twf.doc/n
120 ： 覆晶晶片 121 ： 主動面 122 ： 背面 123 ： 凸塊 130 ： 底膠 140 ： 散熱板 141 ： 結合部 210 ： 基板 210a :第一表面 210b :第二表面 220 ： 晶片 220a :主動面 222 ： 第一凸塊 230 ： 虛晶片 230a :表面 232 ： 第二凸塊 240 ： _第一底膠 250、 250’ ：第二底膠 14120: flip chip 121: active surface 122: back surface 123: bump 130: primer 140: heat sink 141: joint 210: substrate 210a: first surface 210b: second surface 220: wafer 220a: active surface 222: First bump 230: virtual wafer 230a: surface 232: second bump 240: _ first primer 250, 250': second primer 14