1354892 九、發明說明： 【發明所屬之技術領域】 ，特別是運用於— 本發明係有關一種快閃！己，_之資料即時更新方法 種快閃記憶體内部資料區的資料即時更新方法^ 【先前技術】 現今，由於消費者對各型儲存媒體的需求急速増加且快閃記憶體 (F祕Memory)不需要電力即可維持數據的儲存，加上早期的電子可抹除式 • 唯讀記憶體(删10寧允許單處執行緒重寫，但快閃記憶體卻可允許同^ 多處執行緒Μ，所以快閃記憶體的執行速度會比—般早期電子可抹除式 唯讀記憶體(EEPROM)快报乡，使得快閃記憶體已逐漸取代電子可抹除· 讀記憶體(EEPROM)成為目前消費性電子儲存裝置的主流之一。 快閃記憶體之工作原理是利用浮閘大量導引金屬氧化半導體 (Fl〇ating-Gate Avalanche_Injecti〇n 跑以 〇xMe 黯 過内部的電容耦合(Coupling)來有效地控制其浮閘(H〇ating Gate)上之電荷 _ 移動’使得δ玄浮閘可根據该電荷的移動而決定下層電晶體的間值電壓。如 當負電子注入該浮閘時，該浮閘的儲存狀態便會從丨變成〇 ;而當負電子從 該浮閘移走後，該浮閘的儲存狀態便會從〇變成1。藉此，即可令快閃記憶 • 體執行寫入(Write)、抹除(Erase)及讀取(Read)等操作。 . 目前快閃記憶體主要分成四種類型：反或閘(NOR)型、反及閘(NAND) 型、及閘(AND)型以及分裂位線反或閘(Dividedbit_HneNOR3；DiNOR)型等， 各有不同的特性以滿足不同的功能或應用上的需求，其中雖然反或閘型快 5 1354892 閃記憶體是最早被開發出來的，但目前以反及閘型快閃記憶體的使用率最 w 廣。 . 該反或閘(NOR)型快閃記憶體具有低工作電壓、較高的資料存取可靠 度、完整地址和數據界面並可隨機讀取，且資料可以寫入單一位元組或位 元(Bitwise)，但無法抹除(Erase)單一位元組，而必須是以區塊（Bi〇ek)為 單位或對整個區域執行抹除，因此反或閘(NOR)型快閃記憶體的抹除和寫入 速度較慢’加上區塊尺寸較大，使得反或閘(NOR)型快閃記憶體無法應用於 φ 單純的資料儲存或槽案儲存，故較適用儲存不需要經常更新的資料如程式 碼(如可支援XIP)、BIOS或韌體，目前被大量應用於可攜式電子裝置及電 子通訊裝置中之系統資料，如個人電腦(personal Computer，PC)、行動電話 (Cell Phone)、個人數位助理(Personai Digital Assistance, PDA)或轉頻器 (Set-top Box，STB)等，或用於滿足上述電子裝置的開機需求。 該反及閘(NAND)型快閃記憶體的資料存取是以頁(page)為單位，每一 頁包含256或512 Byte的儲存空間(User邱㈣，加上8或16 Byte的 # 輔助空間（Spare Space)。該輔助空間主要用來存放錯誤更正碼（Err〇r Correction Code，ECC) ’記憶體損壞標記和檔案系統的資料。大約32頁或 Μ頁即組成每-個區塊（B1〇ck)，但典型的反及間(NAND)型快μ記憶體的 _區塊事貫上是比反或閘_反)型快閃記憶體的區塊小約8倍，且該反及問 …励)型快閃·_絲是輯贴單位，相雜反或_〇11)型快閃 記憶體的抹除區塊是具有1〇比】的區塊抹除週期比如反及閑^柳)型 快閃記憶體塊抹除時間是2ms，則反或閘型快閃記憶體塊之抹除時間 6 1354892 •可達到幾百⑽。因此，該反及閘(NAND)型快閃記憶體具有比N〇R型快閃 *記憶體更快的寫入和抹除時間、高密度、較長的產品壽命以及比職型 、’己隐體低的製造成本。但因為該反及閘(NAND)型快閃記憶體之I/O界 面只允許序列讀取，所以反及閘(NAND)型快閃記惇體不適合儲存程式碼， 但是適合作為可儲存大量數據之儲存裝置如儲存卡等之用，亦可用於手 機、MP3播放器或數位㈣體播放器等存放多媒體檔案祕介之一。 "5而特·?j疋反及閘型快閃記憶體，除了在製程中有可能會導 • 賴區塊陶Β_的產生外，當該快閃記憶體經過多次的寫入、抹除及 貝取運作後亦會造成位元的損毁(Bit E·)。因此習知反及問⑽ 型快脱ft勸勒具有義龄料管理_咖⑶Μ·δ_，bbm)以 及可自動偵錯及改正損毁位元的錯誤校正碼(Err〇r ^職論c〇de，ecc), l識另丨及取代在寫A_、抹除及讀取運作時所產生的壞區塊，並同時將該等 壞區塊的資料拷貝到有效區塊，從而維持該快閃記憶體的可靠性。 但疋，上述的壞區塊資料管理及錯誤校正碼仍無法確保該反及閘 _ 嫂快閃δ己憶體内部所儲存的資料的可靠性及安全性，其主要原因為 習知反及閘(NAND)型快閃記憶體係藉由電容賴合來控制該浮閉上電荷的 移動，以決定資料的讀取或寫人運作。然而，當該反及問^AND)型快閃記 憶體在執行多次讀取運作時，由於在同一區塊(B1〇ck)中，非被選為做讀取 的頁面所產生的通道熱載子(channei hot carrier)會對浮閘充電，即產生些微 的電位差，因而導致抹除的狀態由i轉變為〇,或是因浮閘自身的漏電問題 而無法將狀態持續保持為〇，上述之問題皆會造成讀取混亂(ReadDisturb)， 7 1354892 因此當該快閃記憶體重複讀 u τ禺-人之後，就會因為讀取混亂(Read D咖rb)而造成該快閃記憶體所 響’但卻需重新對此區塊(block)再一次 又重要貝枓遺失。雖然此讀取混亂並未 對快閃記憶體之結構造成破壞性的影響， 進行抹除與寫入之程序。 因此’有必要針對_是反及_細聰快閃記憶體内部的資料區管 =提供-種㈣資料更新方法，以避免該快閃記憶翻讀取混邮ead ㈣讓浮軸存__細糊失的問題。 【發明内容】 為解決上·題，本翻之主要目的係提供—種㈣資料更新方法， 八用於决閃5己憶體内部的資料區之資料自動更新處理，其可有效地避免 該快閃記憶體因内部浮閑所錯存的電荷問題而造成資料遺失，且縮短開機 時該快閃記憶體„料區_料_咖，故能增加該鋼記隨的可靠 性及資料的安全性。 為達到上述發明目的’本發示—種即時資料更新方法，係運用於 -快閃記㈣之資料結構中，該_刪包含—資料區塊師驗）， /、内1、冑主要資料分割區塊以及複數個次要資料分割區塊一冗餘區 兔(RedundantBloek) ’其畴具有複數個職分割區塊，並與蹄料區塊内 的各次要分塊呈對錢結，錢―變換彳㈣緩衝印刪^ k aside Buffer，TLB)，其分別連接至該資料區塊及該冗餘區塊，用於讀 取3亥貝料區塊⑽主要㈣分割眺所儲存的備份資料。該資料結構更新 之方法包含下列步驟： 8 1354892 步驟一：讀取該資料區塊内的主要資料分割區塊所儲存的備份資料； 步驟二：將該備份資料與該冗餘區塊内的冗餘分割區塊所暫存的資料進行 比較，以識別該冗餘分割區塊所暫存的資料是否為最後一筆寫入 的資料， 步驟三：如果該冗餘區塊所暫存的資料即是最後一筆寫入的資料，更新該 變換後備緩衝區内的對映表，並將該資料置換至該資料區塊内， 接著該快閃記憶體便執行正常運作； 步驟四：如果該冗餘區塊所暫存的資料並不是最後一筆寫入的資料，則該 快閃記憶體便直接執行正常運作； V驟五.右該快閃記憶體在初始化結束後並在執行一正常運作時，接收到 -更新指令，_快閃記便啟動自動麟運作，接著將該冗 餘區塊内其中-個冗餘分割區塊所暫存的資料抹除以形成一個 空的冗餘分祕塊；反之’若該快閃記‘_在執行正常運作時未 接收到該更新指令，則該快閃記憶體便繼續執行正常運作； 步驟六：將該資料區塊内其中-個指定的次要資料分割區塊所儲存的資料 移至該冗餘區塊内空的冗餘分割區塊中； 步驟4- 將該資料區塊内其中另-個次要資料分龍塊所儲存的資料抹除 以形成一個空的次要資料分割區塊； 步·？^ \ …將於步驟六中移人該冗餘區塊内的暫存f料移至該資料區塊内空 的次要資料分_塊中’接記憶體便_執行正常運 1354892 綜上所述，藉由本發明的資料即時更新方法，除可有效地避免因快閃 記憶體内浮閘所儲存的電荷問題而造成資料的遺失外，尚可縮短開機時該 快閃記憶體内資枓區的資料回復時間，以及增加該快閃記憶體的可靠性及 資料的安全性。 【實施方式】 請參閱第1A圖，係闡示本發明的資料結構示意圖，其適用於一快閃記 憶體内部的資料區。該快閃記憶體的類型可為反或閘"OR)、反及閘 (NAND)、及閉(AND)以及分裂位線反或問(Divided bit-line NOR ; DiNOR) 等四種其中之一，惟在本發明之較佳實施例中係以一具有N〇R介面之反及 閘(NAND)快閃記憶體為案例加以說明，但並不因此限定本發明之專利範 圍。如第1A圖所示的資料區塊1〇1 (Data B1〇ck)包含複數個資料分割區塊 l〇la、101b ' l〇lc、101d、101e〜 1〇lm，其中該主要資料分割區塊驗用 於存放有關該資料區塊101的各種管理資料及一對映表(ΜαρρίηβΤ·)，從 次要資料分f_m塊101b開始才真正觀雌存各種由該快閃記憶體外部寫 入的資料。 前述每一個資料分割區塊101b〜101m進一步包含64個全頁面斤讪 Page)，且每一個全頁面又為4個分頁面(partiti〇n page)m組成，其中如第汨 圖所示之每—頁面1⑽包含512 Bytes的使用者資料位於使用者空哪卿 沖咖)，以及16邮冗餘資料位於輔助空間(Spare Space)，其中該512 Bytes 的使用者資料健存由該,_記舰外部寫人_料，以及該16邮冗餘 資料用於儲存触閃記㈣每—個頁面驗祕息，鱗狀舰息係包含 10 1354892 狀態(Status,以”s”表示）訊息、邏輯區塊位址(L〇gicai Bi〇ck Address，以” ‘ LBA”表不)訊息、旗標(Tag,以，T，表示)訊息、同位元^办，以”p”表示)訊 . 息以及循環冗餘檢查(Cyclic Redundancy Check, CRC)碼訊息，使得連接該快 閃記憶體的控制器(Controller)能夠確實了解資料的安全性且易於管理。 又如第1A圖所示’該快閃記憶體還具有一冗餘區塊102(Redundant Block)包含複數個冗餘分割區塊1〇2a、1〇2b、1〇2c〜1〇2n可對應連結至資 料區塊101内之各次要資料分割區塊101b〜101m，由於冗餘區塊102之作 用主要係作為緩衝區’以暫存該資料區塊1〇1内各次要資料分割區塊1〇lb〜 101m所儲存的資枓。須注意的是，冗餘區塊1〇2内的每一個冗餘分割區塊 102a〜102η均未對映至資料區塊101的主要資料分割區塊1〇la。在實際應 用上，若以一具有1Gbits記憶容量的快閃記憶體為例，資料區塊1〇1内所 有資料分割區塊l〇la〜101m)的容量加上冗餘區塊1〇2内所有冗餘分割區塊 102a〜102η)的容量大概僅佔用約1024KBytes，對於該快閃記憶體的整體記 憶容量並不會造成太大影響。 此外’該快閃記憶體具有一變換後備緩衝區l〇3(TranslationL〇〇k_aside Buffer，TLB)設於一靜態隨機存取記憶體(Sram)中，並分別連結至資料區 塊及冗餘區塊102，用於提供各種管理資料及對映表(MappingTaWe)予 該主要資料分割區塊l〇la，且該對映表記錄資料區塊ιοί之每一個次要資 料分割區塊l〇lb〜101m (除了主要資料分割區塊l〇la以外)的邏輯位址 (Logical Address)與實體位址(Physical Address)之間的位址關係，且該對映表 係定義該複數個冗餘分割區塊與對應的複數個次要分割區塊之間的對映關 1354892 係，以加快該快閃記憶體的資料搜尋效率。 ‘ 為了確保該快閃記憶體儲存的資料不會因多次讀取導致其浮閘 ,(Floatmg Gate)中電荷問題而遺失資料，如第2圖所示本發明提供一種資料 即時更新方法來自動完成資料更新的處理。舉例而言，假使該電子裝置突 然關機或㈣電力中斷時，導致如第1A圖所雜快閃記紐之資料區塊 101之某-次要資料分割區塊麵發生資料遺失，此時冗餘區塊1〇2仍會 保有原本對應的冗餘分割區塊隐的資料。此時，利用第2圖所示之依據 鲁本發明之資料更新方法，可在有限的開機時間内先執行一快閃記憶體之初 使化流程S20，在此初始化過程中先改變該變換後備緩衝(孔職⑽之對 映表(Mapping table)内的資料，並利用置換(Swapping)方式以節省開機時的 資料回復時間(待後詳述），再利用此更正資料執行該快閃記憶體執行另一資 料自動更新流程S21。 該快閃記憶體之初使化流程S2〇包括以下步驟： 步驟2〇1表示一電子裝置(諸如電腦、手機、個人數位助理等)開機時， • 開始初始化其配置的快閃記憶體。此開機並不限為冷開機(c〇ld Boost)或暖 開機(Warm Boost)。 於步驟202中，讀取該資料區塊1〇1之主要資料分割區塊咖所儲存 •的變換後備緩衝(TL⑽之備份資料(包括資料區塊1〇1的各種管理資料 及對映表）由於該丨夬閃§己憶體位在靜態隨機存取記憶體(SRAM)中，使得 變換後備緩衝區1〇3具有與快取(Cache)一樣快的讀取速度，因此步驟並J 會耗費报多時間。 12 1354892 於步驟203中’依據讀取到該變換後備緩衝區1〇3内的對映表，與冗 *餘區塊102内各冗餘分割區塊進行逐一的比較，由於冗餘區塊102主要係 .作為緩衝區’其係用於暫存資料區塊101内各次要資料分割區塊所儲存的 資料，因此當上述的中央處理器讀取完冗餘區塊102内某一個冗餘分割區 塊的資料後，會自動把資料區塊101内下一個次要資料分割區塊所儲存的 貧料預先移至冗餘區塊102内其中一冗餘分割區塊。當該中央處理器需要 讀取下-個次要資料分割區塊的資料時，就可直接在冗餘區塊102内進行 Φ 讀取。再者，由於變換後備緩衝區103内的對映表係藉由讀取至資料區塊 l〇la的備份資料而取得’因此該對映表係具有—完整之邏輯位址及實體位 址之間的對應關係。然而，雖然冗餘區塊1〇2於前次使用時係暫存資料區 塊101内各資料分割區塊所儲存的資料，但卻是採用逐一暫存的方式。因 此，對照於帛ΙΑ ϋ，當暫存於冗餘區塊1〇2内的冗餘分割區塊腿的資 料被頃取後，才會自動將下一筆的次要資料分割區塊1〇ld所儲存資料移進 冗餘區塊102的冗餘分割區塊102c中，此時若於使用時發生電力中斷或是 • 贿快閃記題内浮騎齡的電制題而造成料區塊1G1内次要資料 分割區塊ioid所儲存的資料遺失時，冗餘區塊1〇2内的冗餘分割區塊隐 仍保有於前次使用時次要資料分割區塊觀所儲存的資料；此時，當變換 .後備緩衝區103内的對映表與冗餘區塊102内的各冗餘分割區塊相互比較 彳&於在几餘分割區塊102c之後並未有任何的資料移入，因此經由變換 後備緩衝區⑽即可識別冗餘區塊1〇2内的冗餘分割區塊職即是最後一 筆寫入的資料。 13 1354892 再者，於步驟S204中，更新變換後備緩衝區1〇3内的對映表，並同時 '將冗餘分割區塊廳内的資料置換(Swapping)至資料區塊101内的次要資 •料分割區塊> 中，這時變換後備緩衝區1〇3首先將已儲存的對映表中關 於··人要負料分割區塊101d的邏輯位址及實體位址移除，並將次要資料分割 區塊l〇ld新的邏輯位址及實體位址寫入，從而使變換後備緩衝區1〇3在之 後的處理時會有更高的命中率(Hit Rate)，而於變換後備緩衝區1〇3更新完 之後便於步驟S211作進一步的處理。惟，若於前述步驟S2〇3中識別出冗 Φ 餘區塊102内各冗餘分割區塊的資料均與變換後備緩衝區1〇3内的對映表 相同，即冗餘區塊102内的冗餘分割區塊i〇2a至冗餘分割區塊1〇2n所暫 存的資料均相同於資料區塊101内次要資料分割區塊1〇lb至次要資料分割 區塊101m所儲存的資料。換言之，即表示於前次使用時並未發生電力中斷 或是因該快閃記憶體内浮閘所儲存的電荷問題而造成資料區塊1〇1内各次 要資料分割區塊所儲存的資料遺失。因此，變換後備緩衝區1〇3便不需要 更新而直接到步驟S211進一步的處理。然而，這裡需注意的是，由於冗餘 修 區塊丨〇2内每一個冗餘分割區塊的收尋時間約為8〇微秒，因此利用置換的 方式達到資料區塊101完整的初使化可有效地縮短開機時資料回復的時間。 此外，該資料自動更新流程S21包括以下步驟： 步驟S211即是該快閃記憶體在完成前述的初使化步驟之後，開始執行 諸如各種外部資料的讀取、抹除或寫入等的正常運作。當該快閃記憶體夕卜 部所連接的主端(Host)在閒置(Idle)，即並未執行存取運作時，可自行根據& 用程式的需求判斷是否須發出一更新指令(Refresh Co_and)給該快閃記隱 14 13548921354892 IX. Description of the invention: [Technical field to which the invention pertains], especially for use - The present invention relates to a flash! _, _ data instant update method flash memory internal data area data update method ^ [prior technology] Today, due to consumer demand for various types of storage media, and flash memory (F secret Memory) Maintain data storage without power, plus early electronic erasable • Read-only memory (deleting 10 allows for single-thread rewriting, but flash memory allows multiple threads) Oh, so the execution speed of the flash memory will be faster than that of the early-stage electronic erasable read-only memory (EEPROM), so that the flash memory has gradually replaced the electronic erasable and read memory (EEPROM). One of the mainstream of consumer electronic storage devices. The working principle of flash memory is to use a floating gate to guide a large amount of metal oxide semiconductors (Fl〇ating-Gate Avalanche_Injecti〇n running to 〇xMe 内部 internal capacitive coupling (Coupling) To effectively control the charge _ movement on its floating gate (H〇ating Gate), the δ Xuan floating gate can determine the inter-value voltage of the lower layer transistor according to the movement of the charge. For example, when negative electrons are injected into the floating gate The storage state of the floating gate will change from 丨 to 〇; and when the negative electron is removed from the floating gate, the storage state of the floating gate will change from 〇 to 1. Thus, the flash memory can be made. Perform write (Write), erase (Erase), and read (Read) operations. Currently, flash memory is mainly divided into four types: reverse OR gate (NOR) type, reverse gate (NAND) type, and Gate type (AND) and split bit line reverse or gate (Dividedbit_HneNOR3; DiNOR) type, etc., each have different characteristics to meet different functional or application requirements, although the reverse or gate type is fast 5 1354892 flash memory is the earliest It has been developed, but currently it has the widest usage rate of anti-gate type flash memory. The anti-gate (NOR) type flash memory has low operating voltage, high data access reliability, Complete address and data interface and can be read randomly, and the data can be written to a single byte or bitwise (Bitwise), but can not erase (Erase) a single byte, but must be a block (Bi〇ek) Erasing for the unit or for the entire area, so the erase or write speed of the anti-gate (NOR) type flash memory The slower 'plus larger block size makes the anti-gate (NOR) type flash memory not applicable to φ simple data storage or slot file storage, so it is more suitable for storing data that does not need to be updated frequently, such as code ( If it can support XIP), BIOS or firmware, it is widely used in system data of portable electronic devices and electronic communication devices, such as personal computers (PCs), mobile phones (Cell Phone), personal digital assistants. (Personai Digital Assistance, PDA) or a set-top box (STB), etc., or used to meet the booting requirements of the above electronic devices. The data access of the NAND flash memory is in units of pages, each page containing 256 or 512 Bytes of storage space (User Qiu (four), plus 8 or 16 Bytes of # auxiliaries Space (Spare Space). This auxiliary space is mainly used to store the Err〇r Correction Code (ECC) 'memory damage mark and file system data. About 32 pages or pages constitute each block ( B1〇ck), but the typical NAND block of the NAND type fast μ memory is about 8 times smaller than the block of the inverse or gate_reverse type flash memory, and the inverse And ask ... excitation) type flash · _ silk is a patch unit, mixed or _ 〇 11) type flash memory erase block is 1 〇 block block erasure period such as anti-free ^柳) Flash memory block erase time is 2ms, then the erasure time of the reverse or gate type flash memory block is 6 1354892 • It can reach several hundred (10). Therefore, the NAND type flash memory has faster writing and erasing time, higher density, longer product life, and specific type than the N〇R type flash* memory. The manufacturing cost of the hidden body is low. However, because the I/O interface of the NAND flash memory only allows sequence reading, the NAND flash memory is not suitable for storing code, but is suitable for storing large amounts of data. The storage device, such as a memory card, can also be used for storing multimedia files, such as a mobile phone, an MP3 player, or a digital (four) body player. "5 特 特 ? j 疋 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸Damage to the bit (Bit E·) will also result from erasing and beating operations. Therefore, the conventional anti-question (10) type quick release ft persuasion has the ageing material management _ coffee (3) Μ · δ _, bbm) and the error correction code that can automatically detect and correct the damaged bit (Err〇r ^ job theory c〇de , ecc), l recognizes and replaces the bad blocks generated during the write A_, erase and read operations, and simultaneously copies the bad block data to the active block to maintain the flash memory. Body reliability. However, the above-mentioned bad block data management and error correction codes are still unable to ensure the reliability and safety of the data stored in the internal and external flash memory. The main reason is the conventional anti-gate The (NAND) type flash memory system controls the movement of the charge on the floating by the capacitance dependence to determine the reading or writing operation of the data. However, when the flash memory of the AND-AND type is performing a plurality of read operations, the channel heat generated by the page selected for reading is in the same block (B1〇ck). The chanelei hot carrier charges the floating gate, that is, it generates a slight potential difference, which causes the erased state to change from i to 〇, or the state of the floating gate itself cannot maintain the state continuously. The problem will cause read confusion (ReadDisturb), 7 1354892. Therefore, when the flash memory repeatedly reads u τ禺-人, the flash memory will be heard due to read confusion (Read D rb). 'But it is necessary to re-create this block again and again important bei. Although this read disorder does not have a damaging effect on the structure of the flash memory, the erase and write process is performed. Therefore, it is necessary to aim at _ is against _ _ _ _ flash memory internal data area management = provide - kind (four) data update method to avoid the flash memory to read the mixed mail ead (four) let the floating axis save __ fine The problem of loss. [Summary of the Invention] In order to solve the above problem, the main purpose of the present invention is to provide a method for updating data in the fourth (four) data, and eight for automatically updating the data in the data area inside the flash memory, which can effectively avoid the fast The flash memory is lost due to the charge problem of the internal floating memory, and the flash memory is shortened when starting up, so the reliability and data security of the steel can be increased. In order to achieve the above-mentioned object of the invention, the present invention discloses a method for updating real-time data, which is applied to the data structure of the flash flash (4), the _ deleting includes - the data block teacher test), /, the inner 1, the main data segmentation Block and a plurality of secondary data partitioning blocks - RedundantBloek 'The domain has a plurality of divisions, and is associated with each sub-block in the hoof material block, money ― The transform 彳 (4) buffer prints and deletes ^ k aside Buffer (TLB), which are respectively connected to the data block and the redundant block, and are used for reading the backup data stored in the main (four) partitions of the 3 haibei material block (10). The method of updating the data structure includes the following steps 8 1354892 Step 1: Read the backup data stored in the main data partition in the data block; Step 2: Perform the backup data and the data temporarily stored in the redundant partition in the redundant block Comparing, to identify whether the data temporarily stored in the redundant partition is the last written data, Step 3: if the data temporarily stored in the redundant block is the last written data, update the transformation The mapping table in the backup buffer, and the data is replaced into the data block, and then the flash memory performs normal operation; Step 4: If the data temporarily stored in the redundant block is not the last one When the data is written, the flash memory directly performs normal operation; V. V. Right, the flash memory receives the update command after the initialization is completed and performs a normal operation, and the flash memory is started. Automatic lining operation, then erasing the data temporarily stored in one of the redundant partitions in the redundant block to form an empty redundant secret block; otherwise, if the flash ticker is performing normal operation Not received After the update instruction, the flash memory continues to perform normal operations; Step 6: The data stored in one of the specified secondary data partitions in the data block is moved to the redundant block. In the redundant partition block; Step 4 - erase the data stored in the other secondary data split block in the data block to form an empty secondary data partition block; Step·?^ ...will move the temporary storage material in the redundant block to the secondary data sub-block in the data block in step 6. 'Connect the memory to the normal operation 1354892. According to the instant update method of the present invention, in addition to effectively avoiding the loss of data caused by the charge stored in the floating memory of the flash memory, the data of the flash memory body in the flash memory area can be shortened at the time of booting. Reply time, and increase the reliability of the flash memory and the security of the data. [Embodiment] Please refer to FIG. 1A for a schematic diagram of a data structure of the present invention, which is applied to a data area inside a flash memory. The type of the flash memory can be reverse OR gate OR, NAND, AND, and Divided bit-line NOR (DiNOR). One, but in the preferred embodiment of the present invention, a NAND flash memory having an N〇R interface is described as an example, but does not limit the scope of the invention. The data block 1〇1 (Data B1〇ck) shown in FIG. 1A includes a plurality of data partitioning blocks l〇la, 101b′l〇lc, 101d, 101e~1〇lm, wherein the main data partitioning area The block test is used to store various management data and a pair of mapping tables (ΜαρρίηβΤ·) related to the data block 101, and the secondary data is divided into the f_m block 101b to actually view the female external writes written by the flash memory. data. Each of the foregoing data partitioning blocks 101b to 101m further includes 64 full page pages, and each full page is composed of 4 partial pages (partiti〇n page) m, wherein each of the blocks shown in FIG. - Page 1 (10) contains 512 Bytes of user data located in the user's empty space, and 16 mail redundant data is located in the auxiliary space (Spare Space), where the 512 Bytes of user data is stored by the _ The external writer and the 16-mail redundant data are used to store the touch flash (4) each page of the test secret, the scaly ship contains 10 1354892 status (Status, indicated by "s") message, logical block Address (L〇gicai Bi〇ck Address, to "LBA" table) message, flag (Tag, to, T,) message, peers, "p") message and cycle The Cyclic Redundancy Check (CRC) code message enables the controller connected to the flash memory to know the security of the data and is easy to manage. As shown in FIG. 1A, the flash memory further has a redundant block 102 including a plurality of redundant partition blocks 1〇2a, 1〇2b, and 1〇2c~1〇2n. Linking to each of the secondary data partitioning blocks 101b to 101m in the data block 101, since the redundant block 102 functions mainly as a buffer 'to temporarily store the secondary data partitions in the data block 1〇1 The assets stored in block 1 〇 lb ~ 101m. It should be noted that each of the redundant partitions 102a to 102n in the redundant block 1〇2 is not mapped to the main data partition block 1〇1a of the data block 101. In practical applications, if a flash memory having a memory capacity of 1 Gbits is taken as an example, the capacity of all data partition blocks l〇la~101m in the data block 1〇1 is added to the redundant block 1〇2. The capacity of all redundant partition blocks 102a to 102n) occupies only about 1024 KBytes, which does not have much influence on the overall memory capacity of the flash memory. In addition, the flash memory has a transform backup buffer l〇3 (TranslationL〇〇k_aside Buffer, TLB) is set in a static random access memory (Sram) and is respectively connected to the data block and the redundant area. Block 102, for providing various management data and mapping table (MappingTaWe) to the main data partitioning block l〇la, and the mapping table records the data block ιοί each of the secondary data partitioning blocks l〇 lb~ An address relationship between a logical address (Physical Address) of 101m (except the main data partitioning block l〇la) and a physical address, and the mapping table defines the plurality of redundant partitions The mapping between the block and the corresponding plurality of secondary partitions is 1354892 to speed up the data search efficiency of the flash memory. In order to ensure that the data stored in the flash memory does not cause its floating gate due to multiple readings, the data is lost in the Floatmg Gate. As shown in Figure 2, the present invention provides an instant update method for data automatically. Complete the processing of the data update. For example, if the electronic device is suddenly turned off or (4) the power is interrupted, the data is lost in the data area of the certain-secondary data segment of the data block 101 of the flash memory button of FIG. 1A. Block 1〇2 will still retain the hidden data of the original redundant partition. At this time, by using the data updating method according to the invention of FIG. 2, a flash memory initializing process S20 can be executed in a limited booting time, and the transforming backup is first changed in the initializing process. Buffering (the data in the mapping table of the hole (10), and using the Swapping method to save the data recovery time at the time of booting (to be detailed later), and then using the correction data to execute the flash memory Perform another data automatic update process S21. The flash memory initialization process S2 includes the following steps: Step 2: 1 indicates that an electronic device (such as a computer, a mobile phone, a personal digital assistant, etc.) is powered on, • starts initialization The flash memory of the configuration is not limited to cold boot (c〇ld Boost) or warm boot (Warm Boost). In step 202, the main data partition block of the data block 1〇1 is read. The storage backup buffer (the backup data of TL (10) (including various management data and mapping table of data block 1〇1) is stored in static random access memory (SRAM) due to the flash memory. To make a transformation The buffer 1〇3 has the same fast read speed as the cache, so the step and J will consume more time. 12 1354892 In step 203, 'based on the read backup buffer 1〇3 The mapping table is compared with each redundant partition in the redundant block 102. Since the redundant block 102 is mainly used as a buffer, it is used for temporarily storing the data block 101. The data stored in the block is to be divided, so that when the central processor reads the data of a redundant partition in the redundant block 102, the next secondary data in the data block 101 is automatically deleted. The poor material stored in the partition block is moved to one of the redundant partition blocks in the redundant block 102. When the central processor needs to read the data of the next-second data partition block, it can directly Φ reading is performed in the redundant block 102. Furthermore, since the mapping table in the conversion lookaside buffer 103 is obtained by reading the backup data to the data block l〇la, the mapping table has - the correspondence between the complete logical address and the physical address. However, However, the redundant block 1〇2 is used to store the data stored in each data segment in the data block 101 in the previous use, but it is used in a temporary storage manner. Therefore, in contrast to 帛ΙΑ ϋ, when After the data of the redundant partition block temporarily stored in the redundant block 1〇2 is taken, the data stored in the next secondary data partition block 1〇ld is automatically moved into the redundant block. In the redundant partition block 102c of 102, if the power interruption occurs during use or the electric title of the floating riding in the flashing question is caused, the secondary data partition block ioid stored in the material block 1G1 is stored. When the data is lost, the redundant partition in the redundant block 1〇2 still retains the data stored in the secondary data partitioning block view in the previous use; at this time, when the transform is in the backup buffer 103 The mapping table is compared with each of the redundant partitions in the redundant block 102. & no data is moved after the plurality of partitions 102c, so the transform buffer (10) can be identified. The redundant partition in the redundant block 1〇2 is the last written data. 13 1354892 Furthermore, in step S204, the mapping table in the transform backup buffer 1 〇 3 is updated, and at the same time 'swapping the data in the redundant partition block to the secondary in the data block 101 In the resource partitioning block>, the transformation backup buffer 1〇3 first removes the logical address and the physical address of the stored mapping table about the partitioning block 101d. Write the new logical address and physical address of the secondary data partition block l〇ld, so that the transform backup buffer 1〇3 will have a higher hit rate in the subsequent processing, and After the update backup buffer 1〇3 is updated, the step S211 is further processed. However, if the data of each redundant partition in the redundant block 102 is identified in the foregoing step S2〇3, it is the same as the mapping table in the transform backup buffer 1〇3, that is, in the redundant block 102. The data temporarily stored in the redundant partition block i〇2a to the redundant partition block 1〇2n is the same as the data in the data block 101 from the secondary data partition block 1〇lb to the secondary data partition block 101m. data of. In other words, it means that there is no power interruption in the previous use or the data stored in each secondary data segment in the data block 1〇1 due to the charge problem stored in the floating memory. Lost. Therefore, the conversion backup buffer 1〇3 does not need to be updated and proceeds directly to the further processing of step S211. However, it should be noted here that since the acquisition time of each redundant partition in the redundant repair block 丨〇2 is about 8 〇 microseconds, the replacement of the data block 101 is achieved by the replacement method. It can effectively shorten the time for data recovery at boot time. In addition, the data automatic updating process S21 includes the following steps: Step S211 is that the flash memory starts to perform normal operations such as reading, erasing or writing of various external materials after completing the foregoing initializing step. . When the host connected to the flash memory is idle (Idle), that is, the access operation is not performed, it is determined according to the requirements of the & program whether an update command must be issued (Refresh Co_and ) Give the flash to remember 14 14354892
^ite 〇 . I 於步驟S212中，若該快閃記憶體並未接收到由主端所發出的更 新^ 7 ’便繼續於步驟_巾執行各種外部諸的讀取抹除或寫入的正 i f 准若該快閃§己憶體於步驟S2i2中接收到由主端所發出的更新指 7時，則於步驟S213中作進一步的處理。 於步驟S213中，當該快閃記憶體接收到由主端所發出的更新指令便 啟動自動更新運作。此時，首先將冗餘區塊1〇2内其中一冗餘分割區塊所 暫存的資料抹除以形成一個空的冗餘分割區塊，再於步驟咖中將資料區 • 塊1〇1内其中一個次要資料分割區塊所儲存的資料移至冗餘區塊搬内空 的冗餘分割區塊中。 又，於步驟S215中，再將資料區塊1〇1㈣中另一次要資料分割區塊 所儲存的資料抹除以形成一個空的資料分割區塊。並於步驟伽中係將 已於前述步驟S214中暫存於冗餘區塊搬内的資料移至資料區塊ι〇ι内空 的次要資料分割區塊中。最候，於步驟8217即表示結束自動更新的運作， 即雜閃記憶體係返回步驟SU1以執行各種外部資料的讀取、抹除或寫入 修的正常運作。综上所述，步驟S21的完整更新時間約為2〇〇毫秒，其可有 效地確保資料區塊不會因多次讀取而造成浮問所儲存的電荷問題進 而造成資料區塊101内各次要資料分割區塊所儲存的資料遺失。 • 目此’藉由本發明㈣料結構及其即較新方法，除可有效地避免因 . 快閃記憶體内浮閘所儲存的電荷問題而造成資料的遺失外，尚可縮短開機 時該快閃記憶體内資料區的資料回復時間，以及增加該快閃記憶體的可靠 性及資料的安全性。 15 1354892 綜合以上所述，雖然本發明已較佳實施例揭露如上，然其並非用以限 、 定本發明，任何热習此項技藝者，在不脫離本發明之精神和範圍内，當可 •作各種更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。^ite 〇. I in step S212, if the flash memory does not receive the update issued by the primary end ^ 7 ' continue to the step _ towel to perform various external read erase or write positive If if the flash is succumbed to the update finger 7 issued by the master in step S2i2, then further processing is performed in step S213. In step S213, the automatic update operation is initiated when the flash memory receives the update command issued by the master. At this time, firstly, the data temporarily stored in one of the redundant partitions in the redundant block 1〇2 is erased to form an empty redundant partition, and then the data area is blocked in the step coffee. The data stored in one of the secondary data partitions is moved to the redundant partition of the redundant block. Moreover, in step S215, the data stored in another secondary data partitioning block in the data block 1〇1 (4) is erased to form an empty data partitioning block. And in the step gamma, the data temporarily stored in the redundant block in the foregoing step S214 is moved to the secondary data partition in the data block ι〇ι. At the most, in step 8217, the operation of ending the automatic update is ended, that is, the flash memory system returns to step SU1 to perform the normal operation of reading, erasing or writing the various external data. In summary, the complete update time of step S21 is about 2 〇〇 milliseconds, which can effectively ensure that the data block does not cause the charge problem stored by the floating question due to multiple readings, thereby causing each of the data blocks 101. The data stored in the secondary data partition is lost. • By the fact that the material structure of the invention (4) and its relatively new method can effectively avoid the loss of data due to the charge problem stored in the floating memory of the flash memory, it can shorten the time of booting. The data recovery time of the flash memory data area, as well as the reliability of the flash memory and the security of the data. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Various modifications and refinements are made, and the scope of the present invention is defined by the scope of the appended claims.
16 1354892 【圖式簡單說明】 第1A圖係闡示根據本發明的資料結構示意圖。 第1B圖係闡示根據本發明的資料結構中每一頁的組成示意圖。 第2圖係闡示本發明的資料即時更新方法流程圖。 【主要元件符號說明】 104 貧料區塊 105 冗餘區塊 • 106變換後備緩衝區 1010 頁面 101m次要資料分割區塊 冗餘分割區塊 S204、S210、S21、S211、S212、S213 101a主要資料分割區塊 101b、101c、101d、101e 102a、102b、102c、102η S20 ' S201 ' S202 ' S203 S214、S215 步驟 m 1716 1354892 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram showing the structure of a data according to the present invention. Figure 1B is a schematic diagram showing the composition of each page in the data structure according to the present invention. Fig. 2 is a flow chart showing the method for updating the data of the present invention. [Main component symbol description] 104 Poor block 105 Redundant block • 106 transform backup buffer 1010 Page 101m Secondary data partition block Redundant partition S204, S210, S21, S211, S212, S213 101a Main data Split block 101b, 101c, 101d, 101e 102a, 102b, 102c, 102n S20 ' S201 ' S202 ' S203 S214, S215 Step m 17