『1353001 —『1353001 —
100年27 日修正I 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種電子源及其製備方法，尤其涉及一種場 發射電子源及其製備方法。 【先前技術】 [0002] 場發射電子源係利用在外場作用下，從固體材料表面逸 出的電子來實現電子發射的一種電子源。場發射電子源 在低溫或者室溫下工作，與電真空器件中的熱發射電子 源相比具有能耗低、回應速度快以及低放電等優點，因 此用場發射電子源替代電真空器件中的熱發射電子源成 為了人們研究的一個熱點。 ^003]早期的場發射電子源以Spindt微尖結構為場發射陣列。 逆種基於微奈米加工技術製造的電子源包括：一絕緣基 底；一形成於該絕緣基底上的陰極電極；一形成於該陰 極電極上的發射體微尖陣列卜形成於該陰極電極上的 帶有開孔的絕緣層；一設置在該絕緣層上的栅極，且每 一個發射體微尖與-開孔對準。由於採用薄膜光刻工藝 ’陰極導電層和柵極的間距在微米級或者亞微米級。這 種電子源的主要問題係栅極和陰極電極之間的漏電嚴重 ，導致一般栅極電壓只能加到100¥左右，場發射電流密 度小’因此受到限制。 [0004] 奈米碳管（Carbon Nanotube, CNT)係一種新型碳材料 ，由日本研究人員Ii jima在1991年發現，請參見”以卜 ical Microtubules of Graphitic Carbon", S. Iijima，Nature’ v〇l.354, p56 (1991 )。奈米碳管 096147924 表單編號A0101 第4頁/共23頁 1003271718-0 100年07月27日修正替換頁 1353001 具有極優異的導電性能、良好的化學穩定性和大的長徑 比，且其具有幾乎接近理論極限的尖端表面積（尖端表面 積愈小，其局部電場愈集中），因而奈米碳管在場發射真 空電子源領域被廣泛應用。 [0005] 先前的奈米碳管場發射電子源的結構包括：一絕緣基底 ;一形成於該絕緣基底上的陰極電極；形成於該陰極電 極上的一高度密排的奈米碳管場發射體陣列；一設置於 陰極電極上的隔離體；一設置在該隔離體頂部的金屬柵 網。其中，該金屬柵網和陰極電極之間的間距在100微米 到數毫米。這種結構的缺點係發射體密度過高，電場屏 蔽效應嚴重，工作時往往只有少部分發射體發射電子， 故，很難做出高電流密度的電子源。另外，該場發射電 子源的隔離體的絕緣性設計不係最優，限制了加在金屬 栅網與陰極電極之間的工作電壓。 [0006] 有鑒於此，提供一種金屬栅網與陰極電極之間絕緣設計 較優，且可以有效防止發射體陣列密度過高而導致屏蔽 效應*能夠獲得較大密度的場發射電流的場發射電子源 及其製備方法實為必要。 【發明内容】 [0007] 一種場發射電子源，其包括：一絕緣基底；一陰極發射 電極設置於該絕緣基底上，且該陰極發射電極包括一陰 極電極和一陰極發射體設置於該陰極電極上；一隔離體 設置於該絕緣基底上；以及一金屬柵網設置在該隔離體 上，且該金屬柵網進一步延伸到陰極發射電極上方；其 中，該隔離體與陰極電極間隔設置。 096147924 表單編號 A0101 第 5 頁/共 23 頁 1003271718-0 1353001 100年07月27日修正势換1ϊ [0008] 一種場發射電子源的製備方法，其具體包括以下步驟： 提供一絕緣基底；在上述絕緣基底上製備一陰極發射電 極，且該陰極發射電極包括一陰極電極和一陰極發射體 設置於其上；在絕緣基底上製備一隔離體預製體，並對 該隔離體預製體進行曝光；在上述隔離體預製體上製作 一金屬柵網；以及除去上述隔離體預製體已經曝光部分 ，形成一隔離體與陰極電極間隔設置，從而得到一場發 射電子源。 [0009] 相較于先前技術，所述的場發射電子源，隔離體與陰極 電極間隔設置。這種結構有效增加了陰極電極與金屬柵 網之間的絕緣距離，解決了陰極電極和金屬栅網絕緣的 問題，可以大幅度提高柵極的電壓，從而獲得較大密度 的場發射電流。 【實施方式】 [0010] [0011] 以下將結合附圖對本技術方案作進一步的詳細說明。 請參閱圖1及圖2，本技術方案實施例提供一種場發射電 子源100，其包括：一絕緣基底102，一陰極發射電極 108設置於該絕緣基底102上表面，一隔離體116設置於 該絕緣基底102上表面，以及一金屬柵網120設置在該隔 離體116上，且該金屬柵網進一步延伸到陰極發射電極上 方，其中，該陰極發射電極108包括一陰極電極110和一 陰極發射體112設置於該陰極電極110上。 [0012] 096147924 所述的絕緣基底102為一絕緣基板，如：SOI (Silicon-On-Insulator，絕緣襯底上的石夕）基底或玻 璃基板等。本實施例中，優選SOI基底作為絕緣基底102 表單編號A0101 第6頁/共23頁 1003271718-0 1353001 100年07月27日核正替換頁 。該絕緣基底102包括一矽層104和一二氧化矽絕緣層 106設置於矽層104的表面。該二氧化矽絕緣層106的厚 度為100微米。 [0013] 所述的陰極電極110由導電材料製成，如金屬薄膜。本實 施例中，該陰極電極110優選為一高濃度摻雜的矽導電層 形成於緣基底102上。該陰極電極110的面積小於絕緣基 底102的面積。可以理解，陰極電極410的面積可以根據 場發射電子源100的大小來確定，且，該陰極電極110可 以根攄需要製作成不同的形狀，如：圓形、方形、正六 邊形或三角形等。該陰極電極110的厚度為10~ 100微米 〇 [0014] 所述的陰極發射體112為一微尖陣列，包括多個發射體微 尖114設置於陰極電極110上，且該多個發射體微尖114 按一定形狀分散排列。該發射體微尖114可以為三角形、 方形、矩形、圓形或其他形狀排列，本實施例中，優選 為密排正六邊形排列。該發射體微尖114可以係矽尖、鉬 尖、鎢尖或其他材料製備的可以用於場發射的微尖。該 發射體微尖114形狀不限，可為任意形狀的微尖，本實施 例中，優選為類圓錐形。每個發射體微尖114的高度為 1〜2微米，相鄰的發射體微尖114的尖端間距為1〜2微米 。多個發射體微尖114平行排列。採用微米尺度分散排列 的陰極發射體112作為場發射體，可以減小屏蔽效應，提 高場發射電流密度。請參閱圖3，該陰極發射電極108進 一步包括一表面修飾詹130，該表面修飾層130覆蓋於發 射體微尖114的表面，其厚度為卜10奈米，優選為5奈米 096147924 表單編號A0101 第7頁/共23頁 1003271718-0 1353001 100年07月λ·7 E修正替換頁 。該表面修飾層130為碳化姶、碳化锆 '碳化鈦或碳化鈮 等碳化物薄膜，優選的，該表面修飾層130選用碳化鈦或 碳化鍅，其逸出功分別為3. 82電子伏特和3. 32電子伏特 。表面修飾層13 0可以減小場發射電壓，增大場發射電流 密度。 [0015] 所述的金屬柵網120厚度為1~10微米。金屬柵網120包括 多個網孔124。金屬柵網120的形狀不限，網孔124形狀 不限。本實施例中，優選圓形金屬栅網120，網孔124為 正六邊形。該金屬栅網120為採用微納加工技術製作或採 用編織技術製作。該金屬柵網120具有很高的透過率，大 約在85%〜95%之間。此處，透過率指金屬柵網120的網孔 - 124與金屬柵網120的面積比。 [0016] 所述的隔離體116為一環形結構或“C”型結構，該隔離 體116包圍陰極電極110，且與陰極電極110間隔設置於 絕緣基底102上。本實施例中，該隔離體116為一“C”型 結構，其包括一本體138以及一形成於本體138上的開孔 118與一開口 126。該隔離體116的開孔118與陰極發射電 極108對應，開孔118面積大於陰極發射電極108的面積 ，使陰極發射電極108完全露出。該隔離體116的開口 126可以設置於隔離體116的側壁任意位置，開口 126寬 度小於5微米。該隔離體116的開口 126用來佈置陰極引線 128。該隔離體116與陰極電極110之間的水平距離大於 20微米，本實施例中，隔離體116與陰極電極110的水平 距離優選為50~100微米。該隔離體116材料為SU-8光刻 膠或其他厚膜曝光膠，其厚度為50〜1 000微米。進一步， 096147924 表單編號A0101 第8頁/共23頁 1003271718-0 [0017] [0017] 100年07月27日梭正替换頁 5隔離體116本體138的側壁122為一凹凸結構122。該凹 凸、’·。構122可以為棱錐狀，柱狀或半球狀。該凹凸結構 U可以增加陰極電極110與金屬柵網120之間的絕緣距 離。 所述的場發射電子源1 00進一步包括一陰極引線128，該 陰極引線丨28 一端與陰極電極110電性連接，另一端與外 電路連接。本實施例中，陰極引線128穿過開口 ι26與外 電路連接。該陰極引線128選自高熱導、低電阻材料，優 選為金膜。可以理解，通過開口 126將陰極引線12g引出 ，使陰極引線128不與隔離體116接觸，可以使隔離體 116與陰極電極110之間完全絕緣。 [0018] 所述的場發射電子源1〇〇進一步還包括_設置於絕緣基底 1〇2底部且與絕緣基底1〇2下表面接觸的散熱片（圖中未 顯示）或風扇等配套散熱系統。該散熱系統用來散發場 發射電子源100工作時產生的熱，降低其工作溫度。 [0019] 本實施例中，該隔離體11 6側壁122採用凹凸結構122， 並使隔離體116與陰極電極110間隔設置，該結構可以有 效增大陰極電極110與金屬柵網120之間的絕緣距離，解 決了陰極電極110和金屬柵網120絕緣的問題，可以大幅 度提高柵極的電壓，從而獲得較大密度的場發射電流。 另外’採用分散排列的發射體微尖陣列作為陰極發射體 112，這種結構避免了發射體之間的屏蔽作用。 請參閱圖4及圖5 ’本技術方案實施例還進一步提供場發 射電子源100的製備方法’其具體包括以下步驟： 096147924 表單編號A0101 第9頁/共23頁 1003271718-0 [0020] 1353001 · · 100年07月27日核正替换頁 [0021] 步驟一，提供一絕緣基底102。 [0022] 該絕緣基底102為一 SOI基底，包括一第一 ^夕層104、一 形成於該第一矽層104上的二氧化矽絕緣層106，以及設 置於該二氧化矽絕緣層106上的第二矽層132。其中，二 氧化矽絕緣層106厚度為100微米，第二矽層132的厚度 為10~100微米》 [0023] 步驟二，在上述絕緣基底102上製備一陰極發射電極108 ，且該陰極發射電極108包括一陰極電極110和一陰極發 射體112設置於其上。 [0024] 陰極發射電極108製備於第二矽層132上，具體包括以下 . 步驟： [0025] 首先，採用高濃度摻雜的方法，對第二矽層132進行部分 摻雜。 [0026] 所述的高濃度摻雜的方法為離子注入法或擴散法。掺雜 區域的面積小於第二矽層132的面積。 [0027] 其次，刻蝕掉第二矽層132上沒有摻雜的區域，形成一陰 極電極11 0。 [0028] 刻蝕可以採用反應離子刻蝕法、離子濺射刻蝕法、反應 氣體刻蝕法或其他刻蝕方法。 [0029] 進一步，製備上述陰極電極110的方法包括製備一陰極引 線128。該陰極引線128可以採用濺射法、氣相沈積法、 蒸鍍法或摻雜工藝製作。本實施例中，該陰極引線128選 自高熱導、低電阻材料，優選為金膜。 096147924 表單編號A0101 第10頁/共23頁 1003271718-0 1353001 ^ 1100年07月27日修正替換< [0030] 再次，在上述陰極電極110上製作陰極發射體112，得到 一陰極發射電極108。 [0031] 製作陰極發射體112的方法為微納加工技術。該陰極發射 體11 2為一密排正六邊形排列的矽尖陣列。每個矽尖為類 圓錐形，矽尖高度為卜2微米，間距為1~2微米。 [0032] 進一步，本實施例還可以包括：在上述陰極發射體112表 面製備一表面修飾層130。該表面修飾層130可以採用濺 射法、蒸鍍法或化學氣相沈積法製備。該表面修飾層130 覆蓋於陰極發射體112表面，厚度為1~10奈米，優選為5 奈米。該表面修飾層130為碳化給、碳化錯、碳化欽或碳 化鈮等碳化物薄膜，優選的，該表面修飾層130選用碳化 鈦或碳化鍅，其逸出功分別為3. 82電子伏特和3. 32電子 伏特。 [0033] 步驟三，在絕緣基底102上製備一隔離體預製體136，並 對該隔離體預製體136進行曝光。 [0034] 所述隔離體預製體136為一絕緣層，採用厚膜甩膠工藝製 作，且該隔離體預製體136覆蓋了上述陰極發射電極108 。該隔離體預製體136的厚度為50〜1 000微米。該隔離體 預製體136材料通常採用光刻膠，如：SU-8光刻膠或其他 厚膜曝光膠。 [0035] 所述曝光過程採用普通曝光技術即可實現。曝光過程主 要係對離體預製體136與開孔118和開口 126對應的地方 進行曝光，以利於後面步驟中將該曝光部分去除，得到 一開孔118與一開口 126。 096147924 表單編號A0101 第11頁/共23頁 1003271718-0 1353001 100年07月27日核正替換頁 [0036] 步驟四，在上述隔離體預製體136上製作一金屬柵網120 〇 [0037] 製作金屬栅網120具體包括以下步驟： [0038] 首先，在上述隔離體預製體136上鍍一金屬薄膜。 [0039] 所述鍍膜工藝可以採用濺射法、蒸鍍法或化學氣相沈積 法。金屬薄膜的厚度為1-10微米。 [0040] 其次，刻蝕上述金屬薄膜得到一金屬柵網120。 [0041] 刻蝕金屬薄膜採用普通刻蝕技術。該金屬柵網120採用密 排正六邊形排列，具有很高的透過率，大約在85%~95%之 · 間。 [0042] 步驟五，除去上述隔離體預製體136已經曝光部分，形成 一隔離體116與陰極電極110間隔設置，從而得到一場發 射電子源100。 [0043] 本實施例中，所述除去隔離體預製體136已經曝光部分的 方法為通過丙酮浸泡。浸泡過程在常溫下進行，浸泡時 間為10〜30分鐘。除去隔離體預製體136已經曝光部分後 ，形成一 “C”型結構的隔離體116 ，其包括一開孔118 與一開口126。其中，開孔118使陰極發射體112露出， 並與金屬栅網120通過開孔118相對，開口 126使陰極陰 線128露出且不與隔離體116接觸。 [0044] 在曝光過程中，由於光的反射，使得入射光與反射光形 成駐波效應，因此在隔離體116側壁會形成曝光不均勻， 這樣在除去隔離體預製體136已經曝光的部分後就會在隔 096147924 表單編號A0101 第12頁/共23頁 1003271718-0 1353001 100年07月27日修正替換頁 離體116側壁上形成凹凸結構122。該凹凸結構122可 以增加陰極電極110與金屬柵網120之間的絕緣距離。 [0045] 可以理解，本實施例中，可以在一絕緣基底1〇2上製備多 個場發射電子源1〇〇，得到一場發射電子源10{)陣列。製 備上述場發射電子源100陣列，進一步需要在絕緣基底 102底部設置一散熱片。也可以對該場發射電子源1〇〇陣 列配置一風扇或冷卻水系統。 [0046] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施例 ’自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0047] 圖1為本技術方案實施例場發射電子源的結構示意圖。 [0048] 圖2為沿圖1中線11 -11的剖視圖。 [0049] 圖3為本技術方案實施例％發射電子源的發射體微尖的结 構示意圖。 [0050] 圖4為本技術方案實施例場發射電子源的製備方法流程圖 〇 [0051] 圖5為本技術方案實施例場發射電子源的製備過程示意圖 〇 【主要元件符號說明】 [0052] 場發射電子源：1〇〇 096147924 表單編號A0101 第13頁/共23頁 1003271718-0 1353001 __=_ 1100年07月27日修正替換頁 [0053] 絕緣基底：102 [0054] 矽層：104 [0055] 二氧化矽絕緣層：106 [0056] 陰極發射電極：108 [0057] 陰極電極：110 [0058] 陰極發射體：112 [0059] 發射體微尖：114 [0060] 隔離體：116 [0061] 開孔：118 [0062] 金屬柵網：120 [0063] 凹凸結構：122 [0064] 網孔：124 [0065] 開口 ： 126 [0066] 陰極引線：128 [0067] 表面修飾層：130 [0068] 矽層：132 [0069] 隔離體預製體：136 [0070] 本體：13 8 096147924 表單编號A0101 第14頁/共23頁 1003271718-0100, 27, Revision I. VI. Description of the Invention: [Technical Field] [0001] The present invention relates to an electron source and a method of fabricating the same, and more particularly to a field emission electron source and a method of fabricating the same. [Prior Art] [0002] A field emission electron source is an electron source that realizes electron emission by electrons escaping from the surface of a solid material under the action of an external field. The field emission electron source operates at low temperature or room temperature, and has the advantages of low energy consumption, fast response speed, and low discharge compared with the heat emission electron source in the electric vacuum device, so the field emission electron source is used instead of the electric vacuum device. Thermal emission electron sources have become a hot topic of research. ^003] Early field emission electron sources used a Spindt microtip structure as a field emission array. The electron source manufactured by the micro-nano processing technology comprises: an insulating substrate; a cathode electrode formed on the insulating substrate; and an emitter microtip array formed on the cathode electrode is formed on the cathode electrode An insulating layer having an opening; a gate disposed on the insulating layer, and each of the emitters is aligned with the opening. Due to the thin film lithography process, the pitch of the cathode conductive layer and the gate is on the order of micrometers or submicrometers. The main problem with this electron source is that the leakage between the gate and the cathode electrode is severe, resulting in a general gate voltage that can only be added to about 100¥, and the field emission current density is small', thus being limited. [0004] Carbon Nanotube (CNT) is a new type of carbon material discovered by Japanese researcher Ii jima in 1991. Please refer to "Italian Microtubules of Graphitic Carbon", S. Iijima, Nature' v〇 L.354, p56 (1991). Carbon nanotubes 096147924 Form No. A0101 Page 4 of 23 1003271718-0 Correction replacement page 135301 of July 27 has excellent electrical conductivity, good chemical stability and Large aspect ratio, and it has a tip surface area close to the theoretical limit (the smaller the tip surface area, the more concentrated the local electric field), so the carbon nanotubes are widely used in the field of field emission vacuum electron sources. [0005] The structure of the carbon nanotube field emission electron source comprises: an insulating substrate; a cathode electrode formed on the insulating substrate; a highly dense array of carbon nanotube field emitters formed on the cathode electrode; a separator on the cathode electrode; a metal grid disposed on the top of the separator, wherein the spacing between the metal grid and the cathode electrode is between 100 micrometers and several millimeters. The disadvantage is that the emitter density is too high, the electric field shielding effect is serious, and only a small part of the emitter emits electrons during operation, so it is difficult to make a high current density electron source. In addition, the insulation of the field emission electron source isolation body The design is not optimal, and the working voltage applied between the metal grid and the cathode electrode is limited. [0006] In view of the above, the insulation design between the metal grid and the cathode electrode is superior, and the emitter can be effectively prevented. A field emission electron source capable of obtaining a large-density field emission current and a method for fabricating the same are required. [0007] A field emission electron source comprising: an insulating substrate a cathode emitter electrode is disposed on the insulating substrate, and the cathode emitter electrode includes a cathode electrode and a cathode emitter disposed on the cathode electrode; a separator is disposed on the insulating substrate; and a metal grid is disposed on the cathode On the spacer, and the metal grid further extends above the cathode emitter electrode; wherein the spacer is spaced from the cathode electrode 096147924 Form No. A0101 Page 5 of 23 1003271718-0 1353001 Correction of the potential of the field of July 27, 2001 [0008] A method for preparing a field emission electron source, which specifically includes the following steps: providing an insulating substrate; Preparing a cathode emitter electrode on the insulating substrate, and the cathode emitter electrode comprises a cathode electrode and a cathode emitter disposed thereon; preparing a spacer preform on the insulating substrate, and exposing the spacer preform Forming a metal grid on the spacer preform; and removing the exposed portion of the spacer preform to form a spacer spaced apart from the cathode electrode, thereby obtaining a source of electron emission. [0009] Compared to the prior art, the field emission electron source, the separator is spaced apart from the cathode electrode. This structure effectively increases the insulation distance between the cathode electrode and the metal grid, solves the problem of insulation between the cathode electrode and the metal grid, and can greatly increase the voltage of the gate, thereby obtaining a large-density field emission current. [Embodiment] [0011] The present technical solution will be further described in detail below with reference to the accompanying drawings. Referring to FIG. 1 and FIG. 2, the embodiment of the present invention provides a field emission electron source 100, which includes an insulating substrate 102. A cathode emitter electrode 108 is disposed on the upper surface of the insulating substrate 102, and a spacer 116 is disposed thereon. An upper surface of the insulating substrate 102, and a metal grid 120 disposed on the separator 116, the metal grid further extending over the cathode emitter electrode, wherein the cathode emitter electrode 108 includes a cathode electrode 110 and a cathode emitter 112 is disposed on the cathode electrode 110. [0012] The insulating substrate 102 described in 096147924 is an insulating substrate such as an SOI (Silicon-On-Insulator) substrate or a glass substrate. In this embodiment, an SOI substrate is preferably used as the insulating substrate 102. Form No. A0101 Page 6 of 23 1003271718-0 1353001 Correction page of July 27, 100. The insulating substrate 102 includes a germanium layer 104 and a germanium dioxide insulating layer 106 disposed on the surface of the germanium layer 104. The ceria insulating layer 106 has a thickness of 100 μm. [0013] The cathode electrode 110 is made of a conductive material such as a metal thin film. In this embodiment, the cathode electrode 110 is preferably formed of a high concentration doped germanium conductive layer on the edge substrate 102. The area of the cathode electrode 110 is smaller than the area of the insulating substrate 102. It can be understood that the area of the cathode electrode 410 can be determined according to the size of the field emission electron source 100, and the cathode electrode 110 can be formed into different shapes such as a circle, a square, a regular hexagon or a triangle. The cathode electrode 110 has a thickness of 10 to 100 micrometers. [0014] The cathode emitter 112 is a microtip array, and includes a plurality of emitter microtips 114 disposed on the cathode electrode 110, and the plurality of emitters are micro The tips 114 are arranged in a dispersed shape. The emitter microtips 114 may be arranged in a triangular, square, rectangular, circular or other shape. In this embodiment, a dense hexagonal arrangement is preferred. The emitter microtip 114 can be a tip made of a tip, a molybdenum tip, a tungsten tip or other material that can be used for field emission. The shape of the emitter microtip 114 is not limited and may be a microtip of any shape. In this embodiment, it is preferably a conical shape. The height of each emitter microtip 114 is 1 to 2 microns, and the tip spacing of adjacent emitter microtips 114 is 1 to 2 microns. A plurality of emitter microtips 114 are arranged in parallel. The use of a micron-scale dispersed cathode emitter 112 as a field emitter can reduce the shielding effect and increase the field emission current density. Referring to FIG. 3, the cathode emitter electrode 108 further includes a surface modification layer 130 covering the surface of the emitter microtip 114 having a thickness of 10 nm, preferably 5 nm 096147924. Form No. A0101 Page 7 of 23 1003271718-0 1353001 100 years of July λ·7 E correction replacement page. The surface modification layer 130 is a carbide film of tantalum carbide, zirconium carbide, titanium carbide or tantalum carbide. Preferably, the surface modification layer 130 is made of titanium carbide or tantalum carbide, and the work function is 3.82 eV and 3, respectively. 32 electron volts. The surface modification layer 130 can reduce the field emission voltage and increase the field emission current density. [0015] The metal grid 120 has a thickness of 1 to 10 microns. Metal grid 120 includes a plurality of cells 124. The shape of the metal grid 120 is not limited, and the shape of the mesh 124 is not limited. In this embodiment, a circular metal grid 120 is preferred, and the mesh 124 is a regular hexagon. The metal grid 120 is fabricated using micro-nano processing techniques or by weaving techniques. The metal grid 120 has a high transmittance of between about 85% and 95%. Here, the transmittance refers to the area ratio of the mesh-124 of the metal grid 120 to the metal grid 120. [0016] The separator 116 is an annular structure or a “C” structure. The separator 116 surrounds the cathode electrode 110 and is spaced apart from the cathode electrode 110 on the insulating substrate 102. In this embodiment, the spacer 116 is a "C" type structure, and includes a body 138 and an opening 118 formed in the body 138 and an opening 126. The opening 118 of the spacer 116 corresponds to the cathode emitter electrode 108. The area of the opening 118 is larger than the area of the cathode emitter electrode 108, so that the cathode emitter electrode 108 is completely exposed. The opening 126 of the spacer 116 can be disposed anywhere on the sidewall of the spacer 116, and the opening 126 has a width of less than 5 microns. The opening 126 of the spacer 116 is used to arrange the cathode lead 128. The horizontal distance between the spacer 116 and the cathode electrode 110 is greater than 20 micrometers. In the embodiment, the horizontal distance between the spacer 116 and the cathode electrode 110 is preferably 50 to 100 micrometers. The spacer 116 material is SU-8 photoresist or other thick film exposure adhesive having a thickness of 50 to 1 000 micrometers. Further, 096147924 Form No. A0101 Page 8 of 23 1003271718-0 [0017] [0017] The reversing body of the body 138 of the spacer 116 is a concave-convex structure 122. This concave convex, '·. The structure 122 can be pyramidal, columnar or hemispherical. The uneven structure U can increase the insulation distance between the cathode electrode 110 and the metal grid 120. The field emission electron source 100 further includes a cathode lead 128. One end of the cathode lead 28 is electrically connected to the cathode electrode 110, and the other end is connected to an external circuit. In this embodiment, the cathode lead 128 is connected to the external circuit through the opening ι26. The cathode lead 128 is selected from a high thermal conductivity, low resistance material, preferably a gold film. It will be appreciated that the cathode lead 12g is drawn through the opening 126 such that the cathode lead 128 does not contact the spacer 116, and the spacer 116 and the cathode electrode 110 can be completely insulated. [0018] The field emission electron source 1 further includes a heat sink (not shown) disposed on the bottom of the insulating substrate 1〇2 and in contact with the lower surface of the insulating substrate 1〇2 or a supporting heat dissipation system such as a fan. . The heat dissipation system is used to dissipate the heat generated by the field emission electron source 100 during operation and to lower its operating temperature. In this embodiment, the sidewalls 122 of the spacer 116 are provided with the concave-convex structure 122, and the spacers 116 are spaced apart from the cathode electrodes 110, and the structure can effectively increase the insulation between the cathode electrodes 110 and the metal grids 120. The distance solves the problem of insulation between the cathode electrode 110 and the metal grid 120, and the voltage of the gate can be greatly increased, thereby obtaining a large-density field emission current. In addition, a dispersed array of emitter microtip arrays is used as the cathode emitter 112, which avoids shielding between the emitters. Please refer to FIG. 4 and FIG. 5 'The embodiment of the present technical solution further provides a method for preparing the field emission electron source 100', which specifically includes the following steps: 096147924 Form No. A0101 Page 9 / Total 23 Page 1003271718-0 [0020] 1353001 · July 27, 100, nuclear replacement page [0021] Step one, an insulating substrate 102 is provided. [0022] The insulating substrate 102 is an SOI substrate, including a first layer 104, a ceria insulating layer 106 formed on the first buffer layer 104, and disposed on the ceria insulating layer 106. The second layer 132. The thickness of the second germanium layer 132 is 10 to 100 micrometers. [0023] Step 2, preparing a cathode emitter electrode 108 on the insulating substrate 102, and the cathode emitter electrode 108 includes a cathode electrode 110 and a cathode emitter 112 disposed thereon. [0024] The cathode emitter electrode 108 is prepared on the second buffer layer 132, specifically including the following. Step: First, the second buffer layer 132 is partially doped by a high concentration doping method. [0026] The high concentration doping method is an ion implantation method or a diffusion method. The area of the doped region is smaller than the area of the second germanium layer 132. [0027] Next, an undoped region of the second germanium layer 132 is etched away to form a cathode electrode 110. [0028] The etching may be performed by reactive ion etching, ion sputtering etching, reactive gas etching, or other etching methods. Further, the method of preparing the cathode electrode 110 described above includes preparing a cathode lead 128. The cathode lead 128 can be formed by a sputtering method, a vapor deposition method, an evaporation method, or a doping process. In this embodiment, the cathode lead 128 is selected from a high thermal conductivity, low resistance material, preferably a gold film. 096147924 Form No. A0101 Page 10 of 23 1003271718-0 1353001 ^ Correction Replacement on July 27, 1100 [0030] Again, a cathode emitter 112 is fabricated on the above cathode electrode 110 to obtain a cathode emitter electrode 108. [0031] The method of fabricating the cathode emitter 112 is a micro-nano processing technique. The cathode emitter 11 2 is an array of tips arranged in a close-packed regular hexagon. Each tip is conical, with a tip height of 2 microns and a pitch of 1 to 2 microns. [0032] Further, the embodiment may further include: preparing a surface modification layer 130 on the surface of the cathode emitter 112. The surface modification layer 130 can be prepared by a sputtering method, an evaporation method, or a chemical vapor deposition method. The surface modification layer 130 covers the surface of the cathode emitter 112 and has a thickness of 1 to 10 nm, preferably 5 nm. The surface modification layer 130 is a carbonization film, a carbonization, a carbonization or a carbonization of a carbide film. Preferably, the surface modification layer 130 is made of titanium carbide or tantalum carbide, and the work function is 3.82 eV and 3, respectively. 32 electron volts. [0033] Step 3, a spacer preform 136 is prepared on the insulating substrate 102, and the spacer preform 136 is exposed. [0034] The spacer preform 136 is an insulating layer which is formed by a thick film silicone process, and the spacer preform 136 covers the cathode emitter electrode 108. The separator preform 136 has a thickness of 50 to 1 000 micrometers. The spacer body 136 material is typically a photoresist such as SU-8 photoresist or other thick film exposure paste. [0035] The exposure process can be realized by a common exposure technique. The exposure process primarily exposes the body preform 136 corresponding to the opening 118 and the opening 126 to facilitate removal of the exposed portion in a subsequent step to provide an opening 118 and an opening 126. 096147924 Form No. A0101 Page 11 of 23 1003271718-0 1353001 July 27, 2007 Nuclear Replacement Page [0036] Step 4, a metal grid 120 is fabricated on the above-mentioned separator preform 136 [0037] The metal grid 120 specifically includes the following steps: [0038] First, a metal thin film is plated on the separator preform 136. [0039] The plating process may be a sputtering method, an evaporation method, or a chemical vapor deposition method. The metal film has a thickness of from 1 to 10 μm. [0040] Next, the metal film is etched to obtain a metal grid 120. [0041] The etching of the metal film is performed by a common etching technique. The metal grid 120 is arranged in a closely packed regular hexagonal shape and has a high transmittance of between 85% and 95%. [0042] Step 5, removing the exposed portion of the spacer preform 136, forming a spacer 116 spaced apart from the cathode electrode 110, thereby obtaining a field electron source 100. [0043] In the embodiment, the method of removing the exposed portion of the separator preform 136 is by acetone soaking. The soaking process is carried out at room temperature for 10 to 30 minutes. After the exposed portion of the spacer preform 136 has been removed, a "C" shaped spacer 116 is formed which includes an opening 118 and an opening 126. The opening 118 exposes the cathode emitter 112 and is opposed to the metal grid 120 through the opening 118. The opening 126 exposes the cathode cathode 128 and does not contact the separator 116. [0044] During the exposure process, the incident light and the reflected light form a standing wave effect due to the reflection of the light, so that uneven exposure is formed on the sidewall of the spacer 116, so that after the portion of the spacer preform 136 that has been exposed is removed, The embossed structure 122 is formed on the side wall of the outer body 116 at 096147924, Form No. A0101, Page 12 of 23, 1003271718-0, 1353001, July 27, 100. The relief structure 122 can increase the insulation distance between the cathode electrode 110 and the metal grid 120. [0045] It can be understood that, in this embodiment, a plurality of field emission electron sources 1 制备 can be prepared on an insulating substrate 1 〇 2 to obtain an array of emission electron sources 10{). To prepare the above array of field emission electron sources 100, it is further required to provide a heat sink at the bottom of the insulating substrate 102. It is also possible to configure a fan or cooling water system for the field emission electron source array. [0046] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the patent application of the present invention is not limited thereto. Equivalent modifications or variations made by those skilled in the art to the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0047] FIG. 1 is a schematic structural view of a field emission electron source according to an embodiment of the present technical solution. 2 is a cross-sectional view taken along line 11-11 of FIG. 1. 3 is a schematic diagram showing the structure of an emitter microtip of a %-emission electron source according to an embodiment of the present technology. 4 is a flow chart of a method for preparing a field emission electron source according to an embodiment of the present invention. [0051] FIG. 5 is a schematic diagram of a process for preparing a field emission electron source according to an embodiment of the present invention. [Main component symbol description] [0052] Field emission electron source: 1〇〇096147924 Form No. A0101 Page 13/Total 23 Page 1003271718-0 1353001 __=_ July 27, 2017 Revision Replacement Page [0053] Insulation Base: 102 [0054] Layer: 104 [ 0055] cerium oxide insulating layer: 106 [0056] cathode emitting electrode: 108 [0057] cathode electrode: 110 [0058] cathode emitter: 112 [0059] emitter microtip: 114 [0060] separator: 116 [0061 Opening: 118 [0062] Metal grid: 120 [0063] Concavo-convex structure: 122 [0064] Mesh: 124 [0065] Opening: 126 [0066] Cathode lead: 128 [0067] Surface finish: 130 [0068]矽 Layer: 132 [0069] Separator Preform: 136 [0070] Body: 13 8 096147924 Form No. A0101 Page 14 of 23 1003271718-0