TWI343716B - Digital-to-analog converter and method thereof - Google Patents

Description

1343716 VII. Designated representative map: (1) The representative representative of the case is: (2). (2) The symbol of the symbol of the representative figure in this case is briefly described: 200: digital to analog converter; 210: digital code generator; 220, 230: decoder; and 240, 250: switching circuit array. 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: None 0. Description of the invention: [Technical field of invention] The present invention relates to a digital-to-analog converter, and in particular to an improvement A method and apparatus for digital to monotonicity in an analog converter. [Prior Art] A digital-to-analog converter (DAC) is an important device for many application circuits. Digital to analog converter is an analog circuit with multiple output characteristics controlled by a digital control word. The art is generally related to a digital-to-analog converter, and 1343316 can be applied to a general-purpose digital-to-analog converter, for example, using a digitally controlled oscillator (digitally contro丨led〇sciUat〇r DC) The application of 'Digital Control Oscillator is a device for generating a periodic signal, wherein the periodic signal has a frequency controlled by the digital control character. The digitally controlled oscillator usually includes an adjustable circuit. An adjustable circuit element whose value is used to determine the oscillation frequency of the digitally controlled φ oscillator. This digital control character is used to set the value of the adjustable circuit component to determine the oscillation frequency. For example, one has An LC oscillator approximating the oscillation frequency of 4 = 1 / you #) can be used to control a digitally controlled oscillator having a fixed inductance 1 and a variable; = capacitor C. The capacitance value of this variable capacitor c is controlled by the digital control sub-element. Since the digitally controlled oscillator receives the digital control word and outputs an analog signal corresponding to one of the digital control characters, the digitally controlled oscillator is also an embodiment of a digital to analog converter. Φ Figure 1A is a schematic diagram of a conventional digitally controlled variable capacitor 1〇〇. The variable capacitor 100 includes a decoder 11 with a fixed capacitor CF, a plurality of switching capacitors (such as C0, Cl, C2), and a plurality of switches (swjtch) (eg, s〇, S1, S2). The decoder 11 receives a digital control character w and generates a plurality of binary data (e.g., D[0], D[1], D[2]) to control the switches separately. The effective capacitance of this variable capacitor 1 Ce is Ce / / · Ι) / ^ + C7 · D / 77 + C2 . Therefore, this variable capacitor! The oscillation frequency of one of the Lc oscillators is determined by the digital control character W. 1343716 The three important properties of this digitally controlled oscillator are the range ' - (range ), resolution, and monotonicity. The range and accuracy of the values of the adjustable circuit components determine the range and resolution of the digitally controlled oscillator, respectively. For example, the resolution of the previously mentioned LC oscillator is determined by the minimum capacitance of the cut capacitors (such as CO, Cl, C2), and the range is determined by the maximum total effective capacitance. The value (such as Ce / / ( max ) ...) and the minimum total effective capacitance value (such as Q / y {min) φ ) is determined. If the value of the tunable circuit component changes together (as the digital control character increases or decreases, so that each capacitance value increases or decreases), the monotonicity of the digitally controlled oscillator will be revealed. For example, 'If a larger control character produces a larger 'total effective capacitance value, then the monotonicity of the previously mentioned LC oscillator will also be revealed." A digitally controlled oscillator is usually Add to a digital phase lock loop (DPLL) to generate one of the target frequencies • Output the clock. One of the digital control characters used in the digitally controlled oscillator is a closed loop to control the oscillation frequency of the digitally controlled oscillator. This digital control character has a finite resolution, and the instantaneous oscillation frequency of this digitally controlled oscillator also has a limited resolution. In fact, the instantaneous oscillation frequency of this digitally controlled oscillator cannot be as accurate as this target frequency. A conventional digital phase-locked loop typically requires a strictly monotonic digitally controlled oscillator to ensure stable operation. For example, when a larger digit control character corresponds to a larger output frequency, then the digital phase-locked loop will attempt to reduce the digit control character to lower the output frequency above ^43716 or attempt to increase this digit. The control character is in the loop - (iv) the internal frequency. In the stable digital phase lock phase, the digital control character usually changes between two values ψ 2 , one of the two values meets the frequency of one of the target frequencies slightly higher than the frequency of the f and the other two values - Then, the output frequency is slightly lower than the target frequency, so that an average output frequency is close to the target frequency. ^ This change in the digital control character causes multiple undesired jitters (jiUer) in the output clock. These jitters can be reduced by increasing the resolution of the digitally controlled oscillator so that the instantaneous oscillation frequency can be closer to the target and frequency. However, due to the occurrence of noise, a digital phase-locked loop is prone to interference, and the steady-state value of the digital phase-locked loop will temporarily drift away due to the aforementioned interference. Fortunately, if this digitally controlled oscillator is monotonic, the effect of this interference will only occur temporarily (temp〇rary). For example, if the digital control character drifts too high (or too low) due to the presence of interference, the digital phase-locked loop will detect that the output frequency is too high (or too low) and will decrease (or increase) ) The digital control word's flat φ mean to correct this error. However, if the digitally controlled oscillator is not strictly monotonic, the digital phase-locked loop may adjust the digital control characters in the wrong direction, causing such jitter or loop instability. One method uses a thermometer-code decoding scheme to ensure that a digitally held oscillator is in a strictly monotonic state. Fig. 1B is a diagram showing an example of decoding a two-digit control character W into one of eight binary data (e.g., D1, ... D7). Referring to the embodiment of the LC oscillator mentioned in the previous '14331716, each incremental change in the digital control character w will cause an additional control bit to be turned on = this total effective capacitance value. This ensures that the digital control oscillator is monotonic. In general, it is very difficult to ensure monotonicity without using a thermometer code decoding architecture. However, this thermometer code destructuring typically requires a very large number of switching capacitors. Therefore, how to reduce the number of switching elements used in the control oscillator, and the fact that the virtuality can still ensure monotonicity is an urgent problem to be solved. [Invention] In order to solve the above problems, the present invention A digital pair analogy is proposed: a converter (or digital control analog circuit) that includes a digital code generator that receives a digital input character (or digital control character) and enters a character based on the digital input character At least the first digit code and the second digit code are generated, which is determined by the state of one of the digit code generators. In one embodiment, when the second digit code is detected to have a wraparound (Wrap_ar〇Und) condition, the digital code generator undergoes a state transition. In one embodiment, the digital code generator changes the states during steady state operation to enhance the digital to analog converter, without relying on a strict thermometer-code decoding scheme. Monotonic (m〇n〇t〇nicky). In an application embodiment of the present invention, the digital input character is mapped such that the first-digit code represents the most significant bit mos (mos^significant bh, MSB) and the second digit code of the digit-input character. Represents the least significant bit of this digit input sub-unit (ΙμΜ (10), 1343716 LSB). A method for detecting the surround condition is to determine when the second digit code is numerically increased to correspond to a decrease in the value of one of the digit input characters or to decrease numerically to correspond to an increase in the value of one of the digit input characters. . In one embodiment, the first digit code has a first norm value, and the second digit code has a second range value, and the second range value partially overlaps the first range value. For example, the second digit code has a maximum value that is greater than (e.g., at least twice) a value represented by one of the least significant bits of the first digit code. ▲ In one embodiment of the invention, the finite state machine has a first state and a second state. The second digit code is generated in the first state by performing a two-module operation (m〇dul〇operati〇n) by using the digit input character as a dividend (dividend), and the second digit code is generated. In the second state, a one-module operation is performed by using one of the digital input characters and an offset (offset) as a dividend. A common divisor uses a modulo operation in the first state and a modulo operation in the second state. In one embodiment, the shift has a value that is less than (e.g., almost - half) one of the common divisors. In an embodiment of the invention, the digital to analog converter further includes a first decoder and a second decoder (e.g., a binary code decoder or a hidden code decoder). The first decoder maps the first-digit code to the binary data of the first group, and a first switching circuit array generates a first analog signal to correspond to the binary data of the first group. The second decoder maps the second digit code to the binary data of the second group and a second array of switching circuits to generate a second analog signal to correspond to the 1343716 binary data of the second group. The first analog output signal and the second combination are compared with the digital input character. In the first example, the binary data of each group controls a group of switching circuits in respective sources to generate a current-to-current ratio output. To be used by the & to the common circuit node to match the digital pair analogy conversion, - output signal. In an application embodiment, the analog to digital conversion is used in the digital control, and the output value is a variable capacitance value to be determined according to the digital input character - the vibration rate: Furthermore, the present invention proposes A method of converting a digital input character into an analog signal (or a digital control analog circuit), and second: inputting a character and a rule according to the digit to generate a digital code and a second digit A code, wherein the law is determined by a variable value from one of the values. For example, the method switches between a first algorithm and a second algorithm (tGggle) (or exchanges (_)) = the second digit code is generated by f, wherein the timing of the switching is: Whether -valued to - relatively high value (eg, close to a highest = ^^ or from a relatively high value (eg, a value close to a maximum) to a relatively low value over a short period of time (eg, A U-clock cycle or a small number of clock cycles produces an abrupt or an instantaneous (as well) change. ~ In an embodiment, the first digit code is used to indicate that the digit input word is most valid. The second digit code represents the least significant bit of the digit input character. A type of fast change is detected in the second digit code (eg, a boundary condition or a ring 1343716) The method includes determining, by the time value, the value of the second digit code corresponding to the decrease of one of the digit input characters or the decrease of the value corresponding to the increment of one of the digit input characters. Digital code and second digit code The range of values may be partially overlapping. In an embodiment, the least significant bit of the first digit code has a number of ones, the value being almost one-half of the maximum of one of the second digit codes. In an embodiment, The first algorithm includes the first modulo operation as one of the two divisors by the input character, and the second algorithm includes the sum of one of the input sub-elements and an offset as a dividend a second modulo operation. A common divisor is used in the first modulo operation and the second modulo operation, the common divisor having a value greater than (e.g., almost twice) the offset One of the values. This first digit code is generated by dividing by - a difference, where the difference is the offset between the digit input character and the second digit code. The digital code is converted into a first analog output signal and the second binary code is converted into a second analog output signal, wherein the combination of the first analog output signal and the second analog output signal results in an analogy k Number corresponds to the digit input character. In an implementation The first digital code and the second digital code are respectively decoded into binary data of the respective first and second groups. In an application embodiment, the first digital code is obtained by using a binary code decoder. Mapping to the binary data of the first group, and the second digit code is mapped to the binary data of the second group by using a thermometer code decoder. The binary data of the first group is controlled by the first switching circuit. a first group of switches in the array and the binary data of the first group is controlled in the second switching circuit array

J 12 1343716 = Switch of the two groups. The output of the second switching circuit array is switched by the output of the first switching circuit array to generate such a location. To: discuss the presently preferred embodiments in detail. However, it should be understood that the present invention provides a number of applicable inventive concepts which are embodied in a wide variety of material contexts. The specific embodiments discussed are merely illustrative of specific ways in which the invention may be used without limiting the scope of the invention. [Embodiment] The present invention relates to reading a digital input word for a tb output signal. The method and apparatus are discussed in detail below with reference to a number of embodiments. It should be understood, however, that the present invention is to be construed as being limited to the specific embodiments. The specific embodiments discussed are merely illustrative of specific ways of using the invention and do not limit the scope of the invention. For example, as previously mentioned, digital to analog converters (or digitally controlled analog circuits are used for digitally controlled oscillations). Please refer to FIG. 2, which is a circuit of a digital-to-analog converter 200 according to the present invention. The digital-to-analog converter 2 includes a digit, a generating circuit (which can be decoded by a dividing circuit) The circuit is implemented by a finite state machine 210 for receiving a digital input character (w) to generate two output numbers Code (wj and W2). A coarse decoder (c〇arse(jec〇der) 220 system decodes (or maps) a 13 1343716 one-digit code (wi) into B1 bit data or a first group of binary data. And a fine decoder (fme decoder) 230 decodes a second digit code (W2) into two; B2 bit data (eg, D2 [〇: 2 B2__ a second group of two data). This first-group second feed is used to provide a plurality of coarse switched circuit arrays (24) and is used to clamp a plurality of (for example, B^-changing circuits) within the coarse switching circuit array 24''. The second set of binary data is used to provide to a fine-switching circuit array 250 and to control a plurality of (eg, 'double Β 2) switching circuits within the fine switching circuit array. This coarse tangential array 240 The output terminal and the donor terminal of the fine switching circuit array 250 are coupled to the - common circuit node to generate the digital pair analogy "" analog output signal. The so-called "rough," and "fine, only degree The difference in the (adjusted scale) is similar in its circuit architecture. The 6-Hai fine decoder 230 is a thermometer code decoder. Meanwhile, the 'Dan decoder 220 can be a binary code decoder or a w code decoder. 疋苟 / 皿汁a & In an embodiment A, the implementation bits of the switching circuit arrays 240, 250 control the variable capacitors. The circuits are the same as or similar to the i-th, the digital control variable capacitors. In another embodiment, the two-switches 2 array 24G, 25G implementation is used as a digital eye, see Figure 3, Figure 3, as an example of a digital control::: (current S0urce), where the digital control motor source 300 contains A plurality of current sources 31〇, 31丨, the current is achieved by connecting a binary control signal to one of the gate terminals of the = 〇SFET), wherein the binary 1343716 control signal is, for example, from the first group or the second One of the binary data of the group. As can be seen by reference to the embodiment of Figure 1, these switching circuit arrays 240, 250 are implemented as the digitally controlled capacitors in the operating circuit. The coarse switching circuit array 24A includes B1 ^capacitors ^ (eg, C0 〇), C1 (", CW··) and binary data from the first group (eg, 'D1[0], Dl[l], Dl [2]···.) separately control the m switches. Similarly, the fine switching circuit array 250 includes twice as many B2 capacitors (eg, C0(2), C1(2), C2(2), etc. And the second set of B2 switches are separately controlled by the second set of binary data (eg, etc.). In an embodiment, the fine decoder 23 is a thermometer code decoder and is here The fine switching circuit array 25 。 亥 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些 些In an embodiment, the coarse decoder 220 is also a gradual code decoder and the plurality of voltaic devices in the coarse switching circuit array 24 大致 are substantially equal weighted (eg, Has almost the same capacitance value, wherein the capacitance value is represented by a coarse capacitance value C (c°arse). In another embodiment, this rough The decoder 22 is a binary, and the code decoder and the capacitors in the coarse switching circuit array 240 are weighted by a power of 2. For example, such a device There are respective approximations y.Ckoarse}, ^lc^oarse}, '') and the like. In another embodiment, the coarse capacitance value c(c°arse) is almost B2 times the fine capacitance value c (fine In other words, the maximum total capacitance of the double B2 capacitors in the fine cut 15 1343716 circuit array 250 is almost twice the minimum capacitance of the Bi capacitors in the coarse switching circuit array 240. The coarse capacitance value c (e°ai"se) of the minimum capacitance value among the electric grids in the coarse switching circuit array 24〇 can also be referred to as the most 'low effective bit of the coarse switching circuit array 24〇. Element (LSB). This fine capacitance value is the least significant bit used for each of the capacitors in the fine switching circuit array 250 and is also referred to as the least significant bit of the fine switching circuit array 25A. • In the example, the least significant bit ratio of the coarse switching circuit array 240 is finer than The least significant bit of the switching circuit array 250 is almost higher than (greater than) B2 times. When one embodiment of the digital code generating circuit 210 is a dividing circuit, the first digital code (W1) is the digital input character. (w) with a divisor of the divisor, the second digit code (W2) is the remainder of the digit input character (W) and the divisor, wherein the divisor is related to the ratio of the switching circuit arrays 240, 250 In another embodiment, the digital code generating circuit 210 can be implemented by a hardware or a software or a mixture of the two. In other words, the first digital code (W1) and the second digital code (W2) can be decoded or It is generated by looking up the table. In another embodiment, the digital code generation circuit 210 is implemented by a finite state machine (FSM) 400. Figure 4 illustrates a finite state machine 400. The finite state machine 400 receives a digital control character W and generates a first output character wi and a second output character W2. In an embodiment, the finite state machine 4 includes a first register (REG) 420 for receiving the digital control 1343716 character w and outputting one of the digital calibration characters. One of the predetermined values is a predetermined control character. Similarly, a first modulus operator (or modulo operation circuit) MOD 410 also receives the digital control character and performs the following mathematical operation W2(〇)=m〇d ( W,2.B ) To generate a first intermediate character W2 (0). In other words, after the digital control character is divided by the division operation of 2·Β, the first intermediate character is a modulus 〇B can be any positive integer. In one embodiment, B is a positive integer of a power of two, so designed to simplify the hardware circuitry. In one embodiment, the fine decoding device 230 in Fig. 2 is a thermometer code decoder, and b is equivalent to B1. The digital control character is also provided to a first summing operator 460' which also combines the digital control character with an offset (〇ffset) (B). An output signal of one of the first summation operators 460 is supplied to a second modulo operator MOD 411, and a second is generated by executing the following mathematical expression: W2(1)= mod ( W+B, 2B ) Intermediate character W2 (1). Also, after the sum of the digital control character and the offset is divided by φ by 2B, the second intermediate character is a modulus, the first intermediate character and the second intermediate The characters are provided to a first multiplexer 430 to produce a second output character W2. The second output character W2 is selected from the first intermediate character W2(0) and the second intermediate word W2(1) according to the value of a variable state STATE. The first intermediate character W2(0) and the second intermediate character W2(1) are also provided to a second multiplexer 431 to generate a tentative character 1343716 W2 (tent). The temporary character W2 (tent) is selected from the first intermediate character W2 (G) and the second intermediate word W2 (1) according to the value of a previous variable state STATE (pfev). A second register REG421 receives the variable state STATE and outputs the previous variable state STATE (prev). Of course, there are other implementations, such as using only one mode of operation, one adder, and one multiplexer. The value of W+B is output by the adder; the input of the multiplexer receives the values of W+B and W, and selects one (W+B or W) according to the variable state STATE to output to the mode. An arithmetic circuit that performs a modulo operation on the input value (W+B or W) to generate the second output character W2. The second output word W2 is provided to a third register REG 422 to generate a previous second output character W2 (pfev) to conform to the previous value of the second output word. This previous second output character W2_ev) is provided to a logic circuit LOGIC 450. The logic circuit 450 also receives the digital control character W, the previous digital control character W (I^ev) and the temporary character W2 (tent)' and performs the following logical operations: TOGGLE= ( ( W > W(prev) & W2(tent) <W2(prev) ) | (W<w(prev) & W2 (tent) > W2(prev))) to generate a logic signal TOGGLE. In the above equation, the symbol "&" represents a logical "AND" operation, and the symbol Τ' represents a logical "OR" operation. The aforementioned logical operation is a method of determining a wrap-around condition within the second output character. Of course, this can be achieved by using other methods. For example, in another embodiment of the present invention, the digital code generator (ie, the finite state machine 400 described above) 1343716 also includes a detection circuit for detecting a boundary condition. This boundary condition is the basis for judging the above wrap-around condition. It is defined by a second digit code that is incremented as the digital input signal value is decremented, or by a second digit code value that is decremented as the digit input signal value is incremented. This logic signal TOGGLE is supplied to a logic operator XOR 440. The logical operator XOR 440 also receives the previous variable state STATE(prev) to generate the variable state STATE. For example, the current value of this variable state STATE is derived by performing a logical exclusive OR or exclusive-OR operation on the logical signal TOGGLE and the previous variable state STATE (pi_ev). Regardless of when this logic signal TOGGLE is high (or set to high), this variable state STATE will change state. Finally, the finite state machine 400 further includes a second summation operator 461 and a divider 470 for generating the first output character W1 by performing the following mathematical operation W1 = (W-W2) /B. Fig. 5 is a view showing a state of a finite state machine 400 of Fig. 4. For example, the finite state machine 400 has two states: a first state (e.g., State 0 or STATE = 0) and a second state (e.g., State 1 or STATE = 1). In this first state, the first and second output characters are derived by the following operations:

Wl=( W- mod( W, 2.B)) /B ; and W2=mod( W,2.B). In this second state, the first and second output characters are derived by the following operations:

Wl=( W-mod ( W+B, 2 B)) /B ; and W2=mod ( W+B, 2.B).

19 1343716 In one embodiment, when the logic signal TOGGLE is set to *1, the finite state machine 400 transitions from one state to another. When the second output character has a wrap-around condition, the logic signal TOGGLE is set to one. The method for detecting the surround condition is to determine when the current value of one of the digital control characters W is greater than a previous value of one of the digital control characters. Meanwhile, one of the second output characters is less than the temporary character. The previous value of one of the digit control characters (in other words, one of the second output characters is less than this temporary character)

φ two output characters one of the previous values); or, one of the digital control characters W is less than the previous value of one of the digital control characters, and one of the second output characters is greater than the previous character The digital control word is one of the previous values (in other words, one of the second output characters is temporarily, the word 7L is greater than one of the previous output characters, and the second value is the temporary value of the second output of the element. ASSumpti〇n) is determined that the finite state machine 400 is still in a current state. It is also possible to detect when the second output character is generated by other methods. In a digital phase lock The loop (digita丨phase丨〇仏1〇叩) should, in the embodiment, the digital control character is generated in a closed loop c ed-l〇op) and is quickly changed in the loop. Dry f (ghtCh), big value (big VaUie) change or more = shape, is not expected to occur during steady state operation. In the case of a stable value, the digital control character is usually used in two values or in the small value of the number of control characters to generate i β 聋 = the number of extreme values of the extra code. Then the second round of code out may occur around to correspond to multiple changes (or slight changes) within the digital control 20 1343716 characters. The code can be close to the second low value of the second input (four). The phase value (for example, having the range of the - (10) range: the amount of change) (four) (G ate) to correspond to

Under the circumstance of this digital control material - a small increase / decrease. Here, the H-first output code is compensated for by taking the fast value change, and some of the changes are about the same value _ but for the second output, the opposite direction (> 'in--hypothetical value Not 2' is also the first input: the least significant bit is weighted by the second most significant bit of the second output code that is close to the high power. • f is implemented, the fasts in the first and second output codes are offset from each other 'do not—the combined output signal has a significant η/ as controlled by the first and second output codes Total effective capacitance value). However, in fact, limited component tolerance and other manufacturing constraints can result from interference with one of the combined output signals. For example, due to the limited component tolerance of the capacitors in the coarse switching circuit array 24 and the fine switching circuit array 250, the least significant bit of the first output code is not exactly higher than the second The B-weight of the least significant bit of the output code, therefore, a glitch will occur on the total effective capacitance. In one embodiment, this total effective capacitance value produces an undesired rapid change when the second output rocker wraps around. In an embodiment, the finite state machine 400 is configured to detect the surrounding conditions (or boundary conditions) that may be within the second output code and to switch a variable state STATE to cause a state change. A different set of squares 21 1343716 is used to derive one of the first and second output codes from each other. Thus, it is possible to prevent undesired changes in the first and second output codes. For example, the logic signal TOGGLE is set to 丨 to indicate a possible sth. > or a second output code that is close to the boundary limit of the second output code and the finite state machine 4 〇〇 changes to a different state, wherein the different state is a value in which the second output code has a relatively close range of its own range. Changes in different states may not eliminate an initial interference in a combined output code, wherein the combined output code is controlled by the first and second output codes. However, this second output code W2 is deviated (or adjusted to be away from) its own boundary value (or extreme value 〇 and 2B) and after changing these states, it is concentrated to its own mid-range value (eg The second is almost B). Therefore, any disturbance or rapid change becomes a one-time event. The frequency of these state changes is somewhat dependent on B (or the range of this second output code). • In one embodiment, the range of the second output code is significantly larger (e.g., a relatively large B) such that these state changes do not occur frequently during steady state operation within the digital phase locked loop application circuit. Figures A and 6B show graphical representations of the total effective capacitance values corresponding to a digital control character to illustrate certain criteria of the present invention. For example, during steady state operation, the digital control character varies over a range close to a steady state value. If the finite state machine 400 is currently in the first state (STATE 0) and the steady state value is almost an integer multiple of 2.B, a surround condition may occur for the second output code with 22 1343716 corresponding to This number controls multiple changes within a character. As can be seen in =, this surround situation will inevitably cause a jump (or rapid change) in the total. As shown in the figure from the figure = 〇 ot control system 1 yuan = in w (ss) soil 2B (four) move and this finite state: when the second 〇 is in the first state, the total effective capacitance value can have a rapid change to this total A rapid change in the effective capacitance value, when one of the possible surrounding conditions is available, this is the case: 働: the first state is switched to the second state (STATEi=;, multiple surrounds within the first output code or Further reducing the amount of rapid change in her effective capacitance value 'at the same time, as shown in Fig. 6B:: number: control word 70 continues to change around the steady state value w (four) to completely switch to the second state and effectively again The second output code. w(8) is in the state of 匕t. ##The digital control character gradually tends to-, then multiple surround conditions in the second output code may be sent. Therefore, if there is no strong interference, this digit is made. When the control word production is close to B, the second output code does not wrap around and the wide control sub-element is used to correspond to various steady-state changes, and the total effective electric value changes smoothly during steady state operation (eg, There is no rapid change two) a. The mistake is chosen by a large enough Depreciation, the round-robin situation in this second output code will not exceed one event in the steady-state operation of the digital phase-locked loop. 23 1343716 In the group stepping embodiment, this second output is dumped. To - thermometer code J = i such as 'fine decoder 23 〇' to generate for control - variable:: two? The data 'in which the variable capacitance value is the total effective capacitance value, and the θ production is the application range of the digital phase-locked loop, the ςϋ decoder effectively takes this total effective capacitance value to actually count this number ^ One of the monotonic functions of the control unit 70 is revealed. Furthermore, the one-two-two decoder can be used to generate a binary paradigm according to the second output code, and the binary data system controls the second switching capacitors of the second = ί2: and the total effective capacitance value The most = inside is still in the "surrounding" situation. Although the strict monotonicity is not smashed, the _ change in the value of the capacitor is still only - and only occurs in a surround condition. The present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection of the invention is subject to the definition of the attached claim. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram showing an example of a conventional digitally controlled variable capacitor; FIG. 1B is a diagram of mapping a digital control character w to one of eight binary data. 1 is a block diagram showing one of the digital control analog circuits according to an embodiment of the present invention; FIG. 3 is a diagram showing an embodiment of a switching current source array; 24 1343716 4 A block diagram showing an embodiment of a finite state machine for the digital control analog circuit in the second figure; FIG. 5 is a schematic diagram showing a state of the finite state machine in FIG. 4; The 6A diagram depicts a transfer function of one of the analog output signals to correspond to a graph of one of the digits of the input character, wherein the digitized input character is in a state in which the analog output signal changes drastically during steady state operation. Under the scenario);

The geese Ϊ6i diagram shows a transfer graph of one of the analog output signals in a pair of graphs, wherein the phenotype analog output signal at the digit input character has a plurality of gradual transfer morphological finite state machine switching (toggling) To one

25 1343716 [Description of main component symbols] 100: Variable capacitor; 200: Digital to analog converter; 210: Digital code generation circuit; 110, 220, 230: Decoder; 240, 250: Switching circuit array; 300: Switching current Source array; 310, 311, 312: current source; 400: finite state machine; 410: first mode operator; 411: second mode operator; 420: first register REG; 421: second register REG; 422: third register REG; 430: first multiplexer; 431: second multiplexer; 440: logic operator XOR; 450: logic circuit LOGIC; 460: first summation operator; : second sum totalizer; 470: divider; and S0~S3: switch. 26

Claims (1)

1343716 . X. Patent Application Fan I·. A digital-to-analog converter comprising: - a digital code generator for generating at least - a digital horse and a second digital code according to a digital input signal, The digital code generator has a first state invitation-second state, wherein the digital code generator is generated when the digital code generator_to the second digital code has a wraparound (and p-around) condition State conversion; • a first decoder that outputs - the first group data according to the first digit code; - a second decoding H' is based on the second new code to output - a second group data; a first switching circuit _, according to the first material to generate a chirp output signal; and - the second switching circuit array is based on the second group data to generate a second analog output signal, wherein the first analog output signal and the first The combination of the two analog output signals results in an analog output signal corresponding to one of the digital input signals. § 2. The digital-to-analog converter of item 1, wherein the detection of the surround condition detects that the second digit code increases the value or the first digit code of the digital digit due to the decrease of the value of the digit input signal The value of the digital input signal is increased to decrease the value. The digital-to-analog converter of item 1, wherein the digital code generator comprises: a first modulo operator for receiving the digital round-in signal and inputting the digital input Signaling to perform a first algorithm 'to generate a second digit code corresponding to the first state, and a second modulo operator for receiving the 27 1343716 revised correction on November 26, 1999 Page. The digit is input to the § §, and a second algorithm is performed on the digit input signal to generate the second digit code corresponding to the second state. 4. The digital-to-analog converter of item 3, wherein the digital code generator further comprises: a signal operation unit, and inputting the signal according to the second digital code and the digital number to generate the first digital mother. 5. The digital-to-analog converter of item 1, wherein the first switching circuit array includes a plurality of switched current sources, and the switching elements of the switching current source are broken. Controlled by individual bit values in the first group of data. The digital-to-analog converter of item 1, wherein the second switching circuit array includes a complex-current source, and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ The value is controlled by the value. 7. As the first! The digital-to-analog converter of the item, wherein the first digital code represents an upper significant bit of the digital input signal and has a value of a first range, and the second digit code table complements the low-dimensional bit of the input signal And having a value of - the second norm, and the value of the second paste touches the value of -_ partially. 8. The digital-to-analog converter of item 7, wherein the second digit code has a maximum value, and the maximum value is the lower significant bit of the first digit code. 28 is called 3716 99 years. At least two times the value shown on the replacement page is corrected on the 26th of the month. 9. The digital-to-analog converter of claim 1, wherein the second digit code is in the first state by performing a modulo operation by using the digit input signal as a dividend (modulo) The operation is performed, and the second digit code is generated in the first state by performing a modular operation by using a sum of the digital input signal and an offset (〇ffset) as a dividend. 10. The digital-to-analog converter according to item 9, wherein - the common divisor (di W) is operated by the mechanical H-string, and the offset is substantially half of the common divisor . H. The digital-to-analog converter of item 1, wherein at least one of the first decoder and the second decoder is a binary code decoder. The digital _transfer, the 鄕-decoder and the second decoding n are at least the thermometer code decoder. η, as shown in the first item, the digital ratio is turned over, and the towel-city circuit array and the 5 Xuan-di "a switching circuit array of at least its φ _, the capacitor, < one contains a digital control variable _对_换29 1343716 November 26, 1999 revised replacement page! 5• The digital-to-analog converter as described in the above item, wherein the analog output signal is determined by the - (iv) capacitance value, The variable capacitance value determines the vibration frequency of the train based on the digital input signal. The digital-to-analog converter of item 1, wherein the digital code generator comprises: - an anger test for the price measurement - boundary condition (10), such as (d) (10), and the boundary condition is determined by - The increment value of the second digit code applied to the decrement value of the digital input signal is defined by a pair of decrement values of the second digit code applied to an increment value of the digit input signal. Π.- A method for converting a digital-to-digital input signal into an analog signal, the method comprising: recording, according to the number, a product, a 帛-number _ and a second digit code, the first digital code system corresponding The high-order bit of the digit input signal, the second digit code corresponds to the low-order bit of the digit input signal; 冨 detecting that the first digit of the code has a surround (wrap — ar〇un(J In the case of a situation, switching between at least two algorithms to generate the second digit code; converting the first digit code to a first analog round-out signal; converting the second digit code to a second analog round And combining the first analog output signal with the second analog output signal to generate 30 T343716. The modified replacement page of November 26, 1999 corresponds to an analog output signal of the digital input signal. 18. As recited in item 17 The method for detecting whether the second digit code has a circumscribing condition comprises: determining a rapid change of the second digit code to determine whether the second digit code has the surround condition, wherein The rapid change is The digital input 彳. The value of the number is decreased and the δ 第一 first digit code is increased by the value, or the second digit code is decreased by the value of the digital input signal. ^ 19. The method of claim 17, wherein The first digit code and the second digit code have a value of an overlapping range. 20. The method of claim 17, wherein the lowest value of the first digit code is substantially the maximum value of the 5th digit of the first digit code. The method of claim 17, wherein the step of switching between the at least two algorithms to generate the second digit code comprises: switching between the broad algorithm and the first algorithm Generating the second digit code 'where the first algorithm includes a digital input signal as a dividend - a modulo operation and the second algorithm uses the digital input signal and an offset The method of claim 21, wherein the step of generating the first-digit code comprises: calculating a difference between the dividend and the second digit code. Value; and the difference value into 31 134371 6-year replacement page row division to generate the first digit code = the method according to item 21, the shot-marriage fine is different from the second mode operation in the first mode, and the common divisor is substantially the deviation The method of item n, wherein the step of converting the first digit code further comprises: providing - the first decoder mapping the first digit code into a material; and using the first - Group data to control - the first 2 of the first - _ lose & record. State to produce 25. As described in the 24th, the paper miscellaneous:: for: the second group of materials; (four) _ second group f Controlling the H-switching circuit array to generate the second analog wheeling signal. At least one of the decoders is a method as described, wherein the first (four) (10) «two' hexadecimal decoder is the second The decoder 27' is the method described in item 25, wherein the $3 is a small thermometer. The Dane-3Hide-Decoder is one of the thermometers. 28. The method of clause 25, wherein the switching circuit array is at least wherein: the switching circuit array and the second, 匕 comprise a digitally controlled variable capacitor. The method of claim 25, wherein at least one of the first switching circuit array and the second switching circuit array comprises: There are a plurality of switching current sources (30). The conversion method converts the wide-bit input signal into an analog signal, and the method includes: inputting a signal according to the digit to generate a first digit code; State § § selection operation in a first state or a second state, the φ second digit code is generated, wherein 'the first digit code corresponds to a high significant bit of the digit input signal, the second digit The code system corresponds to the low significant bit of the digital input signal; converting the first digital code to a first analog output signal; converting the second digital code to a second analog output signal; and combining the first analog output signal And outputting a signal analogous to the second analog to produce an analog output signal corresponding to the digital input signal. 31. The method of claim 30, further comprising: detecting one of the second digit codes • a boundary condition to output the status signal, wherein the boundary condition is - corresponding to the digital input signal The decrement value of the second digit code is defined by an increment value or is defined by a pair of decrement values of the second digit code applied to one of the digit input signals. 3= The method of item 3G, further comprising: a wrap-ar_d condition of the second digit code to output the status signal. 33 31 The method described in the 32nd, ^ from - relatively low value to - relative: number:: the condition is the condition of the second digital value. The number of the question is from the relatively high value to the phase 34 34. If the 30th speed is changed to turn the heart digits, the scale is fast. The number is as described in Item 3G, wherein the first digit code and the first A value with an overlapping range. The method of claim 30, wherein the most significant value of the first digit code is substantially at least half of a maximum value of the second digit code. The method of claim 30, wherein the first algorithm and the second method are respectively used in the first state and the second state, wherein the third method includes the digital input signal as a One of the first modulo operations; and the second algorithm uses the sum of the digital input signal and an offset as a second modulo operation of a dividend. 38. The method of clause 37, wherein a common divisor is used in the first mode operation and the second mode operation, the common divisor being substantially twice the offset. Eleven, round: