TWI342071B - - Google Patents
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- TWI342071B TWI342071B TW96102450A TW96102450A TWI342071B TW I342071 B TWI342071 B TW I342071B TW 96102450 A TW96102450 A TW 96102450A TW 96102450 A TW96102450 A TW 96102450A TW I342071 B TWI342071 B TW I342071B
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Description
九、發明說明： 【發明所屬之技術領域】 本發明係關於一種形成包含鉬（M0)之層之基板之製 造方法及基板處理裝置。 【先前技術】 在近年來’液晶顯示裝置用薄膜電晶體（在以下、顯 不為TFT )之電極及配線材料係使用由習知之鉻（在以下、 顯不為Cr )系材料開始至低配線電阻之鋁（在以下、顯示 為A1)系或鉬（在以下、顯示為M〇)系之材料。但是，m〇 係具有所謂容易氧化之性質，M〇氧化物係具有所謂容易溶 解於水等之性質。因此，在M〇使用於TFT之電極等之狀態 下，生成於Mo表面之Mo氧化物（Μ〇〇χ)係產生所謂在洗 淨製私而溶出於洗淨液之問題。溶出於洗淨液之氧化物 (系產生所謂在基板之乾燥後而再附著於TFT之二次污染， 成為顯示不均等之TFT之功能不良之原因。 就前述之問題而言，以逆參差（staggered)型a_Si (amorphous Silicon (非結晶矽））TFT之刮面構造，來 作為例子，按照圖5而進行說明。逆參差（staggered)型 a Si之TFT係最多製造成為液晶顯示裝置用TFT之構造。 正如圖5所示，逆參差（staggered )型a — Si之TFT1 21 係在藉由玻璃（glass)等來形成之基板122上而形成閘極 (gate)電極層123之後，連續地成膜閘極（gate)絕緣 層124、半導體層125及歐姆接點ι26[Technical Field] The present invention relates to a method of manufacturing a substrate for forming a layer containing molybdenum (M0) and a substrate processing apparatus. [Prior Art] In recent years, the electrode and wiring material of a thin film transistor (hereinafter, not shown to be a TFT) for a liquid crystal display device have been used since the conventional chromium (hereinafter, not explicitly Cr) material is used to low wiring. A material of aluminum (hereinafter referred to as A1) or molybdenum (hereinafter referred to as M〇). However, m〇 has a property of being easily oxidized, and M〇 oxide has a property of being so easily dissolved in water or the like. Therefore, in the state in which M is used for an electrode of a TFT or the like, the Mo oxide formed on the surface of Mo causes a problem that it is dissolved in the cleaning liquid by washing. Oxide dissolved in the cleaning solution (which causes secondary contamination after the substrate is dried and then adheres to the TFT), which causes a malfunction of the TFT which exhibits unevenness. In terms of the aforementioned problem, the inverse parameter is The staggered type a_Si (amorphous silicon) TFT scratch-off structure will be described as an example with reference to Fig. 5. The reverse-staggered type a Si TFT is manufactured at most as a TFT for a liquid crystal display device. As shown in Fig. 5, a reverse-staggered type a-Si TFT1 21 is formed continuously on a substrate 122 formed by glass or the like to form a gate electrode layer 123, and is continuously formed. Membrane gate insulating layer 124, semiconductor layer 125 and ohmic contact ι26
2185-8619-PF 5 1342071 而進行圖案化（patterning)。半導體層125係形成為通 道（channel)層，以非結晶矽（a_Si)作為材料。此外， 歐姆接點（ohmic contact)層126係形成為半導體層125 和電極之歐姆接點（ohmic contact)，以低電阻之非結晶 矽（n+a — Si)作為材料。然後，作為源極（s〇urce)電極 層127及汲極（drain)電極層128係成膜含有鉬（M〇)之 材料而進行圖案化（patterning)。在圖案t(patterning) 之後，除去在源極（source)電極層127及汲極（drain) 電極層128之形成之所使用之阻劑（resist)。 在源極（source)電極層127及汲極（drain)電極層 128之表面而包含Mo之狀態下，藉由氧化而在電極層之表 面，生成Mo氧化物。該Mo氧化物係具有對於水或鹼 (alkali)性之液體等而容易溶解之性質。因此，在形成 源極（source)電極層127及汲極（drain)電極層128之 後而除去阻劑之純水洗淨之時，有在洗淨液而溶出M〇氧化 物之狀態發生。然後’在乾燥浸丨責於洗淨液之TFT 1 21之 時’在TFT121之上，析出Mo氧化物1 30。 正如圖5所示’在析出之Mo氧化物130附著於TFT121 之通道（channel )之表面時，透過M〇氧化物130而容易 流動表面漏（1 eak )電流。因此，無法控制TFT 121之導通 /截止（on/ of f )，降低電流—電壓特性。結果，有所謂 產生使用TFT121之液晶顯示裝置之畫像不均等之畫像缺 陷之問題發生。 解決Mo氧化膜之附著之技術係揭示於專利文獻1。圖2185-8619-PF 5 1342071 and patterning. The semiconductor layer 125 is formed as a channel layer using amorphous yttrium (a_Si) as a material. Further, an ohmic contact layer 126 is formed as an ohmic contact of the semiconductor layer 125 and the electrode, and a low-resistance amorphous 矽 (n+a - Si) is used as a material. Then, as a source electrode layer 127 and a drain electrode layer 128, a material containing molybdenum (M〇) is formed and patterned. After the pattern t (patterning), the resist used in the formation of the source electrode layer 127 and the drain electrode layer 128 is removed. In a state where Mo is contained on the surface of the source electrode layer 127 and the drain electrode layer 128, Mo oxide is formed on the surface of the electrode layer by oxidation. This Mo oxide has a property of being easily dissolved in water or an alkali liquid or the like. Therefore, when the source electrode layer 127 and the drain electrode layer 128 are formed and the pure water from which the resist is removed is washed, the M 〇 oxide is eluted in the cleaning liquid. Then, at the time of drying and dipping the TFT 1 21 of the cleaning liquid, over the TFT 121, Mo oxide 1 30 was precipitated. As shown in Fig. 5, when the deposited Mo oxide 130 adheres to the surface of the channel of the TFT 121, the surface leakage (1 eak ) current is easily transmitted through the M 〇 oxide 130. Therefore, the on/off of the TFT 121 cannot be controlled, and the current-voltage characteristics are lowered. As a result, there has been a problem that image defects in which the image of the liquid crystal display device using the TFT 121 is uneven are generated. A technique for solving the adhesion of a Mo oxide film is disclosed in Patent Document 1. Figure
2185-8619-PF 6 1342071 6係顯示該實施狀態之示意圖。正如圖6所示，藉由在表 面形成Mo氧化物1 30之基板上’塗敷及加熱六甲基二石夕氨 炫（（CH〇 3SiNHSi (CH3) 3)，而反應於基板表面之氫氧 基（〇H)，產生氨（NHO。可以結合該氨和Mo氧化物130， 成為（NH4) 2M〇3〇1D，除去Mo氧化物130。藉由在形成包含 Mo之配線131之後，在進行洗淨處理之前，除去M〇氧化 物130 ’而防止由於Mo氧化物130所造成之顯示缺陷。 φ 此外，在專利文獻2，揭示：將殘留在藉由Mo所形成 之源極（source)電極層和汲極（drain)電極層上之有機 物予以除去之技術。該有機物係形成在源極（s〇urce )電 極層和汲極（drai η )電極層上之有機絕緣膜之殘留物，揭 不所謂藉由氧電漿（plasma)而除去殘留在有機絕緣膜之 開口部之有機物之技術。正如前面之敘述，不同於除去由 Mo配線來溶出之Mo氧化物之技術。 此外’在專利文獻3，揭示：在M〇及A1系金屬之二 籲層構造之源極（source)電極層和汲極（drain)電極層， 在Mo之成膜時，添加氮之技術。可以藉由在M〇添加氮， 而使知Mo及A1系金屬之蝕刻（etching)速率（rate)接 近，在二層之同時，進行蝕刻（etching)。因此，正如前 面之敘述，不同於除去由M〇配線來溶出之M〇氧化物之技 術。 【專利文獻1】曰本特開平7一30119號公報 【專利文獻2】曰本特開平1〇一 135465號公報 【專利文獻3】日本特開平09 — 148586號公報2185-8619-PF 6 1342071 6 shows a schematic diagram of this implementation state. As shown in FIG. 6, hydrogen is reacted on the surface of the substrate by coating and heating hexamethyldiazepine ((CH〇3SiNHSi(CH3)3)) on the substrate on which Mo oxide 130 is formed. The oxy group (〇H) produces ammonia (NHO. The ammonia and Mo oxide 130 may be combined to become (NH4) 2M〇3〇1D, and the Mo oxide 130 is removed. After forming the wiring 131 containing Mo, Before the cleaning treatment, the M 〇 oxide 130 ′ is removed to prevent display defects due to the Mo oxide 130. φ Furthermore, in Patent Document 2, it is revealed that the source is formed by Mo. a technique for removing an organic substance on an electrode layer and a drain electrode layer, the organic substance forming a residue of an organic insulating film formed on a source electrode layer and a drain electrode layer. The technique of removing the organic substance remaining in the opening portion of the organic insulating film by plasma plasma is different from the technique of removing the Mo oxide eluted by the Mo wiring as described above. Document 3, reveals: in the M〇 and A1 metal The source electrode layer and the drain electrode layer of the layer structure, the technique of adding nitrogen during the film formation of Mo. It is possible to know the Mo and the A1 metal by adding nitrogen to the M layer. The etching rate is close, and etching is performed at the same time as the two layers. Therefore, as described above, it is different from the technique of removing the M 〇 oxide which is eluted by the M 〇 wiring. 。 特 特 7 7 7 7 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135
2185-8619-PF 7 1342071 【發明内容】 【發明所欲解決的課題】 可以藉由專利文獻1之構造，藉由除去析出M〇氧化 物’而防止顯示品質之降低。但是，該方法係對於通常之2185-8619-PF 7 1342071 [Problem to be Solved by the Invention] By the structure of Patent Document 1, it is possible to prevent deterioration of display quality by removing precipitated M〇 oxide. However, this method is for the usual
溥膜圖案（pattern)形成用之塑兹，技Λ M 又用之氣程，追加Mo氧化膜之除 去用之處理製程。因此，成為增加製造處理製程數之結果， 產生所謂降低製造之生產性之問題。 此外，也在除去Mo氣化铷夕你 , 札化物之後，即使是在短時間也將 包含Mo之層來配置於大氣中之狀態下，在表面，再度生成The pattern of the ruthenium film is formed, and the technique used for the ΛM is added, and the process for removing the Mo oxide film is added. Therefore, as a result of increasing the number of manufacturing processes, there is a problem that the productivity of manufacturing is lowered. In addition, in addition to the Mo gasification, you will be re-generated on the surface even if the layer of Mo is placed in the atmosphere even in a short time.
Mo氧化物，無法完全地除去Μ〇氧化物。 本發明之目的係提供一種並無增加製程數而除去肋 氧化物同時抑制Μο氧化物對於基板之附著之基板之製造 方法及基板處理裝置。 【用以解決課題的手段】 本發明之基板之製造方法’係在基板上，形成包含鉬 (Mo)之層’在露出前述之包含鉬（M〇)之層之狀態下， 對於前述之基板，至少進行使用氮氣（gas)之大氣壓電聚 (pi asma )處理。 此外，本發明之基板處理裝置，係'包括：對於露出包 含翻（Mo)之層所形成之基板來除去形成在前述之包含翻 (Mo)之層之鉬（Mo)氧化物而形成鉬（M〇)氮化物的大 氣壓電漿（plasma)處理部。 此外’本發明之配線基板係在形成於基板上而包含钥 (Mo)之層，具有形成於前述之包含鉬（M〇)之層之表面Mo oxide, which cannot completely remove niobium oxide. SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate manufacturing method and substrate processing apparatus which do not increase the number of processes and remove rib oxide while suppressing adhesion of ruthenium oxide to a substrate. [Means for Solving the Problem] The method for producing a substrate of the present invention is based on a substrate, and a layer containing molybdenum (Mo) is formed in a state in which the layer containing molybdenum (M〇) is exposed, and the substrate is At least atmospheric pi asma treatment using nitrogen gas is performed. Further, the substrate processing apparatus of the present invention includes a method of removing molybdenum (Mo) oxide formed in the aforementioned layer containing the (Mo) layer to form a substrate formed by exposing a layer including a layer of (Mo). M〇) Atmospheric piezoelectric plasma treatment unit of nitride. Further, the wiring board of the present invention is a layer including a key (Mo) formed on the substrate and having a surface formed on the layer containing the molybdenum (M〇).
2185-8619-PF 8 1342071 之鉬（Mo )氮化物。 【發明效果】 如果藉由本發明的話’則能夠提供—種並無增加製程 數而除去MQ氧化物同時抑制Mq氧化物對於基板之附著之 基板之製造方法及基板處理裝置。 【實施方式】 在以下，說明本發明之理想實施形態。由於說明之明 確化，因此，以下之s己載及圖式係適當地進行省略及簡化。 此外’由於說明之明確化’因此，配合於需要而省略重複 之說明。 實施形態1 首先，就本實施形態之液晶顯示裝置（並未圖示）而 進行說明。首先，使用密封（seal)劑而貼合在玻璃（giass) 基板形成TFT和各個電極線及儲存電容之TFT陣列（array ) 基板以及在玻璃（glass)基板形成公用（common)電極及 R(紅）、G(綠）和B(藍）之彩色渡光片（colorfilter) 之對向基板。然後，在這些基板之縫隙，注入液晶，藉由 密封劑而密封住入口’形成液晶面板（panel)。接著，將 構裝有驅動用LSI或面板（Panel )控制用1C之驅動電路 基板’連接在液晶面板（Pane 1 )。此外，將背光單元 (backl ight uni t)，配置在TFT陣列（array )基板之背 部，完成液晶顯示裝置。該液晶顯示裝置係可以使得藉由 驅動電路所驅動之液晶面板（Pane 〇 ’藉由來自背光單元 2185-8619-PF 9 x^42〇71 (backlight unit)之光之透過，而顯示畫像。 接者’按照圖1而說明TFT陣列（array )基板之製造 方法。圖1係顯示將包含像素電極部分之TFT21之構造予 以顯示之剖面圖，但是，省略其他之部分。首先，使用純 水或酸等而洗淨例如藉由光透過性之玻璃（g 1 ass )、聚碳 .酸酯（polycarbonate)、丙烯酸酯（acrylate)樹脂等之 所形成之基板22。接著，形成閘極（gate )電極層23。具 •體地說’在基板22上’藉由濺鍍（sputtering)法而成膜 例如鉬组（MoTa )膜。接著，在M〇Ta膜上，塗敷光阻劑 (Photoresist)，在烘烤（bake)後，進行既定之圖案 (pattern)形狀之遮罩（masking)而進行曝光處理。然 後’例如藉由有機丙烯（a 1 ka 1 i )系之顯影液而進行顯影， 圖案化（patterning)光阻劑（ph〇toresist)。接著，例 如使用鱗酸及硝酸之混合溶液而進行濕式蝕刻 (etching )。藉此而使得M〇Ta膜形成為要求之圖案 φ (pattern)形狀。接著，由基板22之上，來除去光阻劑 (photoresist)，洗淨除去光阻劑（ph〇t〇resist)之基 板22。經過以上之製程，在基板22之上，形成閘極（以以） 電極層23，利用該閘極（gate )電極層23，來作為閘極 (gate)配線。 接著，使用化學氣相成膜（CVD )法，成膜閘極（gate ) 絕緣層24而覆蓋基板22上之閘極（gate)電極層23。同 樣地，層積於該閘極（gate)絕緣層24之上而成膜成為半 導體層25材料之非結晶矽膜。此外，在該非結晶矽層進Molybdenum (Mo) nitride of 2185-8619-PF 8 1342071. According to the present invention, it is possible to provide a substrate manufacturing method and a substrate processing apparatus which do not increase the number of processes and remove the MQ oxide while suppressing the adhesion of the Mq oxide to the substrate. [Embodiment] Hereinafter, a preferred embodiment of the present invention will be described. Since the description is clear, the following suffixes and drawings are omitted and simplified as appropriate. Further, the description is omitted because the description is clarified. (Embodiment 1) First, a liquid crystal display device (not shown) of this embodiment will be described. First, a sealing agent is attached to a giass substrate to form a TFT and an array of TFT electrodes of respective electrode lines and storage capacitors, and a common electrode and R (red) are formed on a glass substrate. ), the opposite substrate of the color filter of G (green) and B (blue). Then, liquid crystal is injected into the gap between the substrates, and the inlet is sealed by a sealant to form a liquid crystal panel. Next, a driving circuit substrate '' of the drive LSI or panel control 1C is connected to the liquid crystal panel (Pane 1). Further, a backlight unit (backl ight uni t) is placed on the back of the TFT array substrate to complete the liquid crystal display device. The liquid crystal display device can display a picture by a liquid crystal panel driven by a driving circuit (Pane 〇' is transmitted by light from a backlight unit 2185-8619-PF 9 x^42 〇 71 (backlight unit). The method of manufacturing a TFT array substrate will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the structure of the TFT 21 including the pixel electrode portion, but the other portions are omitted. First, pure water or acid is used. The substrate 22 formed by, for example, light-transmissive glass (g 1 ass), polycarbonate, acrylate resin, or the like is washed, etc. Next, a gate electrode is formed. Layer 23. The body is formed on the substrate 22 by a sputtering method such as a molybdenum group (MoTa) film. Next, a photoresist is applied on the M〇Ta film. After baking, a masking of a predetermined pattern shape is performed to perform exposure processing, and then development is performed, for example, by a developing solution of an organic propylene (a 1 ka 1 i ) system. Patterning photoresist (ph Next, wet etching is performed using, for example, a mixed solution of scalylic acid and nitric acid, whereby the M〇Ta film is formed into a desired pattern φ shape. Then, on the substrate 22, The photoresist is removed, and the substrate 22 of the photoresist is removed. After the above process, a gate electrode layer 23 is formed on the substrate 22, and the electrode layer 23 is used. A gate electrode layer 23 is used as a gate wiring. Next, a gate insulating layer 24 is formed by a chemical vapor deposition (CVD) method to cover the gate on the substrate 22 ( The electrode layer 23 is similarly laminated on the gate insulating layer 24 to form an amorphous ruthenium film which is a material of the semiconductor layer 25. Further, the amorphous ruthenium layer is formed.
2185-8619-PF 10 1-342071 行離子摻雜（i on dope )，形成n+非結晶矽膜，形成歐姆 接點（ohmic contact )層26。在該層積上，形成阻劑 (resist)圖案（pattern) ’ 進行乾式钱刻（etching)。 触刻（etching)η +非結晶矽膜、非結晶矽膜和氮化矽（SiN) 膜而形成要求之圖案（pattern )形狀。接著，由基板22 之上’來除去光阻劑（photoresist)，洗淨除去光阻劑 (photoresist)之基板22。經過以上之製程而在基板22 之上’形成半導體層25、閘極（gate )絕緣層24和歐姆 接點（ohmic contact)層 26。 接著，形成源極（source )電極層27和汲極（drain) 電極層28。首先，藉由錢鑛（sputtering)法而成膜形成 源極（source)電極層27和汲極（drain)電極層28之金 屬膜。例如Mo—Al —Mo層積膜，形成於基板上。在該層積 膜上而形成阻劑圖案（resist pattern)之後，藉由乾式 触刻（etch i ng )而進行通道（channe 1 )钱刻。藉此而使 得Mo— A1 — Mo層積膜，形成為要求之圖案（pattern)形 狀’源極（spurce)電極層27和汲極（drain)電極層28 係形成利用作為源極（source )配線之配線。接著，由基 板22之上’來除去光阻劑（photoresist)，洗淨除去光 阻劑（photoresist )之基板22，但是，就具體之洗淨方 法而言，在以後’詳細地進行敘述，在該階段，進行用以 在包含Mo之配線之表面來形成氮化物之處理。 接著，由源極（source )電極層27和汲極（draiη ) 電極層28之上開始形成鈍化 (passivation)膜 29。形成 2185-8619-PF 11 1342071 鈍化（passivation)膜29而覆蓋源極（source)電極層 27和汲極（drain)電極層28。首先’例如藉由cvd法而 將成為鈍化（passivation )膜29材料之氮化^(siN)膜， 成膜於基板22之上。在其上面’形成阻劑（resist)圖案 (pat tern )，使用敗（F )系氣體（gas )等而進行乾式姓 刻（dry etching)。藉此而在鈍化（passivation)膜 29 中’形成接觸孔（contacthole) 31。接著，由基板22之 鲁上’來除去光阻劑（photoresist)，洗淨除去光阻劑 (photoresist)之基板 22。 接著’形成像素電極。首先’在基板22之上，藉著減 鍍（sputtering)而成膜由像素電極之材料所構成之透明 導電膜（例如ΙΤ0膜）。此時’也在接觸孔（contact hole) 31之内側，成膜ΙΤ0膜》連接j：及極（dra jn )電極層2§和 no膜。接著’形成阻劑（resist)圖案（pattern)，進 行濕式敍刻（etching)。藉此而使得1了〇膜，形成為要求 _之圖案（pattern)形狀。由基板22之上’來除去光阻劑 (photoresist)，洗淨除去光阻劑（ph〇t〇resist)之基 板22。經過以上之製程而完成液晶顯示裝置用TFT陣列 (array )基板。 參考圖2，就TFT21製造之阻劑（resjst)之除去及 洗淨方法而詳細地進行說明。圖2係本實施形態之基板處 理裝置之構成圖。圖2係具有裝載器（1〇ader) n、入口 輸送器（conveyer) 12、剝離處理單元（unit) A13、剝離 處理單/〇( unit)B14、洗淨單元（unit)15、乾燥單元（2185-8619-PF 10 1-342071 Row ion doping (i on dope), forming an n+ amorphous ruthenium film, forming an ohmic contact layer 26. On the laminate, a resist pattern is formed to perform dry etching. The η + amorphous ruthenium film, the amorphous ruthenium film, and the tantalum nitride (SiN) film areetched to form a desired pattern shape. Next, the photoresist is removed from the upper side of the substrate 22, and the substrate 22 from which the photoresist is removed is washed. Through the above process, a semiconductor layer 25, a gate insulating layer 24, and an ohmic contact layer 26 are formed on the substrate 22. Next, a source electrode layer 27 and a drain electrode layer 28 are formed. First, a metal film of a source electrode layer 27 and a drain electrode layer 28 is formed by a sputtering method. For example, a Mo—Al—Mo laminated film is formed on the substrate. After a resist pattern is formed on the laminated film, a channel (channe 1) is engraved by dry etching. Thereby, the Mo—Al—Mo laminated film is formed into a desired pattern shape. The spurce electrode layer 27 and the drain electrode layer 28 are formed to be used as a source wiring. Wiring. Next, the photoresist is removed from the upper surface of the substrate 22, and the substrate 22 from which the photoresist is removed is washed. However, the specific cleaning method will be described in detail later. At this stage, a process for forming a nitride on the surface of the wiring including Mo is performed. Next, a passivation film 29 is formed from above the source electrode layer 27 and the drain electrode layer 28. A 2185-8619-PF 11 1342071 passivation film 29 is formed to cover the source electrode layer 27 and the drain electrode layer 28. First, a nitridation (siN) film which is a material of a passivation film 29 is formed on the substrate 22 by, for example, the cvd method. A resist pattern (pat tern ) is formed thereon, and dry etching is performed using a gas (gas) or the like. Thereby, a contact hole 31 is formed in the passivation film 29. Next, the photoresist is removed from the upper surface of the substrate 22, and the substrate 22 on which the photoresist is removed is washed. Next, a pixel electrode is formed. First, a transparent conductive film (e.g., ΙΤ0 film) composed of a material of a pixel electrode is formed on the substrate 22 by sputtering. At this time, 'on the inside of the contact hole 31, the film formation 》0 film 》 connects the j: and rad jn electrode layer 2 § and no film. Next, a resist pattern is formed to perform wet etching. Thereby, the ruthenium film is formed to have a pattern shape of _. The photoresist is removed from the upper side of the substrate 22, and the substrate 22 from which the photoresist is removed is washed. Through the above process, a TFT array substrate for a liquid crystal display device is completed. The removal and cleaning method of the resist (TFT) manufactured by the TFT 21 will be described in detail with reference to Fig. 2 . Fig. 2 is a view showing the configuration of a substrate processing apparatus of the present embodiment. Figure 2 is a loader (1〇ader) n, an inlet conveyor 12, a stripping unit (unit) A13, a stripping unit/unit B14, a unit 15, and a drying unit (
2185-8619-PF 12 1342071 16、出口 輸送器（conveyer) 17、卸料器（unl〇ader ) 18 和大氣壓電漿（Plasma)處理部19之基板處理裝置^在 本實施形態’即使是在TFT製造製程中，也在形成包含Mo 之配線層之後，以進行於露出包含之層之狀態下之阻劑 (resist)之除去及洗淨製程，來作為對象。 首先’設置將在裝載器（l〇ader ) 11形成TFT21之基 板（在以下、稱為TFT基板）予以收納之匣盒（cassette)。 TFT基板係藉由自動裝置（r〇b〇t)等之移動裝置而進行抽 取，移載至入口輸送器（c〇nveyer ) j 2。然後，藉由剝離 處理單元（unit) A13和剝離處理單元（unit) B14而將 TFT基板次潰於剝離液。藉此而除去殘留於TFT基板上之 阻劑（resist)殘逢。接著，藉由利用洗淨單元（unit) 15而對於TFT基板進行純水洗淨，來流洗剝離液。接著， 在藉由乾燥單元（unit)16而乾燥7叮基板之後，搬送汀丁 基板至出口輸送器（conveyer) 17為止。此時，在通過出 口輸送器（C〇nveyer) 17之m基板，藉由大氣壓電漿 (PU觀）處理部19而實施大氣麼電漿（piasma)處理。 進行大氣壓電漿（plasma)處理之TFT基板係藉由自動裝 置（robot)等之移動裝置而收納在卸料器（unloader)广8 之ϋ盒（cassette)。這些—連串之洗淨動作係、能 地進行，藉由並未圖示之控射 助 固丁々衩制益（contr〇Uer)而進 制。當然，也可以藉由手動而進行一連串之作業。 二 在剥離處理單元（unit) A13和剝離處理單元 B14，將殘留於TFT基板上之< . 七） 丞板上之阻劑（resist)殘渣，浸漬在2185-8619-PF 12 1342071 16. Outlet conveyor 17. Unloader (unl〇ader) 18 and substrate processing apparatus of atmospheric piezoelectric (Plasma) processing unit 19 In this embodiment, even in TFT In the manufacturing process, after the wiring layer containing Mo is formed, a resist removal and a cleaning process in a state in which the layer is exposed are exposed. First, a cassette in which a substrate (hereinafter referred to as a TFT substrate) of the TFT 21 is formed in a loader 11 is placed. The TFT substrate is extracted by a moving device such as an automatic device (r〇b〇t), and transferred to an entrance conveyor j 2 . Then, the TFT substrate is broken by the peeling liquid by the peeling unit A13 and the peeling unit B14. Thereby, the residue remaining on the TFT substrate is removed. Next, the TFT substrate is washed with pure water by a cleaning unit 15, and the stripping liquid is flow-washed. Next, after drying the 7-inch substrate by the drying unit 16, the Tingding substrate is transferred to the exit conveyor 17. At this time, the atmosphere is subjected to a piasma treatment by the atmospheric piezoelectric slurry (PU) processing unit 19 through the substrate of the outlet conveyor 17 m. The TFT substrate subjected to atmospheric plasma plasma treatment is housed in a cassette of unloader 8 by a moving device such as a robot. These-series of washing operations are carried out in a manner that can be carried out by means of a control (not shown) to help the contr〇Uer. Of course, a series of operations can also be performed manually. 2. In the peeling treatment unit (unit) A13 and the peeling treatment unit B14, the residue residue on the <.7) ruthenium remaining on the TFT substrate is immersed in
2185-86I9^PF 13 工342071 阻劑（resist)剝離液而除去。阻劑（resis〇剝離液係 並無惡化配線材料或耐化學性低之材料，在短時間内，除 去殘留於微細部位之阻劑（resist)殘渣。阻劑（resist) .剝離液係具有藉由丙酮和乙醇等之所造成之有機洗淨液、 或者是藉由過氧化氫水或氨系溶劑等之所造成之酸鹼 (alkali)洗淨液等之許多種類。在各種阻劑（resist)， 由於種類而具有指定之剝離液，因此，能夠設置複數個之 剝離處理單元（unit)，分別使用在每一個阻劑（resist)。 此外，也可以注入相同於複數個之剝離處理單元（⑽丨士） 之剝離液而分割成為粗洗淨和精洗淨。2185-86I9^PF 13 342071 Resist stripping solution and removed. The resist (resis〇 stripping system does not deteriorate the wiring material or the material with low chemical resistance, and removes the residue residue remaining in the fine portion in a short time. Resist. An organic cleaning solution caused by acetone or ethanol, or an acid-base cleaning solution caused by hydrogen peroxide water or an ammonia-based solvent, etc., in various resists (resist) Since there is a specified stripping liquid depending on the type, a plurality of stripping processing units can be provided and used for each resist. Alternatively, the same number of stripping units can be injected ( (10) Gentleman's peeling liquid is divided into coarse washing and fine washing.
在洗淨單元（uni t ) 15，藉由洗淨液而除去附著於TFT 基板表面之阻劑（resist)剝離液或微粒（particle)等 之異物。在本實施形態，作為洗淨液係使用純水。純水係 儘可能地除去不純物，也稱為離子（i〇n)交換水或脫離子 (ion)水。在一般之半導體製造製程，使用電傳導率下降 至lxl〇—6S/cm程度以下為止之水。由於電路之積體度而使 用電傳導率下降至6xl0、/cm以下為止之更加高純度之 純水。 在大氣壓電漿（plasma)處理部19，藉由特殊之方法， 在大氣壓下，產生通常僅發生於真空下之輝光放 電狀態。在大氣壓電漿（plasma)處理部19，使用藉此而 產生之電漿（Plasma)活性種，進行有機物除去等之洗淨。 在大氣壓電漿（Plasma)處理，除去表面層，形成改變化 學组成及構造之新表面層。大氣壓電漿（plasma)處理係In the cleaning unit (uni t) 15, a foreign matter such as a resist peeling liquid or particles adhering to the surface of the TFT substrate is removed by the cleaning liquid. In the present embodiment, pure water is used as the washing liquid. Pure water system removes impurities as much as possible, also known as ion (i〇n) exchange water or deionized water. In a general semiconductor manufacturing process, water having a conductivity lower than that of lxl 〇 6S/cm or less is used. Due to the integrated degree of the circuit, pure water having a higher purity of electrical conductivity down to 6x10 or less is used. In the atmospheric plasma processing unit 19, a glow discharge state which normally occurs only under vacuum is generated by a special method under atmospheric pressure. The plasma piezoelectric treatment unit 19 uses the plasma active species generated thereby to wash the organic matter and the like. In the atmospheric piezoelectric plasma treatment, the surface layer is removed to form a new surface layer that changes the chemical composition and structure. Atmospheric piezoelectric plasma processing system
2185,8619-PF 14 1342071 可以利用在表面形成凹凸形狀之粗面效果或表面處理等之 '舌丨生效果而提高接著性。此外，也可以代表在對於CVD法 等之適用而應用於成膜。 在圖3，顯示大氣壓電漿（pi asma)處理部a之構造 例。大氣壓電漿（p 1 asma )處理部！ 9係例如在導入氣體 (gas )之處理室（chamber ) 34之内，具有電源施加用電 極33和接地電極35等，就大氣壓電漿（plasma)處理部 19之構造而言，也可以使用能夠由於當前業者之所考慮之 其他構造。將氧或氮等之電漿（plasma)生成用之混合氣 體（gas )’導入至處理室（chamber ) 34，在氣體（gas )， 施加電壓，產生電漿（plasma)37。藉由產生之電漿（plasma) 37撞擊至搬送大氣壓電漿（plasma)處理部19之正下方 之TFT基板36，而除去TFT基板36上之有機物等。在電 黎( Plasma)生成用之氣體（gas)，除了氡或氮以外，也 可以使用氬、氦及空氣等。在本實施形態，使用氮及氧。 大氣壓電漿（plasma )處理部1 9係配置在出口輸送器 (conveyer) 17，但是，在阻劑（resist)除去後之基板 搬送通路，陣列（array )係也可以配置於任何位置。 在本實施形態，使用氮流量400L/ m i η、氧流量1. 6 9 xlOla · m3/sec ( 100SCCM)之混合氣體（gas)，基板和 電極間之距離成為3mm，基板搬送速度成為lm/min，來作 為藉由大氣壓電漿（plasma)處理部19所造成之大氣壓電 漿（p 1 asma )處理之條件之某一例子。藉由利用前述之處 理條件，來進行大氣壓電漿（Plasma )處理，而除去形成 2185-8619-PF 15 1342071 於源極（source)電極層27和汲極（drain)電極層28之 表面之Mo氧化物，同時，在源極（s〇urce)電極層”和 汲極（drain)電極層28之表面，生成Mo氮化物（在以下、 稱為MoNx層）❶此外，前述處理條件之值係在基板之搬送 方向和垂直方向之基板尺寸成為4〇〇mm之狀態下之值，必 須在企圖增大基板尺寸之狀態下，也增長電極之長度。此 外，必須按照這個而也適當地增加氮流量或氧流量。 含有Mo之源極（source)電極層27和汲極（drain) 電極層28係由圖案（pattern)開始剝離阻劑（resist) 之即刻後’馬上藉由大氣中之氧而在表面，形成氡化 物。在此’藉著進行由於大氣壓電漿（plasma)處理部19 所造成之大氣壓電漿（plasma)處理，而除去形成於表層 之Mo氧化物’形成新MoNx層。圖4係擴大圖1之一部分 之剖面圖。正如圖4所示，藉由在含有Mo之源極（source ) 電極層27和汲極（drain)電極層28之表層，實施大氣壓 電漿（plasma)處理，而生成MoNx層32。因此，在大氣 壓電漿（pl asma )處理後，即使是在大氣中，放置TFT基 板，也在Mo之表面，形成MoNx層，因此，抑制M〇氧化物 之形成。在此重要者係為了形成MoNx層，因此，必須在大 氣壓電漿（plasma )處理，至少使用氮》 例如在形成源極（source)電極層27和没極（drain ) 電極層28而剝離阻劑（resi st )之後，即使是在實施大氣 壓電漿（plasma )處理之狀態下，藉由下一個之純化 (passivation)膜之成膜前之洗淨而實施純水洗淨，也在 2185-8619-PF 16 1-342071 樣也可以實施在鈍化（passivati〇n：^ 29之阻劑（resist) 到離製程後。此外’也可以在其後面之j τ〇膜等之成膜前 之洗淨製程之最後，實施大氣壓電漿（plasma)處理。 可以藉由以上之構造，而即使是在配線材料來使用含 有Mo之金屬之狀態下，也能夠除去析出於之如氧 化物，同時，可以藉由在M〇之表φ，形成Μ〇Νχ層，而抑 制Mo氧化物之形成。結果，在洗淨製程之所溶出之μ〇氧 化物係並無再附著於TFT21，可以得到電特性良好之 TFT21 。 此外，可以藉由以上之構造，而在阻劑（“以討）之 剝離及洗淨製程之-連串之作業中，實施大氣遷電聚 (…鐵）處理。因此，並無增加製造製程數，能夠消除 Mo氧化物之除去或Mo氧化物對於洗淨液之溶出。 此外’可以藉由抑制M。氧化物對於洗淨液之溶出而 減少洗淨液之交換頻率，削減洗淨液之材料成本（c〇st) 以及由於交換所造成之人事費。 此外’本發明係並無限定在前述之各個實施形態。可 、在本發月之範圍，在藉由當前業者之所能夠容易考廣到 陣列（打1"50之内容，改變、追加和變換前述實施形態之 各個要素W如别述之各個實施形態係、說明在源極 (扣urce)電極層和汲極（drain)電極層使用m〇材料之 狀態，但疋，即使是在其他之配線使用Mo材料之狀態下， 也可以疋相同的。此外，源極（)電極層和沒極 "η110電極層係就m-Mo層積膜之狀態而進行說2185,8619-PF 14 1342071 It is possible to improve the adhesion by utilizing the rough surface effect of the uneven shape on the surface or the tongue-and-groove effect such as surface treatment. Further, it can also be applied to film formation in the application to the CVD method or the like. Fig. 3 shows an example of the structure of the atmospheric pi asma processing unit a. Atmospheric piezoelectric slurry (p 1 asma) processing unit! For example, the power supply electrode 33 and the ground electrode 35 may be provided in a chamber 34 for introducing gas (gas), and the structure of the atmospheric plasma processing unit 19 may be used. Other constructs considered by the current industry. A mixed gas (gas) for plasma generation such as oxygen or nitrogen is introduced into a chamber 34, and a voltage is applied to the gas to generate a plasma 37. The generated plasma 63 hits the TFT substrate 36 directly below the atmospheric plasma processing unit 19, and the organic matter or the like on the TFT substrate 36 is removed. In addition to helium or nitrogen, argon, helium, and air may be used for the gas for plasma generation. In the present embodiment, nitrogen and oxygen are used. The atmospheric piezoelectric plasma processing unit is disposed in the outlet conveyor 17, but the array transfer path after the resist is removed, and the array may be disposed at any position. In the present embodiment, a gas mixture having a nitrogen flow rate of 400 L/mi η and an oxygen flow rate of 1.69 9 x 10 Å · m 3 /sec (100 SCCM) is used, the distance between the substrate and the electrode is 3 mm, and the substrate transport speed is lm/min. This is an example of the conditions of the atmospheric piezoelectric slurry (p1 asma) treatment by the atmospheric plasma plasma processing unit 19. The atmospheric piezoelectric slurry treatment is performed by using the aforementioned processing conditions, and Mo is formed on the surface of the source electrode layer 27 and the drain electrode layer 28 by forming 2185-8619-PF 15 1342071. At the same time, a Mo nitride (hereinafter referred to as a MoNx layer) is formed on the surface of the source electrode layer and the drain electrode layer 28, and the value of the aforementioned processing conditions is In the state in which the substrate size in the transport direction and the vertical direction of the substrate is 4 mm, it is necessary to increase the length of the electrode in an attempt to increase the size of the substrate. Further, it is necessary to appropriately increase nitrogen according to this. Flow or oxygen flow. The source electrode layer 27 and the drain electrode layer 28 containing Mo are immediately after the peeling of the resist from the pattern, immediately by the oxygen in the atmosphere. On the surface, a telluride is formed. Here, by performing atmospheric plasma plasma treatment by the atmospheric plasma treatment portion 19, the Mo oxide formed in the surface layer is removed to form a new MoNx layer. 4 series expansion A cross-sectional view of a portion of Fig. 1. As shown in Fig. 4, atmospheric plasma plasma treatment is performed by coating the surface layer of the source electrode layer 27 and the drain electrode layer 28 containing Mo. The MoNx layer 32 is formed. Therefore, after the pul asma treatment in the atmosphere, even if the TFT substrate is placed in the atmosphere, the MoNx layer is formed on the surface of Mo, thereby suppressing the formation of the M 〇 oxide. In order to form the MoNx layer, it is necessary to treat the plasma in the atmosphere, at least using nitrogen. For example, in forming the source electrode layer 27 and the drain electrode layer 28, the resist is peeled off (resi After st), even in the state where the atmospheric plasma plasma treatment is carried out, pure water washing is carried out by washing the film before the film formation of the next passivation film, also at 2185-8619-PF. 16 1-342071 The sample can also be applied to passivation (passivati〇n: ^ 29 resist to the process after the process. In addition, it can also be used in the cleaning process before the film formation of the j τ film Finally, atmospheric plasma plasma treatment is implemented. According to the above configuration, even in the state in which the metal containing Mo is used as the wiring material, it is possible to remove the precipitated oxide, and at the same time, the ruthenium layer can be formed by the φ of the M ,. On the other hand, the formation of the Mo oxide is suppressed. As a result, the μ〇 oxide which is eluted in the cleaning process does not adhere to the TFT 21, and the TFT 21 having excellent electrical characteristics can be obtained. In addition, by the above configuration, in the series of operations of the stripping and cleaning process of the resist ("discussion"), the atmospheric migration (...iron) treatment is performed. Therefore, the manufacturing process is not increased. The number can eliminate the removal of Mo oxide or the elution of Mo oxide to the cleaning liquid. In addition, it can reduce the exchange frequency of the cleaning liquid by reducing the elution of the cleaning liquid by the oxide, and reduce the cleaning liquid. The material cost (c〇st) and the personnel expenses due to the exchange. In addition, the present invention is not limited to the above-described embodiments. However, in the scope of this month, it is easy to test by the current industry. Widely arranging the contents of the array (changing, adding, and transforming the various elements of the foregoing embodiments, as described in the respective embodiments, the description of the source electrode layer and the drain electrode layer The state of the m〇 material is used, but 疋, even in the state where other materials are used in the Mo material, the same can be used. In addition, the source () electrode layer and the immersion "η110 electrode layer are m-Mo The state of the laminated film Said line
2185-8619-PF 18 1342071 明，但是，即使是Mo之單層膜或者是包含M〇〇他之膜 構造，也可以達到相同之效果。 此外，並無限定在液晶顯示裝置之TFT陣列（παν ) 基板’關於使用M〇氣化物 礼化初之基板製造，也可以是相同的。 此外’以液晶顯示歩·罟夕tpt u γ 、 屐置之TFT陣列（array )基板之製造製 程’作為例子，·^ gg | α α 説明本發明之理想之實施形態，但是，也 可乂適用於其他之顯示裝置或者是適用於源極（source ) 電㈣和:及極（drain)電極層以外之配線。也就是說並2185-8619-PF 18 1342071 However, even a single film of Mo or a film structure containing M〇〇 can achieve the same effect. Further, the TFT array (παν) substrate ー of the liquid crystal display device is not limited to the case of the substrate manufactured using M 〇 vaporization, and may be the same. In addition, 'the manufacturing process of the TFT array substrate of liquid crystal display t·罟 t tpt u γ and 屐 , 作为 作为 作为 作为 作为 作为 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想 理想For other display devices or for wiring other than the source (four) and: drain electrodes. That is to say
無限疋在液晶顯示裝晋，可Π、态田Μ曰士 & A 置了 乂適用於具有包含Mo之層之美 板之一般製造。 圖式簡單說明】 圖1係本發明之液晶顯示用薄膜電晶體之剖面圖。 圖2係顯示本發明之基板處理裝置之構成圖。 圖 圖3係本發明之大氣壓電漿（Plasma)處理部之構成 圖4係顯示本發明之M〇層之狀態之剖面圖。 圖5係顯不析出Mo氧化物之液晶顯示裝置用薄膜電曰 體之狀態之剖面圖。 联電日曰 圖6係除去藉由專利文獻！所造成之⑽氧化 之示意圖。 万表 主要元件符號說明】Unlimited 疋 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a thin film transistor for liquid crystal display of the present invention. Fig. 2 is a view showing the configuration of a substrate processing apparatus of the present invention. Fig. 3 is a view showing the configuration of an atmospheric piezoelectric slurry processing portion of the present invention. Fig. 4 is a cross-sectional view showing the state of the M 〇 layer of the present invention. Fig. 5 is a cross-sectional view showing a state in which a thin film electrode for a liquid crystal display device in which Mo oxide is not deposited. UMC Daily Chart Figure 6 is removed by the patent document! A schematic diagram of the resulting (10) oxidation. 10,000 meters main component symbol description]
1〜基板處理裝置； 2185-8619-PF 1-342071 11〜裝載器（loader ); 12〜入口輸送器（conveyer); 13〜剝離處理單元（unit) A; 14〜剝離處理單元（unit) B; 15〜洗淨單元（unit); 16〜乾燥單元（unit); 17〜出口輸送器（conveyer); 18〜卸料器（unloader); 19〜大氣壓電漿（plasma)處理部； 21〜TFT ; 22〜基板； 23〜閘極（gate)電極層； 24〜閘極（ga t e )絕緣層； 25〜半導體層； 26〜歐姆接點（ohmic contact)層； 27〜源極（source)電極層； 28〜汲極（drain)電極層； 29〜鈍化（passivation)膜； 31 〜接觸孔（contact hole); 32〜MoNx 層； 3 3〜電源施加用電極； 34〜處理室（chamber); 3 5〜接地電極； 36〜TFT基板； 201~substrate processing device; 2185-8619-PF 1-342071 11~loader; 12~input conveyor; 13~peeling unit (unit) A; 14~ stripping unit (unit) B 15~cleaning unit (unit); 16~drying unit (unit); 17~outlet conveyor (conveyer); 18~unloader (unloader); 19~atmospheric piezoelectric plasma (plasma) processing unit; 21~TFT 22~substrate; 23~gate electrode layer; 24~gate (ga te) insulating layer; 25~semiconductor layer; 26~ohmic contact layer; 27~source electrode Layer; 28~drain electrode layer; 29~passivation film; 31~contact hole; 32~MoNx layer; 3 3~power application electrode; 34~processing chamber; 3 5~ground electrode; 36~TFT substrate; 20
2185-8619-PF 1-342071 37〜電漿（piasma ); 121 〜TFT ; 122〜基板； 123〜閘極（gate)電極層； 124〜閘極（gate)絕緣層； 125〜半導體層； 126〜歐姆接點（ohmic contact)層； 127〜源極（source)電極層； 128〜汲極（drain)電極層； 129〜鈍化（passivation)膜； 130〜Mo氧化物； 131〜包含Mo之配線。2185-8619-PF 1-342071 37~plasma (piasma); 121~TFT; 122~substrate; 123~gate electrode layer; 124~gate insulating layer; 125~semiconductor layer; 126 ~ ohmic contact layer; 127 ~ source electrode layer; 128 ~ drain electrode layer; 129 ~ passivation film; 130 ~ Mo oxide; 131 ~ containing Mo wiring .
21twenty one
2185-8619-PF2185-8619-PF
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| CN106711231A (en) * | 2017-01-13 | 2017-05-24 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method of thin film transistor, display substrate and preparation method of display substrate |
| WO2018181296A1 (en) * | 2017-03-29 | 2018-10-04 | シャープ株式会社 | Method for manufacturing channel-etch-type thin film transistor |
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| JP3081954B2 (en) * | 1995-06-13 | 2000-08-28 | 日本プレシジョン・サーキッツ株式会社 | Method for manufacturing MOS transistor |
| US5935648A (en) | 1997-03-28 | 1999-08-10 | The United States Of America As Represented By The Secretary Of The Air Force | High surface area molybdenum nitride electrodes |
| US6291282B1 (en) * | 1999-02-26 | 2001-09-18 | Texas Instruments Incorporated | Method of forming dual metal gate structures or CMOS devices |
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