TWI339553B - Two-layer printed circuit board and method that make impedance controlled - Google Patents
Two-layer printed circuit board and method that make impedance controlled Download PDFInfo
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〔丨99年09月24日修正替换頁 六、發明έ兄明: . 【發明所屬之技術領域】 [〇〇〇1] 本發明涉及一種印刷電路板(Pr inted Circui t Board ,以下簡稱PCB),尤指一種可於高速信號佈線中實現阻 抗控制之兩層印刷電路板及方法。 【先前技術】 [0002] 隨著積體電路輸出開關速度提高以及PCB之佈線密度增加 ’信號完整性已經成爲高速數位p C B設計必須關心之問題 。元器件和PCB之參數、元器件在PCB上之佈局' 高速信 號之佈線等因素,都會引起信號完整性問題,導致系統 工作不穩定,甚至完全不f胃:。設計過程 充分考慮到信號完整性之因|,^%#控制措施 已經成爲當今PCB設計業界之熱門課題^ ‘對於PCB之脅 輸線來講’㈣㈣完整性最重要係阻抗匹配。傳輸線 之特徵阻抗與負載阻抗不匹配時,信_達接收端後有 y部分能量將沿著傳輸線反_去,使信號波形發生崎 變’甚至出現信號之過沖和下沖。信號如果在傳輸線上 來回反射,就會産生往返振蕩。卿傳輸線之阻抗之β 素=鋼線之寬度、鋼線之厚度、介質之介電常數 走:等質之=焊盤之厚度、地線之路徑及走線周邊之 傳輪線之阻抗之計算方法可參照相應 式,如.[丨 09 09 09 09 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 、 六 、 、 、 、 、 、 、 In particular, a two-layer printed circuit board and method for achieving impedance control in high-speed signal wiring. [Prior Art] [0002] As the output switching speed of integrated circuits increases and the wiring density of PCBs increases, 'signal integrity has become a concern for high-speed digital p C B design. The parameters of components and PCBs, the layout of components on the PCB, and the wiring of high-speed signals can cause signal integrity problems, resulting in unstable system operation or even no stomach. The design process takes full account of the signal integrity |, ^% # control measures has become a hot topic in today's PCB design industry ^ ‘for the PCB threat line.' (4) (four) integrity is the most important impedance matching. When the characteristic impedance of the transmission line does not match the load impedance, the y part of the energy after the signal is received will be reversed along the transmission line, causing the signal waveform to become erratic or even overshoot and undershoot the signal. If the signal is reflected back and forth on the transmission line, a round-trip oscillation will occur. The beta of the impedance of the transmission line = the width of the steel wire, the thickness of the steel wire, and the dielectric constant of the medium: the thickness of the pad = the thickness of the pad, the path of the ground wire, and the impedance of the transmission line around the trace The method can refer to the corresponding formula, such as.
[0003] 其中 ,之爲傳輸線之特徵阻抗’ 0 £爲介質之介電常數 r’妒爲傳輸線之寬度’ _ί爲傳輸線之厚度, 爲介質 093131362 表單編號Α0101 $ 4頁/共15頁 0993344619-0 1339.553 099年09月24日梭1 正替换頁[0003] where is the characteristic impedance of the transmission line '0 £ is the dielectric constant r' of the medium is the width of the transmission line ' _ ί is the thickness of the transmission line, is the medium 093131362 Form number Α 0101 $ 4 pages / a total of 15 pages 0993344619-0 1339.553 September 24, 2009, shuttle 1 replacement page
之厚度。習知技術中,四層以上之PCB借由傳輸線與參考 地平面構成之傳輸線結構達成要求之傳輸線阻抗,不同 之傳輸線類型要求有不同之傳輸線標準阻抗值。業界標 準之PCB厚度在62mil(千分之一英寸,約0.0254毫米) 左右,如第一圖所示之四層PCB結構,包括複數個傳輸線 100,介質層110、130及接地層120,其能夠實現阻抗匹 配之傳輸線標準阻抗值爲60歐姆。介質層110之介電常數 爲4,傳輸線100之寬度爲5 mil,傳輸線100之厚度爲 2. 1 mil,介質層110之厚度爲4. 4 mil,根據經驗公式 計算得出傳輸線之特徵阻抗爲54. 7歐姆,基本符合阻抗 匹配之要求。另外,也可利仿:真:軟释乘对;算傳輸線之 阻抗,把含有傳輸線、介質鼻及接也海之傳%線結構之 二維截面輸入仿真軟體,仿‘真軟七會分知^輸線與接地 層産生之電磁場,計算出傳輸線之阻抗。 [0004] 在I/O卡中,兩層PCB之使用不必在介質層中鋪上接地層 I ·· · _ ,可以大幅度降低單位面積之成本。然而,習知兩層PCB # 結構沒有標準之佈線規範,一般係於PCB沒有用上之空白 X · • · · 區域敷上大面積銅層與地相連作爲地線使用,這樣在高 速信號佈線中難以實現阻抗匹配。如第二圖所示之兩層 PCB結構,包括複數個傳輸線150、一接地層160和介質 層170。介質層之厚度56 mil,根據上述經驗公式計算 得出傳輸線150之特徵阻抗爲150歐姆,顯然不符合阻抗 匹配之要求,若要使傳輸線150之特徵阻抗等於60歐姆, 根據上述經驗公式,γ爲傳輸線150之寬度需達到 82mil,這於PCB中係不合理之設計。而一接地層160也 093131362 表單編號 A0101 第 5 頁/共 15 頁 0993344619-0 1339553 099年09月24日修正替换苜 [0005] [0006]The thickness. In the prior art, four or more layers of PCBs achieve the required transmission line impedance by the transmission line structure formed by the transmission line and the reference ground plane, and different transmission line types require different transmission line standard impedance values. The industry standard PCB thickness is about 62 mils (one thousandth of an inch, about 0.0254 mm), as shown in the first four-layer PCB structure, including a plurality of transmission lines 100, dielectric layers 110, 130 and ground layer 120, which can The standard impedance of the transmission line that achieves impedance matching is 60 ohms. The dielectric layer 110 has a dielectric constant of 4, the transmission line 100 has a width of 5 mils, the transmission line 100 has a thickness of 2.1 mil, and the dielectric layer 110 has a thickness of 4.4 mil. The characteristic impedance of the transmission line is calculated according to an empirical formula. 54. 7 ohms, basically meet the requirements of impedance matching. In addition, it can also be imitation: true: soft release multiply pair; calculate the impedance of the transmission line, input the two-dimensional cross-section of the transmission line, the medium nose and the transmission of the % line structure into the simulation software, imitation 'true soft seven will know ^ The electromagnetic field generated by the transmission line and the ground plane calculates the impedance of the transmission line. [0004] In an I/O card, the use of a two-layer PCB does not require a ground plane I··· _ in the dielectric layer, which can greatly reduce the cost per unit area. However, it is known that the two-layer PCB # structure does not have a standard wiring specification, and is generally used in the blank of the PCB. X · • · · A large area of copper is applied to the ground to be used as a ground line, so that it is used in high-speed signal wiring. It is difficult to achieve impedance matching. The two-layer PCB structure as shown in the second figure includes a plurality of transmission lines 150, a ground layer 160, and a dielectric layer 170. The thickness of the dielectric layer is 56 mil. According to the above empirical formula, the characteristic impedance of the transmission line 150 is 150 ohms, which obviously does not meet the requirements of impedance matching. If the characteristic impedance of the transmission line 150 is equal to 60 ohms, according to the above empirical formula, γ is The width of the transmission line 150 needs to be 82 mils, which is an unreasonable design in the PCB. And a ground layer 160 is also 093131362 Form No. A0101 Page 5 of 15 0993344619-0 1339553 Correction of replacement on September 24, 099 [0005] [0006]
沒有考慮到複數個傳輸線150乏阻疼控制要求,使用仿真 軟體時,複數個傳輸線150與一接地層丨60構成之二維戴 面無法去控制每一傳輸線15 〇之特徵阻抗值。 【發明内容】 本發明之目的在於提供一種可實現阻抗控制之兩層印刷 電路板及其方法。 爲實現本發明之目的,本發明之兩層印刷電路板包括一 介質層和配置於該介質層上之複數個高速信號傳輸線’ 該介質層上還配置有與每一高速信號傳輸線相鄰之接地 層。該高速信號傳輸線以及高速信號傳輸線與接地層相 對位置之一組參數值對應該一個特徵 阻抗值,該 高速信號傳輸差分信號 傳輪線。本發明之兩層印刷電路板实现阻抗控制之方法 係於該兩層印刷電路板之介質層上配置與每一高速信號 傳輸線相鄰之接地層,再將該兩層印刷電路板之剖面二 維圖形輸入至一仿真軟體,由仿真軟體計算出該高速信 號傳輸線之特徵阻抗值與其標準阻抗值比較後,若該特The plurality of transmission lines 150 are not considered to have a pain resistance control requirement. When the simulation software is used, the two-dimensional wear formed by the plurality of transmission lines 150 and a ground layer 丨60 cannot control the characteristic impedance value of each transmission line 15 。. SUMMARY OF THE INVENTION It is an object of the present invention to provide a two-layer printed circuit board and method for achieving impedance control. For the purpose of the present invention, the two-layer printed circuit board of the present invention comprises a dielectric layer and a plurality of high-speed signal transmission lines disposed on the dielectric layer. The dielectric layer is further disposed adjacent to each high-speed signal transmission line. Stratum. The high-speed signal transmission line and the high-speed signal transmission line and the ground layer are in a pair of parameter values corresponding to a characteristic impedance value, and the high-speed signal transmits the differential signal transmission line. The method for achieving impedance control of the two-layer printed circuit board of the present invention is to arrange a ground layer adjacent to each high-speed signal transmission line on the dielectric layer of the two-layer printed circuit board, and then to form a two-dimensional cross section of the two-layer printed circuit board. The graphic is input to a simulation software, and the simulation software calculates that the characteristic impedance value of the high-speed signal transmission line is compared with the standard impedance value, and if the
徵阻抗值與標準阻抗值不相等或不接近,則調整高速信 號傳輸線以及高速信號傳輸線與接地層相對位置之參數 值,再重新將上述剖面二維圖形輸入 '重新計算,直到 所得之特徵阻抗值與標準阻抗值相等或接近。 [0007] 栌!:之功政在於該兩層印刷電路板可以通過仿真軟 二=信號傳輪線之特徵阻抗值,從而實現高速 傳輸線與其他負叙阻抗匹配。 【實施方式】 093131362 表單塢號Α0ΠΗ 第6頁/共15頁 0993344619-0 [0008]If the impedance value is not equal to or close to the standard impedance value, adjust the parameter value of the high-speed signal transmission line and the relative position of the high-speed signal transmission line and the ground layer, and then re-calculate the two-dimensional graph of the above-mentioned section until the obtained characteristic impedance value Equal or close to the standard impedance value. [0007] Hey! The trick is that the two-layer printed circuit board can simulate the soft second transmission line with the characteristic impedance value of the signal transmission line to achieve high-speed transmission line matching with other negative impedances. [Embodiment] 093131362 Form Dock Number Α0ΠΗ Page 6 of 15 0993344619-0 [0008]
[0008] Uy9年〇9月24日g正J I U外年〇9月:[0008] Uy9 years old September 24th g Zheng J I U years old September:
本發明可實現阻抗控制之兩層印刷電路板及方法之第 實施例’ π參閱n兩層印刷電路板3包括複數個高 速信號傳輸線(本實施例爲單端傳輸線10)、—介質層 20、複數個接地層3(3和㈣個低迷錢線4〇。每—單端 傳輸線1G之兩側各設置—接地層30,接地層3G與單端傳 輸線ίο並列佈置於介質層2()上,接地_之厚度t等於單 端傳輸線1G之厚度t,接地層3G之長度科料傳輸線10 之長度。單端傳輸線10之寬度爲,,每一接地層30到單 端傳輪線1G之距離&。要實現單端傳輪線1〇 之阻抗控制 ’首先將如第三圖所示之剖面二維圓形輸入至一仿真軟 體’如2D Extract〇r ,寧會分寧剖面二維圖 形構成元件之電磁場’計算特徵阻抗The first embodiment of the present invention can realize two-layer printed circuit board and method for impedance control. π Refer to n two-layer printed circuit board 3 including a plurality of high-speed signal transmission lines (in this embodiment, single-ended transmission line 10), a dielectric layer 20, a plurality of grounding layers 3 (3 and (4) low-key lines 4 〇. Each side of the single-ended transmission line 1G is disposed - the ground layer 30, the ground layer 3G and the single-ended transmission line ίο are arranged side by side on the dielectric layer 2 (), The thickness t of the grounding_ is equal to the thickness t of the single-ended transmission line 1G, the length of the grounding layer 3G, the length of the material transmission line 10. The width of the single-ended transmission line 10 is, the distance from each grounding layer 30 to the single-ended transmission line 1G & To achieve the impedance control of the single-ended transmission line 1 'first input the two-dimensional circular shape as shown in the third figure to a simulation software' such as 2D Extract〇r, Ning will divide the two-dimensional graphic components of the section Electromagnetic field 'calculates characteristic impedance
值’若計算得來之特徵阻抗t不f.合兩.¾刷電路板3要 求之傳輸線標準阻抗值,則調整參數w,s,t之取值 (單端傳輸線10之厚度t一般在2 lmu左右敁主要調 整W’ S之取值),再利用這三個參數確定之另-剖面 二維圖形輸入至仿真軟體,重新計算單端傳輸線1〇之特 徵阻抗值。經過參數值之多次:調整.、二維圖型之多次輸 、仿真軟體之多次計算,找出接近或等於標準阻抗 值之組參數值’按照這組參數值對單端傳輸線10和兩 接也層3G佈線’就可以實現單端傳輪線1G之阻抗控制。 本發也可以在單端傳輸線1〇之一側只設置一個接地層 同樣可以通過仿真軟體之計算取得合乎要求之參數值 。但與_各設置—個接地層相比,後者具有能夠排除 其他傳輸線對單料輸線㈣擾之優點。 本發明可實現 阻抗控制之兩層印刷電路板及方法 093131362 表舉编软AG1G1 « _ 0993344619- # 7頁/共15頁 ^39553 099年09月24日修正替换苜The value 'if the calculated characteristic impedance t is not f. Combined with the standard impedance value of the transmission line required by the brush board 3, the value of the parameter w, s, t is adjusted (the thickness t of the single-ended transmission line 10 is generally 2) The lmu is mainly adjusted to the value of W'S, and then the other two-dimensional graphics determined by these three parameters are input to the simulation software, and the characteristic impedance value of the single-ended transmission line is recalculated. After multiple parameter values: adjustment, multiple conversion of two-dimensional pattern, multiple calculations of simulation software, find the group parameter value close to or equal to the standard impedance value 'according to this set of parameter values to the single-ended transmission line 10 and Two-layer 3G wiring can be used to achieve the impedance control of the single-ended transmission line 1G. In the present invention, only one grounding layer can be provided on one side of the single-ended transmission line, and the desired parameter value can be obtained by calculation of the simulation software. However, compared with _ each set-ground layer, the latter has the advantage of being able to eliminate the interference of other transmission lines to the single-material transmission line (four). The present invention can realize two-layer printed circuit board and method for impedance control. 093131362 Table arranging soft AG1G1 « _ 0993344619- # 7 page / total 15 pages ^39553 Correction replacement 09 on September 24, 099
閱第四圖,用於USB2.0信號傳'輸'兩層印刷電路板5包括 複數個高速信號傳輸線(本實施例爲差分信號傳輸線50 )、一介質層60、複數個接地層70和複數個低速信號線 8〇。差分信號傳輸線50包括兩恒定間距、長度一致且信 號流向相反之傳輸線5 2、5 4。複數個接地層7 0與差分信 號傳輸線50佈置於介質層60上。每一差分信號傳輸線5〇 之兩側各設置一接地層70。接地層70之厚度等於差分信 號傳輪線50之厚度Τ ’接地層70之長度等於差分信號傳輸 線50之長度’每一接地層30到相鄰之傳輸線之距離爲s ,傳輸線52、54之間之距離爲Κ。USB2. 0傳輸線標準阻 <Referring to the fourth figure, the two-layer printed circuit board 5 for USB2.0 signal transmission includes a plurality of high-speed signal transmission lines (the differential signal transmission line 50 in this embodiment), a dielectric layer 60, a plurality of ground layers 70, and a plurality of A low speed signal line is 8 〇. The differential signal transmission line 50 includes two transmission lines 5 2, 5 4 of constant pitch, uniform length, and opposite signals. A plurality of ground layers 70 and differential signal transmission lines 50 are disposed on the dielectric layer 60. A ground layer 70 is disposed on each of both sides of each of the differential signal transmission lines 5A. The thickness of the ground layer 70 is equal to the thickness of the differential signal transmission line 50. The length of the ground layer 70 is equal to the length of the differential signal transmission line 50. The distance from each ground layer 30 to the adjacent transmission line is s, and between the transmission lines 52, 54. The distance is Κ. USB2.0 transmission line standard resistance <
抗值爲90歐姆。將如第四形輸入至 仿真軟體,計算出差分信號抗值,與 標準阻抗值作比較後調整參&數故’ F’ T (差分信號傳 輸線50之厚度T一般在2. lmil左右’故主要調整w,S,KThe resistance is 90 ohms. The fourth shape is input to the simulation software, and the differential signal resistance value is calculated. After comparing with the standard impedance value, the reference parameter is adjusted and the number is 'F' T (the thickness T of the differential signal transmission line 50 is generally about 2. lmil). Main adjustment w, S, K
之取值)之取值。再利用調整後之四個參數確定之另一 剖面二維圖形輸入至仿真軟體’重新計算差分信號傳輸 線50之特徵阻抗值。經過參數值之多次調整、二維圖型 之多次輸入以及仿真軟體之多次計算,找出接近或等於 標準阻抗值之一組參數值。 [0009] 綜上所述,本發明符合發明專利要件,爰依法提出專利 申請。惟,以上所述者僅為本發明之較佳實施例,舉凡 熟悉本案技藝之人士,在爰依本發明精神所作之等效修 飾或變化,皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0010] 第一圖係習知四層印刷電路板阻抗控制之剖面示意圖。 093131362 表單編號Λ0101 第8頁/共15頁 0993344619-0 1339553 099年09月24日梭正替換頁 第二圖係習知兩層印刷電路板之别面示意圖。 [0011] 第三圖係本發明可實現阻抗控制之兩層印刷電路板及方 法之第一實施例之剖面示意圖。 [0012] 第四圖係本發明可實現阻抗控制之兩層印刷電路板及方 法之第二實施例之剖面示意圖。 [0013] 【主要元件符號說明】 兩層印刷電路板:3、 5 [0014] 傳輸線:100、150、 52、54 [0015] 低速信號線:40、80 [0016] 接地層:120、160、 30 ' 7ΰ; ; . . : ;. [0017] 單端傳輸線:10 [0018] 介質層:110、130、 170 ' 20 ' 60 [0019] 差分信號傳輸線:50 • · 093131362 表單編號A0101 第9頁/共15頁 0993344619-0The value of the value). The other two-dimensional graph determined by the adjusted four parameters is input to the simulation software' to recalculate the characteristic impedance value of the differential signal transmission line 50. After multiple adjustments of the parameter values, multiple inputs of the two-dimensional pattern, and multiple calculations of the simulation software, find a set of parameter values that are close to or equal to the standard impedance value. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The first figure is a schematic cross-sectional view of a conventional four-layer printed circuit board impedance control. 093131362 Form No. Λ0101 Page 8 of 15 0993344619-0 1339553 September 24th, 2008, the second page is a schematic diagram of the two-layer printed circuit board. [0011] The third figure is a cross-sectional view of a first embodiment of a two-layer printed circuit board and method for achieving impedance control in accordance with the present invention. [0012] The fourth figure is a cross-sectional view of a second embodiment of a two-layer printed circuit board and method for achieving impedance control in accordance with the present invention. [Explanation of main component symbols] Two-layer printed circuit board: 3, 5 [0014] Transmission lines: 100, 150, 52, 54 [0015] Low-speed signal lines: 40, 80 [0016] Ground plane: 120, 160, 30 ' 7ΰ; ; . . : ;. [0017] Single-ended transmission line: 10 [0018] Dielectric layer: 110, 130, 170 ' 20 ' 60 [0019] Differential signal transmission line: 50 • · 093131362 Form No. A0101 Page 9 / Total 15 pages 0993344619-0
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TW93131362A TWI339553B (en) | 2004-10-15 | 2004-10-15 | Two-layer printed circuit board and method that make impedance controlled |
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TW200612803A TW200612803A (en) | 2006-04-16 |
TWI339553B true TWI339553B (en) | 2011-03-21 |
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TW93131362A TWI339553B (en) | 2004-10-15 | 2004-10-15 | Two-layer printed circuit board and method that make impedance controlled |
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US7603645B2 (en) | 2007-01-29 | 2009-10-13 | Inventec Corporation | Calibration method of insulating washer in circuit board |
TWI414216B (en) * | 2008-06-06 | 2013-11-01 | Hon Hai Prec Ind Co Ltd | Printed circuit board |
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