JP6858345B2 - Printed circuit board - Google Patents

Printed circuit board Download PDF

Info

Publication number
JP6858345B2
JP6858345B2 JP2017066652A JP2017066652A JP6858345B2 JP 6858345 B2 JP6858345 B2 JP 6858345B2 JP 2017066652 A JP2017066652 A JP 2017066652A JP 2017066652 A JP2017066652 A JP 2017066652A JP 6858345 B2 JP6858345 B2 JP 6858345B2
Authority
JP
Japan
Prior art keywords
power supply
wiring
region
wiring layer
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017066652A
Other languages
Japanese (ja)
Other versions
JP2018170403A (en
Inventor
真弘 深谷
真弘 深谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin AW Co Ltd
Original Assignee
Aisin AW Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin AW Co Ltd filed Critical Aisin AW Co Ltd
Priority to JP2017066652A priority Critical patent/JP6858345B2/en
Publication of JP2018170403A publication Critical patent/JP2018170403A/en
Application granted granted Critical
Publication of JP6858345B2 publication Critical patent/JP6858345B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、プリント配線基板に係り、例えば、コア層の両面側に配線用の各層が配置されたプリント基板に関する。 The present invention relates to a printed wiring board, and relates to, for example, a printed circuit board in which wiring layers are arranged on both sides of a core layer.

電子機器の普及に伴い、回路を構成する電子部品同士を接続する配線や、各電子部品に信号を伝送する配線や、電力を供給する配線が配設されたプリント配線基板が広く使用されている。
このプリント配線基板では、プリント配線基板上に配置する他の回路配線との干渉を避けるために、配線層を多層化することで配線層を変更している。異なる層に形成された配線を電気的に接続する場合には、ビア接続が使用されている。
電源供給元回路から電源供給先回路に電力を供給するための配線を他の配線層に変更する場合も同様で、層変更箇所の近傍において、電源供給先回路の消費電力に適した数量の電源ビアが形成される。
例えば、特許文献１では、第４の内層に電源配線を形成し、表面層から電源配線を接続する複数本の電源ビアが形成されている。 With the widespread use of electronic devices, wiring that connects electronic components that make up circuits, wiring that transmits signals to each electronic component, and printed wiring boards that are provided with wiring that supplies power are widely used. ..
In this printed wiring board, the wiring layer is changed by making the wiring layer multi-layered in order to avoid interference with other circuit wiring arranged on the printed wiring board. Via connections are used to electrically connect wires formed in different layers.
The same applies when the wiring for supplying power from the power supply source circuit to the power supply destination circuit is changed to another wiring layer, and the number of power supplies suitable for the power consumption of the power supply destination circuit is in the vicinity of the layer change location. Vias are formed.
For example, in Patent Document 1, a power supply wiring is formed in a fourth inner layer, and a plurality of power supply vias connecting the power supply wiring from the surface layer are formed.

図４は、従来のプリント配線基板における、電源ビアの配置状態を表した説明図である。
図４（ａ）は第１配線層の平面図で、電源供給元回路１５０と、電源供給元回路１５０からの電流が流れる電源配線１２１が形成されている。
一方、図４（ｂ）は第５配線層の平面図で、第５配線層に電源配線１２５が形成されている。
そして、電源配線１２１から電源配線１２５まで貫通する電源ビア１２０が、電源供給先回路（図示しない）の消費電力に応じた数だけ形成されている。
これにより、電源供給元回路１５０からの電流Ｉは、第１配線層の電源配線１２１から各電源ビア１２０、第５配線層の電源配線１２５を経由して、同様に複数配設された電源ビア１２０（図示しない）から電源供給先回路に供給される。 FIG. 4 is an explanatory diagram showing an arrangement state of power supply vias in a conventional printed wiring board.
FIG. 4A is a plan view of the first wiring layer, and the power supply source circuit 150 and the power supply wiring 121 through which the current from the power supply source circuit 150 flows are formed.
On the other hand, FIG. 4B is a plan view of the fifth wiring layer, and the power supply wiring 125 is formed in the fifth wiring layer.
A number of power supply vias 120 penetrating from the power supply wiring 121 to the power supply wiring 125 are formed according to the power consumption of the power supply destination circuit (not shown).
As a result, a plurality of currents I from the power supply source circuit 150 are similarly arranged from the power supply wiring 121 of the first wiring layer via the power supply vias 120 and the power supply wiring 125 of the fifth wiring layer. It is supplied to the power supply destination circuit from 120 (not shown).

しかし、図４に示すように複数の電源ビア１２０を、電源供給元回路１５０から電源供給先回路方向（水平方向）に並べて配置している。このため、電源供給元回路１５０から離れた側の領域Ｂに比べ、近い側の領域Ａ内の電源ビア１２０に電流が集中してしまっていた。
各電源ビア１２０に均等に電流が流れず、一部の電源ビア１２０に電流Ｉが集中することで、電源インピーダンスが増加してしまっていた。
単純に電源ビア１２０の数量を増やしたとしても、電源供給元回路１５０から更に離れた位置に配置することになるため、ビア数を増加しても電源インピーダンス低下の効果は低く、逆に、電源配線の面積が増加してしまう。 However, as shown in FIG. 4, a plurality of power supply vias 120 are arranged side by side in the power supply destination circuit direction (horizontal direction) from the power supply source circuit 150. Therefore, the current is concentrated in the power supply via 120 in the region A on the near side as compared with the region B on the side away from the power supply source circuit 150.
The current did not flow evenly in each power supply via 120, and the current I was concentrated in some power supply vias 120, so that the power supply impedance was increased.
Even if the number of power supply vias 120 is simply increased, the power supply source circuit 150 is located further away from the power supply source circuit 150. Therefore, even if the number of vias is increased, the effect of lowering the power supply impedance is low. The wiring area will increase.

特開２０１３−４８３０号公報Japanese Unexamined Patent Publication No. 2013-4830

本発明は、電源供給用に複数の電源ビアを配置した場合に、電源インピーダンスの増加を抑制することを目的とする。 An object of the present invention is to suppress an increase in power supply impedance when a plurality of power supply vias are arranged for power supply.

（１）請求項１に記載の発明では、第１配線層から第ｎ配線層と、前記第１配線層から第ｎ配線層における各配線層の間に配置された絶縁材と、前記第１配線層に形成された、電源供給元回路が接続される第１電源配線と、前記第１配線層に形成された、電源供給先回路が接続される第２電源配線と、前記第２配線層から第ｎ配線層のうちのいずれかの配線層に形成され、前記第１電源配線の投影領域と前記第２電源配線の投影領域を含み、両投影領域を接続する第３電源配線と、前記第１電源配線と前記第３電源配線とを電気的に接続する複数の第１電源ビアと、前記第２電源配線と前記第３電源配線とを電気的に接続する複数の第２電源ビアと、を備え、前記複数の第１電源ビアは、前記電源供給元回路から前記電源供給先回路に向かう方向よりも、直交方向に長い領域に配置され、前記第３電源配線は、前記第１電源ビアが配置される第１端部領域と、前記電源供給先回路への供給電力に対応する幅の中間領域と、前記第２電源ビアが配置される第２端部領域とを備え、前記中間領域の両端側は、それぞれ前記第１端部領域、前記第２端部領域に向かって拡幅する第１接続領域、第２接続領域で接続されている、ことを特徴とするプリント配線基板を提供する。
（２）請求項２に記載の発明では、前記第３電源配線の前記電源供給元回路側の端部と、前記第１電源配線は、前記直交方向に長く形成され、前記複数の第１電源ビアが配置される領域を含んでいる、ことを特徴とする請求項１に記載のプリント配線基板を提供する。
（３）請求項３に記載の発明では、前記複数の第２電源ビアは、前記電源供給元回路から前記電源供給先回路に向かう方向よりも、直交方向に長い領域に配置されている、ことを特徴とする請求項１又は請求項２に記載のプリント配線基板を提供する。
（４）請求項４に記載の発明では、前記第３電源配線の前記電源供給先回路側の端部と、前記第２電源配線は、前記直交方向に長く形成され、前記複数の第２電源ビアが配置される領域を含んでいる、ことを特徴とする請求項１、請求項２、又は請求項３に記載のプリント配線基板を提供する。 (1) In the invention according to claim 1, the insulating material arranged between the first wiring layer to the nth wiring layer, the first wiring layer to the nth wiring layer, and the first wiring layer. The first power supply wiring formed in the wiring layer to which the power supply source circuit is connected, the second power supply wiring formed in the first wiring layer to which the power supply destination circuit is connected, and the second wiring layer. A third power supply wiring formed in any of the n-th wiring layers, including the projection area of the first power supply wiring and the projection area of the second power supply wiring, and connecting both projection areas, and the said A plurality of first power supply vias that electrically connect the first power supply wiring and the third power supply wiring, and a plurality of second power supply vias that electrically connect the second power supply wiring and the third power supply wiring. The plurality of first power supply vias are arranged in a region longer in a direction orthogonal to the direction from the power supply source circuit to the power supply destination circuit, and the third power supply wiring is the first power supply. The intermediate region includes a first end region in which the vias are arranged, an intermediate region having a width corresponding to the power supplied to the power supply destination circuit, and a second end region in which the second power supply via is arranged. Provided is a printed wiring board characterized in that both end sides of the region are connected by the first end region, the first connection region widening toward the second end region, and the second connection region, respectively. To do.
(2) In the invention according to claim 2, the end of the third power supply wiring on the power supply source circuit side and the first power supply wiring are formed long in the orthogonal direction, and the plurality of first power supplies are formed. The printed wiring board according to claim 1, further comprising a region in which vias are arranged.
(3) In the invention according to claim 3, the plurality of second power supply vias are arranged in a region longer in a direction orthogonal to the direction from the power supply source circuit to the power supply destination circuit. The printed wiring board according to claim 1 or 2, wherein the printed wiring board is provided.
(4) In the invention according to claim 4, the end of the third power supply wiring on the power supply destination circuit side and the second power supply wiring are formed long in the orthogonal direction, and the plurality of second power supplies are formed. The printed wiring board according to claim 1, claim 2, or claim 3, further comprising an area in which vias are arranged.

本発明によれば、複数の第１電源ビアは、電源供給元回路から電源供給先回路に向かう方向よりも、直交方向に長い領域に配置されているので、電源インピーダンスの増加を抑制することができる。 According to the present invention, since the plurality of first power supply vias are arranged in a region longer in the orthogonal direction than the direction from the power supply source circuit to the power supply destination circuit, it is possible to suppress an increase in power supply impedance. it can.

本実施形態において配置される各回路の状態を表したプリント配線基板全体の平面図である。It is a top view of the whole printed wiring board which shows the state of each circuit arranged in this embodiment. 本実施形態のプリント配線基板における電源ビアの配置状態を表した断面図である。It is sectional drawing which showed the arrangement state of the power source via in the printed wiring board of this embodiment. 本実施形態のプリント配線基板における、電源ビアの配置状態を表した説明図である。It is explanatory drawing which showed the arrangement state of the power source via in the printed wiring board of this embodiment. 従来のプリント配線基板における、電源ビアの配置状態を表した説明図である。It is explanatory drawing which showed the arrangement state of the power source via in the conventional printed wiring board.

以下、本発明のプリント配線基板における好適な実施の形態について、図１から図３を参照して詳細に説明する。
（１）実施形態の概要
本実施形態では、複数の電源ビアを配置する場合に、電源供給元回路５０から電源供給先回路６０に向かう方向と直交する方向に配置する。これにより、各電源ビア２０に電流が略均等に流れ、その結果、一部の電源ビアへの電流集中を防ぎ、電源インピーダンスの増加が抑制される。
これは、流れる電流が減少する位置の手前までの距離（限界距離）の範囲内に各電源ビア２０が配置されているためである。すなわち、直交方向の端部に配置された電源ビア２０も、電源供給元回路５０の端部からの距離が限界距離以内に位置するため、直交方向の端部に配置された電源ビア２０を含め均等に電流が流れ、その結果電源インピーダンスの増加が抑制される。
そして、電源インピーダンスの増加が抑制されることで、より少ない数量（最低限）の電源ビアで所望の電源インピーダンスを満たすことができる。 Hereinafter, preferred embodiments of the printed wiring board of the present invention will be described in detail with reference to FIGS. 1 to 3.
(1) Outline of the Embodiment In the present embodiment, when a plurality of power supply vias are arranged, they are arranged in a direction orthogonal to the direction from the power supply source circuit 50 to the power supply destination circuit 60. As a result, the current flows through each power supply via 20 substantially evenly, and as a result, the current concentration on some power supply vias is prevented and the increase in power supply impedance is suppressed.
This is because each power supply via 20 is arranged within the range of the distance (limit distance) before the position where the flowing current decreases. That is, the power supply via 20 arranged at the end portion in the orthogonal direction also includes the power supply via 20 arranged at the end portion in the orthogonal direction because the distance from the end portion of the power supply source circuit 50 is located within the limit distance. The current flows evenly, and as a result, the increase in power supply impedance is suppressed.
Then, by suppressing the increase in the power supply impedance, a desired power supply impedance can be satisfied with a smaller number (minimum) power supply vias.

（２）実施形態の詳細
図１は本実施形態において配置される各回路の状態を表したプリント配線基板１全体の平面図である。
図１はプリント配線基板の１例であり、プリント配線基板が使用される各種電子機器を構成する、ＤＲＡＭ、Ｆｌａｓｈメモリなどの他、ＵＳＢ等の外部接続端子などの各種素子が配置されている。プリント配線基板には、後述する配線層（図示しない）が絶縁体を介して複数層配設され、各配線層に形成された配線によって各素子間が接続されている。
またプリント配線基板１には、電源供給元回路５０と、電源供給先回路６０が配置されている。
本実施形態では、電源供給元回路５０から電源供給先回路６０に電力を供給するための電源ビアとＧＮＤビアの配置に特徴がある。そのため、以下の説明では、図１において電源供給元回路５０と電源供給先回路６０を含む、点線領域Ｐを中心に説明する。 (2) Details of the Embodiment FIG. 1 is a plan view of the entire printed wiring board 1 showing the state of each circuit arranged in the present embodiment.
FIG. 1 is an example of a printed wiring board, in which various elements such as an external connection terminal such as USB are arranged in addition to a DRAM, a Flash memory, and the like constituting various electronic devices in which the printed wiring board is used. A plurality of wiring layers (not shown) described later are arranged on the printed wiring board via an insulator, and each element is connected by wiring formed in each wiring layer.
Further, a power supply source circuit 50 and a power supply destination circuit 60 are arranged on the printed wiring board 1.
In this embodiment, the arrangement of the power supply via and the GND via for supplying power from the power supply source circuit 50 to the power supply destination circuit 60 is characteristic. Therefore, in the following description, the dotted line region P including the power supply source circuit 50 and the power supply destination circuit 60 will be mainly described in FIG.

図２は、本実施形態のプリント配線基板１における電源ビア２０の配置状態を表した断面図である。
図２に示すように、プリント配線基板１の最上層である第１配線層１１には電源供給元回路５０と電源供給先回路６０が配設されている。そして、第１配線層１１には、電源供給元回路５０に接続された電源配線２１（第１電源配線）と、電源供給先回路６０に接続された電源配線２２（第２電源配線）が形成されている。
本実施形態のプリント配線基板１は、絶縁材であるコア層１０を挟んでその一方の面側に第１配線層１１〜第３配線層１３が形成され、他方の面側に第４配線層１４〜第６配線層１６が形成されている。すなわち、本実施形態では第ｍ配線層として第３配線層１３が形成され、第ｎ配線層として第６配線層１６が形成されている。 FIG. 2 is a cross-sectional view showing an arrangement state of the power supply via 20 in the printed wiring board 1 of the present embodiment.
As shown in FIG. 2, a power supply source circuit 50 and a power supply destination circuit 60 are arranged on the first wiring layer 11, which is the uppermost layer of the printed wiring board 1. The power supply wiring 21 (first power supply wiring) connected to the power supply source circuit 50 and the power supply wiring 22 (second power supply wiring) connected to the power supply destination circuit 60 are formed on the first wiring layer 11. Has been done.
In the printed wiring board 1 of the present embodiment, the first wiring layers 11 to 3 are formed on one surface side of the core layer 10 which is an insulating material, and the fourth wiring layer 13 is formed on the other surface side. The 14th to 6th wiring layers 16 are formed. That is, in the present embodiment, the third wiring layer 13 is formed as the mth wiring layer, and the sixth wiring layer 16 is formed as the nth wiring layer.

コア層１０は、プリント配線基板１内でコア材を使用している層であり、本実施形態ではガラス・エポキシ樹脂（ＦＲ−４）が使用されているが、グリーンシート（セラミック基板）等の各種公知の材料を使用することができる。
本実施形態のコア層の一方の面には第３配線層が形成され、他方の面には第４配線層が形成されている。 The core layer 10 is a layer in which a core material is used in the printed wiring board 1, and glass / epoxy resin (FR-4) is used in the present embodiment, but a green sheet (ceramic substrate) or the like is used. Various known materials can be used.
A third wiring layer is formed on one surface of the core layer of the present embodiment, and a fourth wiring layer is formed on the other surface.

第１配線層１１から第３配線層１３の各層間、及び、第４配線層１４から第６配線層１６の各層間には、絶縁材が配設されている。絶縁材としては、多層基板かビルドアップ基板かにより、プリプレグという接着シートを使用する等の各製造方法に応じた絶縁材が使用される。
第１配線層１１〜第６配線層１６には各素子を接続するための配線が形成されている。配線は銅箔で形成されている。 Insulating materials are arranged between the layers of the first wiring layer 11 to the third wiring layer 13 and between the layers of the fourth wiring layer 14 to the sixth wiring layer 16. As the insulating material, depending on whether it is a multilayer board or a build-up board, an insulating material corresponding to each manufacturing method such as using an adhesive sheet called prepreg is used.
Wiring for connecting each element is formed in the first wiring layer 11 to the sixth wiring layer 16. The wiring is made of copper foil.

また、図２に示すように、第５配線層１５には、他の配線との干渉を避けるための電源配線２５（第３電源配線）が形成されている。電源配線２５は、電源供給元回路５０が接続される電源ビア２０（第１電源ビア）と、電源供給先回路６０が接続される電源ビア２０（第２電源ビア）とを第５配線層１５で接続している。
これにより、電源供給元回路５０と電源供給先回路６０とが、両側の電源ビア２０と電源配線２５を介して接続され、図中に矢印で示すように電流Ｉが流れる。
なお、本実施形態では、電源配線２５を第５配線層に形成する場合について説明するが、第１配線層１１以外の他の配線層に形成するようにしてもよい。 Further, as shown in FIG. 2, the fifth wiring layer 15 is formed with a power supply wiring 25 (third power supply wiring) for avoiding interference with other wiring. In the power supply wiring 25, the power supply via 20 (first power supply via) to which the power supply source circuit 50 is connected and the power supply via 20 (second power supply via) to which the power supply destination circuit 60 is connected are connected to the fifth wiring layer 15. It is connected with.
As a result, the power supply source circuit 50 and the power supply destination circuit 60 are connected via the power supply vias 20 and the power supply wiring 25 on both sides, and the current I flows as shown by the arrows in the figure.
In this embodiment, the case where the power supply wiring 25 is formed in the fifth wiring layer will be described, but the power supply wiring 25 may be formed in a wiring layer other than the first wiring layer 11.

図３は、本実施形態におけるプリント配線基板１における、電源ビアの配置状態を表した説明図である。図３（ａ）は第１配線層１１の電源供給元回路５０と電源配線２１の平面図、（ｂ）は第５配線層１５に配置される電源配線２５の平面図である。
なお、図３では、電源供給元回路５０側について表しているが、電源供給先回路６０も同様に形成される。 FIG. 3 is an explanatory diagram showing an arrangement state of power supply vias in the printed wiring board 1 in the present embodiment. FIG. 3A is a plan view of the power supply source circuit 50 and the power supply wiring 21 of the first wiring layer 11, and FIG. 3B is a plan view of the power supply wiring 25 arranged in the fifth wiring layer 15.
Although the power supply source circuit 50 side is shown in FIG. 3, the power supply destination circuit 60 is also formed in the same manner.

図３（ａ）に示すように、本実施形態では、電源供給元回路５０に接続される電源配線２１の形状を、電源供給元回路５０から電源供給先回路６０に向かう方向と直交する方向（以下直交方向という）に長くなるように形成している。
電源配線２１には、電源供給元回路５０と面した領域Ａ（図４（ａ）に示す従来と同じ領域）に、電源ビア２０が形成されると共に、その直交方向両側の領域Ｃに同数の電源ビア２０が形成される。この領域Ｃの電源ビア２０は、図４（ａ）に示した、電流Ｉの流れが悪くなる従来の領域Ｂに形成した電源ビアを、領域Ａに対して直交する方向の両側に半数ずつ移動したものである。 As shown in FIG. 3A, in the present embodiment, the shape of the power supply wiring 21 connected to the power supply source circuit 50 is orthogonal to the direction from the power supply source circuit 50 to the power supply destination circuit 60 (). It is formed so as to be longer in the orthogonal direction (hereinafter referred to as).
In the power supply wiring 21, power supply vias 20 are formed in a region A (the same region as the conventional one shown in FIG. 4A) facing the power supply source circuit 50, and the same number of regions C on both sides in the orthogonal direction thereof are formed. The power via 20 is formed. The power supply via 20 in this region C moves the power supply via 20 formed in the conventional region B where the flow of the current I becomes poor, which is shown in FIG. 4A, by half on both sides in the direction orthogonal to the region A. It was done.

第５配線層１５に形成した電源配線２５は、図３（ｂ）に示すように、電源配線２５ａ（第１端部領域）と、電源供給先回路６０側に延設される電源配線２５ｃ（中間領域）と、電源配線２５ａと電源配線２５ｃとを接続する台形形状の電源配線２５ｂ（第１接続領域）から構成されている。
電源配線２５ｃは、配線の配置位置を第５配線層に変更して電源供給元回路５０からの電流Ｉを電源供給先回路６０に供給するためのものであり、その幅は、従来と同様に電源供給先回路６０に供給する電力に応じた幅に形成される。
なお、上述したように図示していないが、電源供給先回路６０側にも、第１配線層１１の電源配線２２の投影領域に形成された電源配線（第２端部領域）と、この電源配線と電源配線２５ｃとを接続する台形形状の電源配線（第２接続領域）とが形成されている。 As shown in FIG. 3B, the power supply wiring 25 formed in the fifth wiring layer 15 includes the power supply wiring 25a (first end region) and the power supply wiring 25c (extended to the power supply destination circuit 60 side). It is composed of an intermediate region) and a trapezoidal power supply wiring 25b (first connection region) that connects the power supply wiring 25a and the power supply wiring 25c.
The power supply wiring 25c is for changing the arrangement position of the wiring to the fifth wiring layer and supplying the current I from the power supply source circuit 50 to the power supply destination circuit 60, and the width thereof is the same as in the conventional case. The width is formed according to the power supplied to the power supply destination circuit 60.
Although not shown as described above, the power supply wiring (second end region) formed in the projection region of the power supply wiring 22 of the first wiring layer 11 and this power supply are also on the power supply destination circuit 60 side. A trapezoidal power supply wiring (second connection region) that connects the wiring and the power supply wiring 25c is formed.

電源配線２５ａは、電源配線２１の投影領域に、電源配線２１と同一形状に形成され、それぞれ領域Ａ、領域Ｃの各電源ビア２０で接続されている。
この両領域Ｃに配置した電源ビア２０は、いずれも電源供給元回路５０の角部（電源配線２１に接続される端面の両端部）からの距離が従来の領域Ｂ内の電源ビアまでの距離よりも短くなる（限界距離以内）ことで、領域Ａの電源ビア２０への電流の集中が抑制される。 The power supply wiring 25a is formed in the projection region of the power supply wiring 21 in the same shape as the power supply wiring 21, and is connected to each power supply via 20 in the regions A and C, respectively.
The power supply vias 20 arranged in both regions C have a distance from the corners (both ends of the end faces connected to the power supply wiring 21) of the power supply source circuit 50 to the power supply vias in the conventional region B. By making it shorter (within the limit distance), the concentration of the current on the power supply via 20 in the region A is suppressed.

そして、電源ビア２０を流れる電流は、第５配線層１５の電源配線２５ａから、電源配線２５ｂ、電源配線２５ｃを通り、電源供給先回路６０に形成された図示しない電源配線と電源ビア２０及び電源配線２２を通り電源供給先回路６０に供給される。
この際、電源配線２５ａと電源配線２５ｃを直接接続せずに、台形形状の電源配線２５ｂにより接続しているので、電源インピーダンスの増加が抑制されている。
なお、本実施形態では、電源配線２５ａと電源配線２５ｃとを、電源配線２５ｂを介して接続する場合について説明したが、電源配線２５ａと電源配線２５ｃとを直接接続するようにしてもよい。この場合、電源配線２５ａと電源配線２５ｃの幅は同一であっても、異なる幅であってもよい。以上の関係は電源供給先回路６０側においても同様であり、電源配線２２の投影領域に形成された電源配線２５ｄ（図示しない）と、電源配線２５ｃとを直接接続するようにしてもよく、この場合の両電源配線２５ｃ、２５ｄは同一幅、異なる幅のいずれでもよい。 Then, the current flowing through the power supply via 20 passes from the power supply wiring 25a of the fifth wiring layer 15 through the power supply wiring 25b and the power supply wiring 25c, and the power supply wiring, the power supply via 20 and the power supply (not shown) formed in the power supply destination circuit 60. It is supplied to the power supply destination circuit 60 through the wiring 22.
At this time, since the power supply wiring 25a and the power supply wiring 25c are not directly connected but are connected by the trapezoidal power supply wiring 25b, the increase in the power supply impedance is suppressed.
In the present embodiment, the case where the power supply wiring 25a and the power supply wiring 25c are connected via the power supply wiring 25b has been described, but the power supply wiring 25a and the power supply wiring 25c may be directly connected. In this case, the widths of the power supply wiring 25a and the power supply wiring 25c may be the same or different. The above relationship is the same on the power supply destination circuit 60 side, and the power supply wiring 25d (not shown) formed in the projection region of the power supply wiring 22 and the power supply wiring 25c may be directly connected. In this case, both power supply wirings 25c and 25d may have the same width or different widths.

以上説明したように、図３で説明した実施形態では、図４に示した従来との比較で同数の電源ビアを設ける場合について説明したが、本実施形態では、領域Ａ内の電源ビア２０への電源集中が抑制されるので、より少ない数の電源ビア２０で所望の電源インピーダンスを満たすことができる。
そのため図３の両領域Ｃに形成する電源ビア２０を減らしても、電源供給先回路６０への電力の要求を満たすことができる場合には、例えば、電源供給元回路５０から最も離れた領域Ｃ内の電源ビアを省略することができる。具体的には、図３（ａ）において図面上側の領域Ｃにおける右上の電源ビア２０と、下側の領域Ｃにおける右下の電源ビア２０を省略することができる。 As described above, in the embodiment described with reference to FIG. 3, the case where the same number of power supply vias are provided as compared with the conventional case shown in FIG. 4 has been described, but in the present embodiment, the power supply vias 20 in the region A are provided. Since the power supply concentration of the power supply is suppressed, a desired power supply impedance can be satisfied with a smaller number of power supply vias 20.
Therefore, if the power demand for the power supply destination circuit 60 can be satisfied even if the power supply vias 20 formed in both regions C in FIG. 3 are reduced, for example, the region C farthest from the power supply source circuit 50. The power via can be omitted. Specifically, in FIG. 3A, the power supply via 20 on the upper right in the area C on the upper side of the drawing and the power supply via 20 on the lower right in the area C on the lower side can be omitted.

１ プリント配線基板
１１〜１６ 第１配線層〜第６配線層
２０ 電源ビア
２１、２２ 電源配線
２５ａ、２５ｂ、２５ｃ 電源配線
５０ 電源供給元回路
６０ 電源供給先回路 1 Printed wiring board 11-16 1st wiring layer to 6th wiring layer 20 Power supply via 21, 22 Power supply wiring 25a, 25b, 25c Power supply wiring 50 Power supply source circuit 60 Power supply destination circuit

Claims (4)

第１配線層から第ｎ配線層と、
前記第１配線層から第ｎ配線層における各配線層の間に配置された絶縁材と、
前記第１配線層に形成された、電源供給元回路が接続される第１電源配線と、
前記第１配線層に形成された、電源供給先回路が接続される第２電源配線と、
前記第２配線層から第ｎ配線層のうちのいずれかの配線層に形成され、前記第１電源配線の投影領域と前記第２電源配線の投影領域を含み、両投影領域を接続する第３電源配線と、
前記第１電源配線と前記第３電源配線とを電気的に接続する複数の第１電源ビアと、
前記第２電源配線と前記第３電源配線とを電気的に接続する複数の第２電源ビアと、を備え、
前記複数の第１電源ビアは、前記電源供給元回路から前記電源供給先回路に向かう方向よりも、直交方向に長い領域に配置され、
前記第３電源配線は、前記第１電源ビアが配置される第１端部領域と、前記電源供給先回路への供給電力に対応する幅の中間領域と、前記第２電源ビアが配置される第２端部領域とを備え、
前記中間領域の両端側は、それぞれ前記第１端部領域、前記第２端部領域に向かって拡幅する第１接続領域、第２接続領域で接続されている、
ことを特徴とするプリント配線基板。 From the first wiring layer to the nth wiring layer,
An insulating material arranged between each wiring layer in the first wiring layer to the nth wiring layer, and
The first power supply wiring formed in the first wiring layer to which the power supply source circuit is connected and
The second power supply wiring formed in the first wiring layer to which the power supply destination circuit is connected and
A third wiring layer formed in any one of the second wiring layer to the nth wiring layer, including a projection area of the first power supply wiring and a projection area of the second power supply wiring, and connecting both projection areas. Power wiring and
A plurality of first power supply vias that electrically connect the first power supply wiring and the third power supply wiring,
A plurality of second power supply vias for electrically connecting the second power supply wiring and the third power supply wiring are provided.
The plurality of first power supply vias are arranged in a region longer in a direction orthogonal to the direction from the power supply source circuit to the power supply destination circuit .
In the third power supply wiring, a first end region in which the first power supply via is arranged, an intermediate region having a width corresponding to the power supplied to the power supply destination circuit, and the second power supply via are arranged. With a second end area
Both ends of the intermediate region are connected by the first end region, the first connection region widening toward the second end region, and the second connection region, respectively.
A printed wiring board characterized by this. 前記第３電源配線の前記電源供給元回路側の端部と、前記第１電源配線は、前記直交方向に長く形成され、前記複数の第１電源ビアが配置される領域を含んでいる、
ことを特徴とする請求項１に記載のプリント配線基板。 The end of the third power supply wiring on the power supply source circuit side and the first power supply wiring are formed long in the orthogonal direction and include a region in which the plurality of first power supply vias are arranged.
The printed wiring board according to claim 1. 前記複数の第２電源ビアは、前記電源供給元回路から前記電源供給先回路に向かう方向よりも、直交方向に長い領域に配置されている、
ことを特徴とする請求項１又は請求項２に記載のプリント配線基板。 The plurality of second power supply vias are arranged in a region longer in a direction orthogonal to the direction from the power supply source circuit to the power supply destination circuit.
The printed wiring board according to claim 1 or 2. 前記第３電源配線の前記電源供給先回路側の端部と、前記第２電源配線は、前記直交方向に長く形成され、前記複数の第２電源ビアが配置される領域を含んでいる、
ことを特徴とする請求項１、請求項２、又は請求項３に記載のプリント配線基板。 The end of the third power supply wiring on the power supply destination circuit side and the second power supply wiring are formed long in the orthogonal direction and include a region in which the plurality of second power supply vias are arranged.
The printed wiring board according to claim 1, claim 2, or claim 3.
JP2017066652A 2017-03-30 2017-03-30 Printed circuit board Active JP6858345B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017066652A JP6858345B2 (en) 2017-03-30 2017-03-30 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017066652A JP6858345B2 (en) 2017-03-30 2017-03-30 Printed circuit board

Publications (2)

Publication Number Publication Date
JP2018170403A JP2018170403A (en) 2018-11-01
JP6858345B2 true JP6858345B2 (en) 2021-04-14

Family

ID=64020616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017066652A Active JP6858345B2 (en) 2017-03-30 2017-03-30 Printed circuit board

Country Status (1)

Country Link
JP (1) JP6858345B2 (en)

Also Published As

Publication number Publication date
JP2018170403A (en) 2018-11-01

Similar Documents

Publication Publication Date Title
US9131602B2 (en) Printed circuit board for mobile platforms
US9934905B2 (en) Method of manufacturing multilayer board, multilayer board, and electromagnet
JP2016213308A (en) Printed circuit board and printed wiring board
JP2006190873A (en) Printed circuit board and electronic device comprising the same
CN105744739A (en) Printed Circuit Board And Method Of Manufacturing The Same
TW202031106A (en) Multilayer printed board
KR101046138B1 (en) Multilayer Wiring Board and Manufacturing Method Thereof
JP2009283771A (en) Laminate printed circuit board
JP6858345B2 (en) Printed circuit board
US11139101B2 (en) Coil component
JP2006270026A (en) Wiring structure, printed wiring board, integrated circuit, and electronic device
KR102262908B1 (en) Multi layer printed circuit board and manufacturing method thereof
JP2007150212A (en) Circuit board
JP2006302944A (en) Multilayer printed wiring board
JP6980174B2 (en) Printed wiring board
JP4838006B2 (en) Flexible printed wiring board
CN104080268B (en) A kind of pcb board
JP2007281004A (en) Multilayer wiring structural body and multilayer printed board
JP6871752B2 (en) Printed circuit board and printed circuit equipment
JP7272237B2 (en) electronic controller
JP2004327605A (en) Connection structure of printed circuit boards
TWI489922B (en) Multilayer circuit boards
JP6744201B2 (en) Printed wiring board
JP2009164166A (en) Printed circuit board
JP2006059928A (en) Printed circuit board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191017

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200814

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200828

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201027

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210222

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210307

R150 Certificate of patent or registration of utility model

Ref document number: 6858345

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20210423