TWI339374B - Shift register and liquid crystal display - Google Patents

Description

November 15th, 099, according to the positive ridge page changer and the liquid using the displacement register [0002] [0003] [0004] 095149690 表单 Form compilation A0101 VI. Description of the invention: [Technical field of invention] [0001] The present invention relates to a displacement temporary crystal display device. [Prior Art] = Membrane (4) (Thln FUm, coffee, m) Liquid crystal is not a standard output device that has gradually become a variety of digital products, iron, which needs to be designed appropriately to ensure its stable operation. Generally, the liquid crystal display driving circuit includes a data driving circuit and a scanning driving circuit data driving circuit for controlling the luminance of each _ pixel unit, and the driving and driving circuit riding, and the control is turned on and off. The two driver circuits are all applied to the core circuit unit. Generally, the displacement register is formed by connecting a plurality of displacement temporary storage units in series, and the output signal of the front-displacement temporary storage unit is a subsequent displacement temporary storage one-day input signal. Referring to Figure 1, there is a circuit diagram of a displacement temporary storage unit of the prior art shift register. The shift temporary storage unit also includes a -th clock inverting circuit 110, a commutation circuit 120, and a second clock inverting circuit 13A. Each circuit of the shift register unit 100 is composed of PMOS (p_channel Metai_)

Oxide Semiconductor, a p-channel metal oxide semiconductor type transistor, each of the PMOS transistors includes a gate, a source, and a gate. The first clock inverting circuit 1 10 includes a first PMOS transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first output terminal V01, and a first The second output is v〇2. The first transistor M1 page 5 / 31 pages 0993409550-0 [0005] The gate of 1339374 receives the output signal VS of a displacement temporary storage unit before the displacement temporary storage unit 100, and the source receives the high level from the external circuit. The potential signal VDD has its drain connected to the source of the second transistor M2. The gate of the second transistor M2 and its drain receive the low potential signal VSS from the external circuit. The gates of the third transistor M3 and the fourth transistor M4 receive the inverted clock signal from the external circuit: ^, and the drains of the two are respectively used as the first output terminal V01 of the first clocked inverter circuit 110. And a second output terminal V02, wherein the source of the third transistor Μ3 is connected to the drain of the first transistor ,1, and the source of the fourth transistor Μ4 is connected to the gate of the first transistor M1 . [0006] The converter circuit 120 includes a fifth electrical amplifier, a sixth transistor M6, and a signal output terminal VO. The fifth electricity: crystal | 5 capacity t # pole 接: connected to the first office. Two S-... output VO 1, its source receives ^ ip% road high 'check signal VDD, Its drain is connected to the source of the sixth transistor M6. The gate of the sixth transistor M6 is connected to the second output terminal V02, and the drain thereof receives the low potential signal VSS from the external circuit, and the source thereof is the signal output terminal VO of the displacement temporary storage unit 100. The second clock inverting circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the seventh transistor M7 is connected to the signal output terminal VO, the source thereof receives the high potential signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor M8. The gate of the eighth transistor M8 and its drain receive a low potential signal VSS from an external circuit. The source of the ninth transistor M9 is connected to the first output terminal V01, the gate thereof receives the clock signal TS from the external circuit, and the drain thereof is connected to the drain of the seventh transistor M7. The tenth electric 095149690 Form No. A0101 Page 6 / Total 31 Pages 0993409550-0 1339374 * % [0008] November 19, 099 8^正 & Page 139 November 15th 11 The terminal receives the clock of the external circuit The signal TS, the second output terminal V〇2 of the ^^7, is connected to the signal wheel output terminal v〇. Referring to Figure 2, 'the displacement temporary storage unit' is the working sequence diagram of the dry 100. During the T1 period, the previous shift register unit recognizes that the round-up signal VS changes from high potential to low potential, and the inverted clock signal _ , TS changes from low potential to high power aa

The bit causes the third transistor M3 and the fourth transistor _40, (4) to turn off the first clock inverting circuit "0. The clock signal (10) transitions from a high potential to a low potential to turn on the ninth transistor (4) and the tenth transistor Mi ,, thereby turning on the second NMOS circuit 13 (), and the signal output terminal vo The high potential in the initial state passes through the tenth transistor M1〇, so that the sixth transistor Μ 6 is stopped, and the low potential of the eighth electric g 缉 plus 8 output is made fifth by the ninth transistor M9 ′ The electric battery μ 5. is turned on, and then the source high potential signal VDD is output to the signal output terminal ν〇, so the signal output terminal VO maintains a high potential output. [0009] In the Τ2 period, the inverted clock signal changes from a high potential to a low potential, and the third transistor M3 and the fourth transistor JJ4 are turned on, thereby causing the first clock inverting circuit 110 is turned on. When the clock signal TS transitions from a low potential to a high potential, the ninth transistor Μ9 and the tenth transistor Μ10 are turned off, and the second clocked inverter circuit 130 is turned off. When the input signal VS changes from a high potential to a low potential, the first transistor mi is turned on, and the high potential VDD of the source is turned off by the third transistor M3 to the fifth transistor M5 ′ and the input signal The low potential of VS is turned on by the fourth transistor M4 to turn on the sixth transistor M6, so that the signal output terminal v〇 outputs a low potential. During the T3 period, the inverted clock signal; ^ changes from low potential to high potential 095149690 Form No. A0I01 Page 7 of 31 0993409550-0 [0010] 1339374

In November 039, the second transistor Μ 3 and the fourth transistor Μ 4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal TS is turned from a high potential to a low potential, and the ninth transistor Μ9 and the tenth transistor M10 are turned on, thereby turning on the second clocked inverter circuit 130. The low potential of the signal output terminal V0 turns on the seventh transistor M7, and the high potential of the source thereof is turned off by the ninth transistor M9 to the fifth transistor M5. At the same time, the low potential of the signal output terminal V0 also passes through the tenth transistor M10 to turn on the sixth transistor M6. The drain potential of the sixth transistor M6 causes the signal output terminal V0 to maintain a low potential output. [0011] During the T4 period, the inverted clock signal changes from a high potential to a low potential, and the third transistor M3 and the #4 are further caused to cause the first clocked inverter circuit 110 to be turned on. The output transitions from a low potential to a high potential, causing the ninth transistor M9 and the tenth transistor M10 to be turned off, thereby causing the second clock inverting circuit 120 to be turned off. The high potential of the input signal VS is turned off by the fourth transistor M4, and the second low voltage of the second transistor M2 is turned on by the third transistor M3 to turn on the fifth transistor M5. The high potential of the source 'rounds to the signal output terminal VO, causing the output of the signal output terminal VO to jump from a low potential to a high potential. [0012] It can be seen from the working sequence that the displacement temporary storage unit 100 outputs a signal in the T1 period and the T2 period, and the displacement temporary storage unit 100 outputs the signal in the T2 period and the T3 period, and the second output signal There is signal overlap in the T2 period, which leads to the liquid crystal display device using the displacement register as the data driving circuit and the scanning driving circuit. When performing column scanning or blocking scanning, there are adjacent columns (Row) or columns (Column). At the same time 095149690 Form No. A0101 Page 8 / Total 31 Pages 0993409550-0 1339374 __ 'November 15th, 999: The phenomenon of scanning the page is being replaced, causing the load signals to interfere with each other and causing chromatic aberration on the screen. SUMMARY OF THE INVENTION [0013] In view of the above, it is necessary to provide a displacement register with no overlapping output signals. [0014] In addition, it is also necessary to provide a liquid crystal display device capable of avoiding signal interference [0015]

A displacement register includes a complex displacement temporary storage unit. Each displacement temporary storage unit is connected to the clock signal from the external circuit, and the two adjacent displacement temporary storage unit receives the second clock signal and the front displacement temporary storage list.

r. · '»·*. V . -V' -. The output signal of the element is the latter displacement temporary storage card. Each bit shifting unit includes a signal transmission: a second circuit: an input circuit and a logic conversion circuit. The signal output circuit receives a first clock signal from an external circuit, and includes a first transistor and a second transistor 1. The first clock signal is broken by the first transistor, and a cutting signal is passed through the signal. Second transistor output. The signal input circuit is received from the external circuit, the .r, the second clock signal and the output signal of the previous stage of the temporary unit, and outputs a control signal to the first transistor of the signal output circuit, which includes a third transistor that is always in an on state, the third transistor discharging to the output of the signal input circuit and keeping its output signal unchanged for one clock cycle. The logic conversion circuit receives the output signal of the signal input circuit and outputs a control signal to control the on and off of the second transistor. When the signal input circuit inputs the communication number, the communication number turns on the first transistor and the logic conversion circuit, so that the first clock signal is output through the first transistor, and the logic conversion circuit outputs 095149690 form number A010] Page 9 of 31 0993409550-0 1339374

Pgs year November 15 3 Yanzheng Bobai H<I a wear stop signal 'to make the second transistor cut off, and vice versa' when the signal input circuit inputs the cutoff signal, the first transistor is turned off, the logic conversion circuit The first communication signal is automatically outputted to turn on the second transistor, thereby outputting a cutoff signal. [0016] A liquid crystal display device comprising a liquid crystal panel, a data driving circuit and a scan driving circuit. The data driving circuit and the scan driving circuit each include a displacement register. Each displacement register includes a plurality of displacement temporary storage units, each displacement temporary storage unit is connected to a clock signal from an external circuit, and the two adjacent displacement temporary storage units receive the opposite two clock signals, $ and the previous displacement is temporarily suspended. The output signal of the storage unit is the input signal of the latter displacement temporary storage unit. Each displacement temporary storage ^ output circuit,

A total of II signal input circuit and a logic switch. The arm output circuit receives the first clock signal from the external circuit, and includes a first transistor and a second transistor. The first clock signal is output through the first transistor, and the second signal is output through the second transistor. Crystal loss: out. The signal input circuit receives the second clock signal from the external circuit and the output signal of the previous stage displacement register unit, and outputs the power to the signal, and the winter first transistor outputs the control signal, which includes an always-on state. a third transistor that discharges to the output of the signal input circuit and keeps its output signal unchanged for one clock cycle. The logic conversion circuit receives the output signal of the signal input circuit and outputs a control signal to control the on and off of the second transistor. When the signal input circuit inputs the communication number, the communication number turns on the first transistor and the logic conversion circuit, so that the first clock signal is output through the first transistor, and the logic conversion circuit outputs a cutting signal, so that the logic conversion circuit outputs a cutting signal The second transistor is turned off. 095149690 Form No. A0101 Page 10 of 31 0993409550-0 1339374 _-__- On November 15th, 999, the replacement page is turned on. When the signal input circuit inputs the stop signal, the first transistor is turned off. The logic conversion circuit automatically outputs a pilot communication number to turn on the second transistor, thereby outputting a cutoff signal.

[0017] the displacement temporary storage unit receives the communication communication number from the external circuit, and when the first clock signal is the conduction communication number, the displacement temporary storage unit outputs a guiding communication number, and the guiding communication number is input to the subsequent displacement temporary storage unit, And charging its third transistor. When the first clock signal is a cutoff signal, the second clock signal is a pilot communication number, the displacement temporary storage unit outputs a cutting signal, and the third transistor of the latter displacement temporary storage unit discharges the first transistor Keeping on, and then outputting the second clock signal is a pilot number. Since the first clock signal and the second clock signal are mutually inverted signals, the output signals of the phase two displacement temporary storage unit of the displacement register are not overlapped, and the liquid crystal display device using the displacement register does not appear. The phenomenon of scanning adjacent columns or columns simultaneously prevents the load signals from interfering with each other, and the screen does not cause chromatic aberration. [Embodiment] [0018] Please refer to FIG. 3, which is a circuit block diagram of a preferred embodiment of a displacement register of the present invention. The shift register 20 includes a plurality of shift register units 200 of the same structure. The plurality of displacement temporary storage units 200 are connected in series, and the output signal of the previous displacement temporary storage unit 200 is the input signal of the subsequent displacement temporary storage unit 200. Each of the shift register units 200 includes a clock signal input pin CLK and an inverted clock signal input pin.

The CLK signal input pin VIN, a first signal output pin VOUT1, a second signal output pin VOUT2, and a test signal pin VCT. The shift register 20 receives the external circuit from the clock signal input pin CLK of the shift register unit 200 ( 095149690 Form No. A0101 Page 11 / Total 31 Page 0993409550-0 1339374 }059¥ϊΐ^ι5日日正杂页Ί| Figure not shown) clock input signal CLOCK, its inverted clock signal input pin

CLK receives the inverted clock input signal from an external circuit

CLOCK, the signal input pin VIN is used as the signal input end of the displacement temporary storage unit 200, and the first signal output pin V0UT1 is connected to the signal input pin VIN of the subsequent displacement temporary storage unit 200, and the second signal output pin is cited. The pin V0UT2 outputs a signal to the external circuit, and the test signal pin VCT receives the test signal VT from the external circuit. The connection mode of the latter displacement temporary storage unit 200 is similar, and the difference is that the clock signal input pin CLK of the latter displacement temporary storage unit 200 receives the inverted clock input signal CLOCK. from the external circuit, and the inverted clock signal input thereof. The pin 1 receives the clock input signal from the external circuit and the connection mode of the reference element 200 follows the aforementioned two-displacement temporary storage unit 'heat. Then, the clock [0019] signal input pin CLK and its inverted clock signal input pin alternately receive the clock input signal CLOCU the inverted clock input signal CLOCK. Please refer to FIG. 4 , which is a circuit diagram of the displacement temporary storage unit 2 位移 temporary storage unit 2 . The shift register unit 2 includes a signal wheel circuit (1), a logic conversion circuit 212, a test signal input circuit 213, and a signal output power supply 4. The signal is input to the output end of the circuit and the round end of the test signal input circuit 213 is connected to the - node. The temporary storage of the displacement is composed of ρ_ type electro-optical crystal, and each transistor includes a gate, a source and a drain. The signal input circuit 2] ι sentence knowledge ^1 includes - the first transistor P1, a second transistor

CLK respectively

095149690 12th ear/total 31 pages 0993409550-0 [0020] 1339374 » « On November 15, 099, the shuttle is replacing page P2 and a third transistor P3. The drain of the first transistor P1 receives the low potential signal VGL from the external circuit, the gate is the input signal pin VIN of the displacement temporary storage unit 200, and the source thereof is connected to the drain of the second transistor P2. . The source of the second transistor P2 is connected to the gate of the first transistor P1, and the gate thereof is an inverted clock signal input pin of the displacement temporary storage unit 200.

CLK has its drain connected to the source of the third transistor P3. The gate of the third transistor P3 receives a low potential signal VGL from an external circuit, which is connected to node 218. [0021] The logic conversion circuit 21 2 includes a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, and a seventh transistor, a crystal P7. The fourth transistor

The drain and gate of V.V P4 receive the low potential signal VGL from the external, circuit, and its source is connected to the drain of the fifth transistor P 5 '. The fifth: five transistor P 5

The gate is coupled to the node 218 and its source receives the high potential signal VGH from an external circuit. The gate of the sixth transistor P6 is connected to the source of the fourth transistor P4, the drain thereof receives the low potential signal VGL from the external circuit, and the source thereof is connected to the drain of the seventh transistor P7. The gate of the seventh transistor P7 is coupled to the node 218, and its i-pole receives the high potential signal V G 来自 from the external circuit. [0022] The signal output circuit 214 includes an eighth transistor Ρ8, a ninth transistor Ρ9, a tenth transistor Ρ10 and an eleventh transistor Ρ11. The drain of the eighth transistor Ρ8 is the clock signal input pin CLK of the displacement temporary storage unit 200, the gate thereof is connected to the node 218, and the first signal output of the displacement temporary storage unit 200 is taken out from the source thereof. Foot VOUT1. The gate of the ninth transistor Ρ9 is connected to the source of the sixth transistor ,6, and the drain thereof is connected to the 095149690. Form No. 1010101 Page 13 of 31 0993409550-0 1339374

[November 1993, 15S is replacing the source of r I eighth transistor P8, and its source receives high potential signal VGH from an external circuit. The drain of the tenth transistor P10 is connected to the clock signal input pin CLK, the gate thereof is connected to the node 218, and the second signal output pin V0UT2 is taken out from the source thereof. The drain of the eleventh transistor P11 is connected to the source of the tenth transistor P10, the gate thereof is connected to the source of the sixth transistor P6, and the source thereof receives the high potential signal VGH from the external circuit. [0023]

The test signal input circuit 213 includes a twelfth transistor P12. The gate of the twelfth transistor P12 is a test signal pin VCT whose source is connected to its gate and whose drain is connected to the node 218. [0024] Please refer to FIG. 5, which is a temporary suspension punch. During the T1 period, the input signal pin VIN receives: the external-whip power. The road father signal is at the potential signal V G L , and the clock input signal CLOCK changes from a high potential to a low potential, and the inverted clock input signal

CLOCK changes from low potential to high potential, the first

The transistor P1 is turned on, the second transistor P2 is loaded, and the third transistor P3 is directly in an on state, which acts like a capacitor. The 汲·very low potential signal VGL of the first transistor P1 is outputted from the node 218 by the second transistor P3 at a low potential while charging the third transistor P3. When the voltage of the node 218 is floating, the third transistor P3 holds the voltage of the node 218, causing the node 218 to output a stable low potential. The low potential output from the node 218 turns on the eighth transistor P8 and the tenth transistor P10, and the low potential of the clock signal pin CLK is output through the eighth transistor P8 and the first signal output pin V0UT1. The lower displacement register unit 200 outputs a low potential signal VGL, which is also 095149690, form number A0101, page 14 / total 31 pages, 0993409550-0 1339374 •

[0025] The replacement page is corrected on November 15, 099. The tenth transistor P1 0 and the second signal output pin VOUT2 output a low potential signal VGL to the external circuit. In addition, the low potential output from the node 218 also turns on the fifth transistor P5 and the seventh transistor P7 of the logic conversion circuit 212, and the fifth transistor P5 and the seventh transistor P7 output a high potential to the The ninth transistor P9 and the gate of the eleventh transistor P11 turn off the ninth transistor P9 and the eleventh transistor P11, thereby outputting the first signal output pin VOUT1 and the second signal The output of the pin VOUT2 is not affected by the high potential of the ninth transistor P9 and the eleventh transistor PI1. During the T1 period, when the first signal output pin VOUT1 of the displacement temporary storage unit 200 inputs a low potential to the subsequent displacement temporary storage unit 200, the clock signal of the latter displacement temporary storage unit 200 is injected into the pin CLK. Receive inverted clock input signal from an external circuit

CLOCK, its inverted clock signal input pin

CLK

Receive clock input signal from external circuit CLOCK

At this time, the clock input signal CLOCK is low, and the inverted clock input signal

CLOCK is high, so that the first transistor and the second transistor of the latter displacement temporary storage unit 200 are turned on, the signal input circuit 211 outputs a low potential, and the third transistor is charged to ensure the signal input circuit thereof. The 211 outputs a stable low potential in one clock cycle, and the signal output circuit 211 of the subsequent shift register unit 211 outputs a low potential, so that the logic conversion circuit 212 turns off the ninth transistor and the tenth transistor, and the signal thereof Output 095149690 circuit 211 output and inverted clock input signal

CLOCK Synchronous high-potential form number A0101 Page 15 / Total 31 page 0993409550-0 1339374 [0026] [0028] [0028] 095149690 Π ri Γί Ί *1 α ^ r- η <**· —Τ~ -Π - 丄丄乃丄:? mouth

During the Τ2 period, the input signal of the input signal pin V1N of the shift register unit 200 is changed from a low potential to a high potential. The clock input signal CLOCK transitions from a low potential to a high potential, the inverted clock input signal ^ CLOCK transitions from a high potential to a low potential, and the second transistor P2 is turned on, causing the output of the node 218 to be changed from a low potential to a low potential. The high potential further turns off the eighth transistor P8 and the tenth transistor P10. At this time, the output of the low voltage signal VGL of the fourth transistor P4 and the source of the sixth transistor P6 turns on the ninth transistor P9 and the eleventh transistor P11, thereby making the first signal output pin The output signal of V0UT1 and the second signal output pin V0UT2 is changed from a low potential to a high potential, thereby implementing a logic conversion function. During the T2 period, when the displacement is temporarily stored, the #元液-displacement temporary storage unit ^ ·:Ί·一;. 2 0 0 receives the first signal output IFs§P_T-l round #^ high potential, its clock The signal pin CLK is low, and the inverted clock signal input pin is high, so that the first transistor LLiL body and the second transistor of the latter shift register unit 200 are turned off, and the energy is stored in the T1 period. The third transistor starts to discharge, so that the signal input circuit 211 of the subsequent displacement temporary storage unit 200 maintains a low potential output, and the output low potential turns on the eighth transistor and the tenth transistor of the signal output circuit, thereby making the first The output signals of one signal output pin V0UT1 and the second signal output pin V0UT2 are changed from high potential to low potential. The test signal input circuit 213 is kept in an off state under normal operation, and has no effect on the operation of the shift register, and is started only when the liquid crystal panel is tested.

As can be seen from the working timing, when the input signal pin VIN receives a low form number A0101, page 16 / a total of 31 pages 0993409550-0 [0029] when the provincial year n month is the day to replace the page potential conduction communication number The low potential signal VGL causes the eighth transistor 卩8 and the tenth transistor P1 〇 to conduct a clock input signal CLOCK of the source thereof, and outputs the clock input signal to the subsequent shift register unit 2 〇CK. When the clock input signal CLOCK outputs an effective potential, the third transistor of the subsequent shift register unit 200 starts to be charged to ensure that the signal input circuit 211 stably outputs a low potential within one clock cycle, even if the latter displacement is temporarily stored. The eighth transistor P8 and the ninth transistor p9 of the cell 2Q() are turned on to output an inverted clock input signal of the source thereof. Since the input 讥CLOCK and the inverted clock input signal ^_ wave

匕 LOCK is reversed, so the displacement of the temporary storage list - afterwards - the output waveform of the displacement temporary storage unit 2 0 0 does not overlap. Please refer to FIG. 6, which is a schematic structural diagram of an active matrix liquid crystal display device using the displacement temporary storage (4). The liquid crystal display device 30 includes a liquid crystal display panel 31 data driving circuit 3 and a scan driving circuit 33. The liquid crystal display panel 31 includes a substrate (not shown), a lower substrate (shown in FIG. 1), and a liquid crystal layer (not shown) sandwiched between the upper substrate and the lower base, and adjacent to the liquid crystal layer on the lower substrate. a side is provided with a thin film transistor array (not shown) for controlling the twisting condition of the liquid crystal molecules. The scan driving circuit 33 outputs a scanning signal to control the on and off states of the thin film transistor matrix of the liquid crystal display panel 31, The data driving circuit 32 outputs a data signal to control the display change of the liquid crystal display device 30. The scan driving circuit 33 and the data driving circuit 32 both use the shift register 2 to control the input (four) sequence of the scan signal and the data signal, thereby Controlling the display of the liquid crystal display panel 31. The displacement register 20 can be associated with the liquid crystal display device 3, the form number A0101, the third page, a total of 31 pages, 0993409550-0 1339374 I Π η Λ Ί · ϊ α ί γ- R—ι ΙΛγ-γ- ±±^^. -arl 丄丄/3 丄l>m ΚΜϋ'ρτΐη Only i thin film transistor arrays are formed in the same process. [0031] Due to the stages of the displacement register 20 Displacement temporary storage unit 200 There is no signal overlap in the output, so that the liquid crystal display device 30 using the displacement register 20 as the scan driving circuit 32 and the data driving circuit 33 does not generate output scan signals and data signals when performing column scanning or column scanning. Signal interference, thereby avoiding chromatic aberration on the display screen. [0032] In summary, the present invention meets the requirements of the invention patent, and the patent application is filed according to law. However, the above is only a preferred embodiment of the present invention, and is familiar with the case. The equivalents or changes made by the skilled person in the spirit of the creation of the case shall be included in the following patent application, Fan Wei. Cao.. Double 1::3⁄4. • :' .V. .-ϋ, '·".· [Simple description of the schema]

[0033] FIG. 1 is a circuit diagram of a prior art displacement temporary turtle: a shifting unit [0034] FIG. 2 is a timing chart of the operation of the displacement temporary storage unit shown in FIG.

3 is a circuit block diagram of a preferred embodiment of the displacement register of the present invention. [0036] FIG. 4 is a circuit diagram of a displacement temporary storage unit of the displacement register shown in FIG. 5 is a timing chart showing the operation of the shift register shown in FIG. 3. 6 is a schematic structural view of an active matrix liquid crystal display device to which the displacement register shown in FIG. 3 is applied. [Description of Main Component Symbols] [0039] Displacement Register 20 [0040] Displacement Temporary Unit 200 095149690 Form No. A0101 Page 18 of 31 0993409550-0 1339374 November 15th, 1999, the replacement page [0041] Signal input circuit 211 [0042] Logic conversion circuit 212 [0043] Test signal input circuit 2 1 3 [0044] Signal output circuit 214 [0045] Node 2 1 8 [0046] Liquid crystal display device 30 [0047] Liquid crystal display panel 3 1 [0048] data driving circuit 3 2 [0049] scan driving circuit 3 3

[0050] clock signal input pin CLK

[0051] Inverted clock signal input pin π

[0055] [0056] The first signal output pin VOUT1, the second signal output pin VOUT2

Test signal pin VCT

Clock input signal CLOCK inverted clock input signal

CLOCK

[0057] High potential signal VGΗ

[0058] Low potential signal VGL

[0059] Test signal

VT 095149690 Form No. Α0101 Page 19 of 31 0993409550-0 1339374 I g λ r— r-^ t*.» i i ' 1

I 丄丄大)丄5 口 I

[0060] Signal Input Pin VIN [0061] First Transistor P1 [0062] Second Transistor P2 [0063] Third Transistor P3 [0064] Fourth Transistor P4 [0065] Fifth Transistor P5 [0066] The sixth transistor P6 [0067] The seventh transistor P7 [0068] The eighth transistor P8 [0069] The ninth transistor P9 [0070] The tenth transistor P10 [0071] The eleventh transistor P11 [0072] Twelfth transistor P12

095149690 Form No. A0101 Page 20 of 31 0993409550-0

Claims (1)

1339374 _ November 15, 1999, nuclear replacement page VII, the scope of application for patents: 1 · A displacement register, including: a complex displacement temporary storage unit, each displacement temporary storage unit receives two clocks from the external circuit The two clock signals received by the two adjacent displacement temporary storage units are opposite, and the output signal of the previous displacement temporary storage unit is the input signal of the latter displacement temporary storage unit, and each displacement temporary storage unit includes: a signal output a circuit that receives a first clock signal from an external circuit, the method comprising: a first transistor that outputs the first clock signal; and a second transistor that outputs a cutoff signal; a signal input circuit that receives the output signals of the first two shift register units and the external circuit and the The first clock m is opposite to the second clock signal, and outputs a control signal to the first transistor of the signal output circuit, comprising: a third transistor, which is always in an on state, and outputs to the signal input circuit The terminal discharges and keeps its output signal unchanged for one clock cycle\>; and a logic conversion circuit that receives the output signal of the read/round-in circuit, and • t· · · (φ, output-control a signal, which controls the conduction and the cutting of the second transistor; wherein, when the signal input circuit inputs the communication number, the communication number turns on the first transistor and the logic conversion circuit, so that the first clock signal passes the first The transistor outputs, and the logic conversion circuit outputs a wear signal to turn off the second transistor; otherwise, the signal input circuit inputs the cutoff signal to make the first The transistor is turned off, and the logic conversion circuit automatically outputs a conduction signal to turn on the second transistor, thereby outputting a wearing signal 〇095149690 Form No. 1010101 Page 21/31 Page 0993409550-0 1339374 I r» r> ri λ λ ο ί - » - 2 - - - 2 2 2 2 2 j j j j j j j j j j j j j I I I I I I I I I I I I I I I I I I I I I I I I I I I The displacement temporary storage unit is composed of a plurality of transistors. The displacement register according to claim 2, wherein the transistor is a PMOS type transistor. The displacement register described in item 2, wherein the signal The input circuit further includes a fourth transistor and a fifth transistor, wherein the drain of the fifth transistor receives the low potential signal from the external circuit, and the gate of the fourth transistor and the source of the fourth transistor receive the previous displacement The output signal of the temporary storage unit has a source connected to the second electrode of the fourth transistor. The gate of the fourth transistor receives the second clock input signal, and the gate of the third transistor receives the low potential signal. , its bungee is connected to the Pan Tengdian·Qin Ji^ humiliation, from its source; ' ;' V*·..... 浐: Wide-pole output of the signal input circuit: 3⁄43⁄43⁄4 5 . In the fourth aspect, the logic conversion circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the sixth transistor The pole receives the low potential signal of the external circuit, the gate is connected to the drain, the source is connected to the drain of the seventh transistor; the source of the seventh transistor receives the high potential signal of the external circuit, and the gate thereof Connected to the gate of the ninth transistor, the anode of the eighth transistor receives a low potential signal of the circuit, the gate of which is connected to the source of the sixth transistor, the source of which is connected to the drain of the ninth transistor; the gate of the ninth transistor receives the output of the signal input circuit The signal, the bungee receiving the high-potential signal of the external circuit. 6. The displacement register according to claim 2, wherein the displacement temporary storage unit further comprises a test signal input circuit. The displacement register of the sixth aspect, wherein the test signal input circuit comprises a tenth transistor, a gate of the tenth transistor, and 095149690, a form number A0101, page 22, a total of 31 pages, 0993409550-0 1339374 » On November 15, 099, the replacement page source receives the test signal from the external circuit, and the drain receives the signal from the logic conversion circuit and the signal output circuit. 8. The displacement register of claim 2, wherein the signal output circuit further comprises an eleventh transistor and a twelfth transistor, the first transistor and the eleventh The drain of the crystal receives the first clock signal, the gate receives the input signal of the signal input circuit, and the drain outputs the signal respectively; the gate of the second transistor and the twelfth transistor receives the logic conversion circuit The control signal has a source receiving a high potential signal of the external circuit, and a drain electrode connected to the first transistor and the eleventh transistor. 9. A liquid crystal display device comprising: • r Λ a liquid crystal panel; a data driving circuit including a shifting memory; and a scan driving circuit including a shift register; each shift The scratchpad includes: The plurality of displacement temporary storage units, each of the displacement temporary storage units receives the two clock signals from the external circuit, and the two adjacent clock buffer signals received by the adjacent temporary memory unit are opposite, and the output signal of the previous displacement temporary storage unit is The input signal of the subsequent displacement temporary storage unit, each of the displacement temporary storage units includes: a signal output circuit that receives the first clock signal from the external circuit, and includes: a first transistor that outputs the first clock And a second transistor that outputs a cutoff signal; a signal input circuit that receives an output signal of the previous displacement temporary storage unit and a second clock signal from the external circuit opposite to the first clock signal, and The first transistor output control signal of the signal output circuit includes: 095149690 Form number Α 0101 Page 23 / Total 31 page 0993409550-0 (3) 9374 10 11 I year η month press Zheng Bo ^ A third transistor, which is always at Turning on, and discharging to the output of the signal input circuit, and keeping its output signal unchanged for one clock cycle; and - logic conversion Receiving an output signal of the signal input circuit and outputting a control signal to control conduction and deactivation of the second transistor; wherein when the signal input circuit inputs a communication number, the communication number turns on the first transistor and the a logic conversion circuit, wherein the first clock signal is outputted through the first transistor, and the logic conversion circuit outputs a load-stop signal to turn off the second transistor; if the signal input circuit inputs the cut-off signal, the The first transistor is turned off, and the logic conversion circuit automatically outputs a communication number, so that the second electro-spinning dance is converted to a decimation signal-J · 7. As described in claim 9, the displacement is temporarily stored. The unit is composed of a plurality of transistors. The liquid crystal display device according to the first aspect of the invention, wherein the transistor is a PMOS type transistor. The liquid crystal display device of claim 1, wherein the input circuit further comprises a fourth transistor and a fifth transistor, and the fifth transistor receives the drain from the external circuit. a low potential signal, wherein the p-pole and the source of the fourth transistor each receive a transmission t-number of the previous displacement temporary storage unit, and a source thereof is connected to a drain of the fourth transistor, the fourth electric crystal The gate of the bone receives the second clock input signal 'the gate name of the third transistor receives the low potential signal' and the drain is connected to the source of the (four) five transistors, and the signal input circuit is output from the source Output signal. The liquid crystal display device of claim 12, wherein the stencil conversion circuit comprises a sixth transistor, a seventh transistor, a _ eighth $ 军军号 A0101 % 94 Έ / Λ -51 s Page 24 of 31 0993409550-0 13 1339374 » I On November 15, 099, the replacement of the page crystal and a ninth transistor, the drain of the sixth transistor receives the low potential signal of the external circuit, and its gate The pole is connected to the drain, the source thereof is connected to the drain of the seventh transistor; the source of the seventh transistor receives the high potential signal of the external circuit, and the gate thereof is connected to the gate of the ninth transistor, The drain of the eighth transistor receives a low potential signal of the external circuit, the gate thereof is connected to the source of the sixth transistor, and the source thereof is connected to the drain of the ninth transistor; the ninth transistor The gate receives the output signal of the signal input circuit, and the drain receives the high potential signal of the external circuit. The liquid crystal display device of claim 10, wherein the shift register unit further comprises a test signal input circuit. The liquid crystal display device according to claim 14, wherein the test signal input circuit comprises a tenth electric/crystal: read, the gate and the source of the tenth transistor. The test 'm number from the external circuit is received, and the signal is output to the logic conversion circuit and the signal output circuit. The liquid crystal display device of claim 1, wherein the signal output circuit further comprises a tenth '-transistor: and a twelfth transistor, the first transistor and the eleventh a crystal father: the pole receives the first clock r signal, the gate receives the input signal of the signal rim coil, and the drains respectively output signals, the second transistor and the gate of the twelfth transistor Receiving the control signal of the logic conversion circuit, the source receives the high potential signal from the external circuit, and the drain is connected to the first transistor and the eleventh transistor. 095149690 Form No. A0101 Page 25 of 31 0993409550-0