TWI336929B - Method for forming semiconductor structure - Google Patents

Description

1336929 IX. Description of the Invention: [Technical Field] The present invention relates to a method of forming a semiconductor structure, and more particularly to a method of increasing a contact window process space to form a semiconductor structure. [Prior Art] Dynamic Ik machine access memory (DRAM, dynamic random access

Memory) has gradually become an important electronic product. There are a lot of memory crystals in the secret age, and they are arrayed to store data. In addition, the _ random access Wei body also includes a peripheral area for controlling peripheral circuits. Each memory cell and peripheral control circuit includes a MOS transistor and other electronic components, such as fS connected in a connected manner. When the capacitor is electrically connected to - (4), the MOS transistor is electrically connected to the word line. The MOS semiconductor crystal system is used to determine the address of the S-resonant unit cell. In order to electrically connect these electronic components, a plurality of connections are formed between different materials, and in the subsequent steps, the conductors are tilted to complete the function of the semiconductor transistor. In the 9 〇nm process, the process of the bit line contact window requires a favorable oxide layer, but it cannot be removed and the structure is ordered. However, the minimum process space affects the short circuit between the bit line connection _ σ and the bit line contact window contact window. This is a problem in size reduction, an easy problem, and a process difficulty. . to make

4NTC/060I7TW; 9312S~TW 5 special two-plus process space, with self-alignment [invention] II in the above-mentioned invention background 'traditional semiconductor structure ^fi-n^Tb(aspectrati〇)^^^ * I# The two are narrowed down, resulting in many disadvantages in the bit line connection. Therefore, the present invention provides a polymer protection gate structure formed on one side, and utilizes θ and a high-to-material ratio between materials to improve the occupation. The purpose of the other is to use the process space of the wet stripped bit line contact window. Flying text. = Embodiments The present invention provides a method for forming a material structure, providing a substrate, forming a plurality of idler structures on the substrate, forming a protective layer on each of the top surfaces of the It I and the sidewalls, forming a The first structure is on the ft-surface and the lamella layer; the formation-embedding in the gate junction hides the structure _ structure, the substrate H plug = the second electrical layer, the cover structure and the plug; and the removal of the plug and the first - total = ^ A contact window is formed with the bare substrate.

4NTC/06017TW; 93I28-TW [Practical Mode] Some embodiments of the present invention will be described in detail below. In addition, the present invention is also widely practiced in other embodiments, and the invention is limited to the trousers of the present invention, as will be the subject of the following. Figures 1 through 9 are schematic views of the steps of forming a semiconductor = method according to the present invention. Referring to the first figure, in an embodiment, first, the substrate 10, and a plurality of gate structures above the substrate 1G = where the substrate H) can be a general recording board, and the insulating layer is turned on the substrate Body substrate. The _ structure 12 on the substrate H) includes a gate dielectric layer (such as a domain oxide layer), an interlayer mto-P〇ly silicon layer, and an N+ doped polycrystalline stone sequentially from the substrate 〇 The eve layer and the cover layer (4) layer) 'The production method is the same as the conventional technology is not praised in this case. Then 'formed on these gate structures 12' - a conformal layer (_〇ιι:) 4, wherein the conformal layer 14 is an oxide layer, which can be formed in a manner that utilizes the low-tetra-ethyl (four) P_ Therefore, the thickness is about 5 (10) ~ 40 nm °. Then, according to the second figure, the method of surname engraving is used to engrave the conformal layer, so that the _ structure 丨 2 ship 122 is shaped with 142 and retains part of the total The layer 14 is on top of the gate structure, that is, this step is selected for the conformal layer 14 on the side substrate 10, while remaining on the top surface of the _ structure 12 and the conformal layer 侧壁4 of the sidewall to become a protective layer. 42. In the present embodiment, the mode of the insect etch includes the reactive ion side (RIE), more specifically

4NTC/06017TW; 93128-TW 7 QF6'QF8' Ar/〇2 ^ conformal ▲ 14 oxidized bis- 〇 2 4) anti-hetero _, and by (as not shown) between and _ (nitrogen) Cut; the brother enters the 々, has the 阙, the ratio, so that when etching, the part of the surface of the substrate 1 的 conformal layer (oxidation, 1; top gate structure 12 sidewall 122 and removed In the gate structure conformal layer 14, and after the etch, a portion of the surface is exposed, that is, the etching step utilizes a polymer which is controlled by the etchant to protect the gate structure. The top surface of the ^^ Temple is the part that protects the top corner of the gate structure 12. It is only slightly etched and retains part of the oxide layer on the top surface of the gate structure 12. It remains after etching. The oxidized layer (4) of the structure 12 and the contact layer can be used as a protective layer of the contact structure 12, which is advantageous for increasing the process space of the subsequent meal. In this embodiment, after the step of characterization, the remaining structure is closed. The thickness of the oxide spacer 142 on the side wall 122 is about 15 m to 20 nm, and the thickness of the oxide layer on the top surface is about 15 nm to 2 〇 nm. Next, on the substrate 10 A first conformal layer 16 is formed on the surface and protective layer 142, which has a high etching selectivity ratio with the protective layer 142. The material of the first conformal layer 16 includes, but is not limited to, for example, aluminum sulphide (8), and ς The formation can be atomic layer deposition (ALD), and the deposited thickness is about 8 nm. Here, the purpose of forming the first conformal layer 16 is to serve as a sacrificial layer, and the improvement is to improve the bit line contact (CB) process* so that in the subsequent steps, the bit line contact window is formed. In the case of 4NTC/06017TW; 93128-TW 8 1336929, the general wet stripping step (Wet strip) replaces the dry etching step in the current process. On the other hand, the purpose of forming the first conformal layer 16 is to form a bit line window without the need for an additional reactive ion etching step. Next, referring to the third figure, a polysilicon layer 20' is formed on the first conformal layer 16. The polysilicon layer 2' may be an undoped polysilicon layer which is formed to have a thickness of about 720 nm to 880. Next, a planarization step, such as chemical mechanical polishing (CMp), is performed on the polysilicon layer 2〇/on, so that the surface of the polycrystalline layer 2较为 is relatively flat, and the residual polycrystalline layer 2〇 has a thickness of about 3 (8) nm to 400nm. It is to be noted that the planarization step is an optional execution step 'if the surface of the deposited multi-layer 2G is sufficiently flat', no additional planarization step is required. The flattening step is for the subsequent process of the towel, which can be sieved as the nitriding layer 22 of the nitrite layer (4) into the polycrystalline lining 2 〇 ±. Further, in the present embodiment, the method of forming the hard mask layer 22 may include a thickness of about 60 nm to 70 nm deposited by a CVD vapor deposition method (PECVD). Then, please refer to the fourth figure. First, a patterned photoresist is formed on the structure of the third figure to define a plug (that is, a pattern defining a subsequent contact window), and a portion of the hard mask layer 22 is removed after the absence. The portion of the hard mask layer 22 that remains patterned is retained on the polycrystalline layer 20. In this embodiment, the etchant of the hard mask U is comprised of CF4/CHF3/〇2, and the side secret can be used to obtain a straight (4) (not indicated by the ® towel). Then, the hard mask layer 22 patterned by 4NTC/06017TW; 93128-TW 9 is used as a mask, and the unprotected polysilicon layer 20 is etched with HBr/He/〇2 as an etchant, so that the gate structure is The 丨/between electric shape f 202 also exposes a portion of the first conformal layer 16. The idea here is that 'because of the high etching selectivity between the polycrystalline layer 20 and the first conformal layer 16, the polycrystalline germanium layer 2 etches during etching without the first conformal Layer 16 has too much impact.曰 Next, referring to the fifth figure, after forming the plug 2〇2, the hard mask layer 22 on the plug 202 is stripped, and at the same time as the stripping, the portion of the first conformal layer 16 will also be exposed. - and remove. The method of removal is by using a wave: about 80% phosphoric acid (h3P〇4) and stripping at a temperature of about 16 〇〇c. In this step, the selectivity of each layer is used to obtain the selectivity of the singularity. For example, the first conformal layer (Al2〇3) i6 etch rate is about 1 () 2 A per minute. The hard mask layer (the rate of enrichment of tantalum nitride 2 is about 53 A per minute, and the side rate of the listening layer (oxide layer) 142 is about 2 people per minute. Meanwhile, the concentration is about 8〇%_ The acid (Hf〇4) Thai J except the hard mask layer 22 and the first conformal layer have the same side ratio to the substrate, especially the higher the cost ratio. Therefore, the substrate can be The first conformal layer 16 exposed on the 10 is completely removed. In this step, a few layers 142 are also placed above the interpole structure 12, especially in the corners (deleted portions, but due to the protection of S3) Role without affecting the integrity of the entire interpole structure 22

4NTC/060I7TW; 93128-TW 10 1336929 (4) The known formation method, in the fifth layer barrier layer (4), the material can be nitrogen cut, 2 = m to 丨 = here _ is, in the deposition second A total of 择 择 先 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积Figure 7, in the structure of the sixth figure, except for the part of the 3G, part of the singular mf grinding to move the protective layer 24 (if formed). The first conformal layer 26 and part of the extra 3 In the eighth figure, the self-alignment method is used, for example, the isotropic 3 =0=/tc thief and the SIV 〇 2 is used as the engraving gas, and the embolization (the sap layer) 202 ' is removed to expose the part. The second conformal layer 16. Since the etch=body-to-dielectric layer (BPSG) 30, the first conformal layer 16 and the additional protective layer 24 have a very south side selection ratio, only the embolic loading will be removed, That is, 'Using each layer _ high _ selection ratio, no _ fine outer mask is ^ self-aligned effective surname engraved 202. Then, refer to the ninth figure, use

4NTC/06017TW; 93128-TW 11 1336929 The first conformal layer 16 exposed by phosphoric acid stripping at a concentration of about 80% exposes the substrate 10 to form a contact window 32. Here, the condition of stripping the hard mask layer 22 on the plug 202 in the previous step of the fifth figure is similar, and the etching selectivity is achieved by using different etching rates between the layers of materials. In this embodiment, the phosphoric acid (H3P〇4) having a concentration of about 80% is used, and the stripping is performed at a temperature of about 1 thief, wherein the first conformal layer has a rate of 1 G2 per minute. The mask layer 22 has a rate of about 53 people per minute, and the additional protective layer 24 has an etch rate of about 2 people per minute. Here, the first conformal layer is stripped with phosphoric acid (Η^Ο4) having a concentration of about 80%, and the substrate 10 has a high etching selectivity ratio, especially for the germanium substrate. Therefore, the first conformal layer 16 exposed by the eighth figure can be completely removed to expose the substrate 1 to form a contact window %. Therefore, according to the above description, in the conventional 9 〇 nm semiconductor structure, the polymer-preserved pole structure formed by the butterfly is more utilized by the conformal layer 16 and the high cost ratio between materials. Improving the contact window (4) When the contact window can be removed, a wet strip is used to replace the dry paste step in the current semiconductor structure process. In other respects, the dielectric layer 30 is protected without the need for an additional reactive ion etch step or additional masking by forming the first layer 16' when forming the bit line contact. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

4NTC/06017TW; 93128-TW 12 1336929 are to be included in the scope of equivalent changes or modifications made under the application spirit described below. BRIEF DESCRIPTION OF THE DRAWINGS Intent == Figure to the ninth circle, according to the technique disclosed in the present invention, the steps of improving the processing space of the bit line contact window by using the sinking conformal layer are shown. [Main component symbol description] 10 Substrate 12 Gate structure 14 conformal layer 122 sidewall 142 protective layer 16 first conformal layer 20 polysilicon layer 22 hard mask layer 202 embolic 24 additional protective layer 26 second conformal layer 30 dielectric layer 32 contact window 4NTC/06017TW; 93128-TW 13

Claims (1)

1336929 X. Patent Application Range: L - A method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of gate structures on the substrate; forming a protection on a top surface and a sidewall of each of the gate structures Forming a first conformal layer on a surface of the substrate and the protective layer; forming a plug between the gate structures; removing the first portion of the gate structure not covered by the plug a conformal layer; ^# forming a second conformal layer on the gate structures, the surface of the substrate, and forming a dielectric layer to cover the gate structures and the plug; and # removing the plug And the first conformal layer, the method of forming a semiconductor structure according to the first aspect of the patent, wherein the step of forming the protective layer comprises: forming a conformal layer to include the gates The substrate of the pole structure; and the conformal layer removed on the wire of the female board, the green polymer protects the conformal layer on the gate structures, and covers each of the gate structures The top surface and the protective layer of the sidewall. θ / is 3. The method of forming a semi-conductor as described in claim 2, wherein the film is removed on the wire. 4. The method of forming a semiconductor structure as described in the patent specification (4), 4NTC /06017TW; 93128-TW 14 The conformal layer has a high etching selectivity ratio, and the protective layer is an emulsion layer and the dichroic layer is trioxide. i 中利辜! The method of forming a semiconductor structure described in Item 1, 丨; two =; layer method includes _ atomic layer earning (four) her method of finding the structure of the material, a little semi-guided in i a listening method, covering the substrate including the gate structures; forming a germanium layer on the polysilicon click. The photoresist is formed on the layer; and the layer is formed on the layer And the patterned photoresist is a mask, and the patterned nitride is removed in the remaining layer of the nitride layer and the polycrystalline stone. 8. As described in item 7 of the scope of the patent application, the method of flattening the money is to be carried out in a bare way. 9. The shape described in the patent application is further included before the second conformal layer of the shaft. Axis - Method of additionally protecting f's method of forming a semiconductor structure as described in the patent application scope, 4NTC/06017TW; 93128-TW 15 ^36929 The step of removing the plug is a self-alignment step. The method of forming a body structure, such as the forming of the first aspect of the invention, wherein the forming of the electrical layer comprises: depositing the dielectric layer into h; and heat treating the dielectric layer by the second conformal layer β; Removing a portion of the dielectric layer and located at the plug Forming a half as described in the scope of the patent application section wherein the heat treatment utilizes a reflux method. The method of the conductor structure, the method of the invention is a method for the structure of the conductor of the age of the U, and the chemical electric layer and the second conformal layer located on the plug are required to form the first A semi-characteristic method, wherein the dielectric layer is borophosphorus bismuth glass (BPSG). 4NTC/06017TW ; 93128-TW 16