.1332626 ·. * 九、發明說明： ^ ..二 >» .〆· - 【發明所屬之技術領域】 本發明屬於計算機架構（compUter archi tecture)之領 域’是針對處理器（processor)中的分支目標緩衝器（βΤβ)，提 出減少目標位址欄位（target address field)位元個數的方 - 法。 【先前技術】 分支目標緩衝器（BTB)是用來儲存分支指令（branch instructi〇n)的目標位址（target address) ’並常被利用來判 • 斷是否為分支指令，如果某一指令已被認定為分支指令，再由 分支預測器（branch predictor)根據此分支指令跳躍的歷 史’來判斷此分支指令是否會躍（taken or not)，若分支預 測器預測執行方向改變並非循序執行，則由分支目標緩衝器的 目標位址攔位（target address field)提供目標位址，讓程式 繼續執行下去。 而一般的作法是目標位址欄位直接儲存全部的位元，可以 參考圖1。 【發明内容】 • 本發明提出一個新方法，讓分支目標緩衝器（BTB)之目標 ，址欄位（target address field)，不需要儲存目標位址的全 部位元’而是儲存本發明設計的偏移目標(〇ffset target)， 且產生32位元的目標位址（target address)的過程，不會增 加時間延遲。 利用較少的位元數，達成相同功能，可以降低晶片的面 積’也更省電。以32位元MIPS指令集為例，利用此方法每一 個目標位址棚位（target address field)，可以減少15個位 元，也就疋原本需要儲存32個位元，使用本發明只需要儲存 17個位元」減少了 46· 88%。再以32位元ARM指令集為例利 用此方法母一個目標位址欄位（target address f ieid)，可以 5 1332626 Π Μ ... • - , · 減少7個位元，也就是原本需要儲存32個位元，使用本發明 只需要儲存25個位元，減少了 21. 88%。任何指令集都可以適 用本發明，不_指令集可以節省的最大位元個數也不同。 以512-entry的分支目標緩衝器（ΒΤΒ)為例，若是％位元 MIPS指令集總共可以減少刪個位元，32位元纖指令集總 共可以減少3584個位元。64位元或是更高位元的架構，應該 可以節省更多位元。 如果分支目標緩衝器（BTB)的entry數目越多，可以省得 位元個數也會越多，但本發明增加的電路卻是固定的。不過 entry數目小於16，可能就不適用本發明了。 本發明為一種節省分支目標緩衝器（BTB)的目標位址欄位 之位元個數的方法，包括： (a) 不儲存目標位址的全部位元，而儲存位元個數較少的偏移 目標（Offset target) ’偏移目標分成三個部分，目標位 址之變動範圍、進位位元（carry bit)、減/加位元 (Sub/Add bit) 〇 (b) 增加兩個功能單元，使在查（L〇〇k叩）分支目標緩衝器 (BTB)的同時’對分支指令位址之變動範圍以上的部分做 加及減的運算。 其中（a)部分中的偏移目標的目標位址之變動範圍的位元 個數並不一定，為指令集的分支指令格式的偏移量之欄位之位 元個數減去符號位元’若偏移目標的目標位址之變動範圍多儲 存幾個位元，相對地，兩個對指令位址之變動範圍以上的部分 做加及減的功能單元’所運算的位元個數即可減少幾個位元。 其中（b)部分對分支指令位址之變動範圍以上的部分做加 及減的運算’也可以用加法器（Adder)或計數器（c〇unter)來達 成。 本案的目的是提供一種節省分支目標緩衝器（BTB)的目標 位址欄位之位元個數的方法，可使用較少的位元個數產生出完 6 整的目標位址，並且沒有效能損失。 【實施方式】 本發明利用分支指令位址與目標位址有部分相似的部 分’兩者相似的部分就不儲存在分支目標緩衝器（BTB)中，利 用這一點來達到減少目標位址攔位（target address field) 的位元個數，至於兩者相似之部分為何，就要從指令集的分支 指令格式來說明。 圖2為32位元MIPS指令集的分支指令格式、圖3為32 位元ARM指令集的分支指令格式，以下例1為32位元mips指 令集分支指令的跳躍範圍說明，例2為32位元ARM指令集分 支才曰令的跳躍範圍說明。由這兩例子可以知道分支指令跳躍的 距離是有固定範圍的，偏移量（offset)的值會受到限制，而且 不同指令集的分支指令跳躍範圍也不盡相同。 例1 : BNE R3, R4, name if (Regs[R3]!=RegS[R4]) PC name; ((PC+4)-217) <= name < ((PC+4)+217) 例2 : name;.1332626 ·. * IX. Description of the invention: ^..2>». 〆· - Technical Field of the Invention The present invention belongs to the field of computer architecture (compUter archi tecture), which is directed to a processor. The branch target buffer (βΤβ) proposes a method of reducing the number of bits in the target address field. [Prior Art] The branch target buffer (BTB) is used to store the branch address of the branch instruction (branch instructi〇n) and is often used to determine whether the branch instruction is a branch instruction. Is determined as a branch instruction, and then the branch predictor determines whether the branch instruction will take or not according to the history of the branch instruction jump. If the branch predictor predicts that the execution direction change is not sequential execution, then The target address is provided by the target address field of the branch target buffer, allowing the program to continue. The general practice is to store all the bits directly in the target address field. See Figure 1. SUMMARY OF THE INVENTION The present invention proposes a new method for the target of the branch target buffer (BTB), the target address field, without storing all the bits of the target address, but storing the design of the present invention. The process of offsetting the target (〇ffset target) and generating a 32-bit target address does not increase the time delay. By using fewer bits to achieve the same function, the area of the wafer can be reduced and power is saved. Taking the 32-bit MIPS instruction set as an example, each target address field can be reduced by 15 bits by using this method. In other words, 32 bits need to be stored, and the invention only needs to be stored. The 17-bit is reduced by 46.88%. Taking the 32-bit ARM instruction set as an example, this method uses a target address field (target address f ieid), which can be 5 1332626 Π Μ ... • - , · Reduces 7 bits, that is, it needs to be stored. With 32 bits, using the present invention requires only 25 bits to be stored, a reduction of 21.88%. The present invention can be applied to any instruction set, and the maximum number of bits that can be saved without the instruction set is also different. Taking the 512-entry branch target buffer (ΒΤΒ) as an example, if the %bit MIPS instruction set can reduce the number of bits in total, the 32-bit fiber instruction set can be reduced by a total of 3584 bits. A 64-bit or higher-bit architecture should save more bits. If the number of entries in the branch target buffer (BTB) is larger, the number of bits can be saved, but the circuit added by the present invention is fixed. However, the number of entries is less than 16, and the invention may not be applicable. The invention is a method for saving the number of bits of a target address field of a branch target buffer (BTB), comprising: (a) not storing all the bits of the target address, and storing the number of bits less Offset target 'The offset target is divided into three parts, the range of the target address, the carry bit, the Sub/Add bit 〇(b) adds two functions. The unit is used to add and subtract the portion above the range of the branch instruction address while checking (L〇〇k叩) the branch target buffer (BTB). The number of bits in the range of the target address of the offset target in part (a) is not necessarily the number of bits in the field of the offset of the branch instruction format of the instruction set minus the sign bit 'If the range of the target address of the offset target is more than a few bits, the number of bits calculated by the two functional units that add or subtract to the part above the range of the change of the instruction address is Can reduce a few bits. The part (b) in which the addition and subtraction of the portion above the range of the branch instruction address can be used by an adder or a counter (c〇unter). The purpose of this case is to provide a method for saving the number of bits in the target address field of the branch target buffer (BTB), which can generate 6 target addresses with fewer bits and has no performance. loss. [Embodiment] The present invention utilizes a portion where the branch instruction address is partially similar to the target address, and the similar parts are not stored in the branch target buffer (BTB), and the point is used to reduce the target address block. The number of bits in the (target address field), as to the similarity between the two, is explained from the branch instruction format of the instruction set. Figure 2 shows the branch instruction format of the 32-bit MIPS instruction set, and Figure 3 shows the branch instruction format of the 32-bit ARM instruction set. The following example 1 shows the jump range of the 32-bit mips instruction set branch instruction. Example 2 is 32-bit. The description of the jump range of the meta-ARM instruction set branch. From these two examples, it can be known that the distance of the branch instruction jump has a fixed range, the value of the offset is limited, and the branch instruction jump range of different instruction sets is also different. Example 1: BNE R3, R4, name if (Regs[R3]!=RegS[R4]) PC name; ((PC+4)-217) <= name < ((PC+4)+217) 2 : name;
_ name if (Z set) PC ((PC+8)-225) <= name < ((PC+8)+225) 人例3是一個位元個數較少的簡單例子，以32位元Mips指 々集為例’兩個位元個數不相同的二進制數字相加，其中 量之正數最大，case2為偏移量之負數最小「相加之前 移置的值需要先左移（shift)兩個位元，而空出來的兩個位 =的值’直接設定為〇，因為偏移量的位元個數較少，所以還 需要做符號延伸(sign extended)才能與『分支指令位址+4 =加法運算’而運异結果即為目標位址。其中偏移量的變動範 圍以上部分’最右邊的位元是偏移量的符號位元，其餘為符號 1332626_ name if (Z set) PC ((PC+8)-225) <= name < ((PC+8)+225) Person example 3 is a simple example with a small number of bits, with 32 bits The meta-Mips refers to the 々 set as an example of 'two binary numbers with different number of digits added, where the positive number is the largest, and case 2 is the least negative of the offset. The value of the displacement before the addition needs to be shifted first (shift) Two bits, and the value of the two empty bits = 'set directly to 〇, because the number of bits of the offset is small, so you need to do sign extension to "branch instruction bit" The address +4 = addition operation 'and the result of the difference is the target address. The part above the range of variation of the offset 'the rightmost bit is the sign bit of the offset, and the rest is the symbol 1332626
p月Μ日修正替換貝j 延伸（sign extended) » 例3 : 符號位元 1 變動範園 1011 110000 分支指令位址 + 0000 111100 偏移量 > Case 1 1100 101100 目標位址 v 1011 110000 分支指令位址 + 1111 000000 偏移量 ^ Case 2 1010 110000 目標位址 yCorrection replacement p extension (peg extension) Example 3: Symbol bit 1 Change Fan Park 1011 110000 Branch instruction address + 0000 111100 Offset > Case 1 1100 101100 Target address v 1011 110000 Branch instruction Address + 1111 000000 Offset ^ Case 2 1010 110000 Target Address y
由此可知，如果有触產生，會造細者之變誠 的部分有加1或減1的差異，若沒有進位則相同。 將分支指令位址與目標位址來拿一起做比較，可見 圖5 ’分支指令位址與目標位址的差異主要是在變動範圍的邻 分，而目標位址之變動範圍以上的部分，若沒有進位會與原^ 分支指令位址相同，若有進位，則會有加2或減丨的變化''。From this, it can be seen that if there is a touch, the difference between the part that becomes finer is increased by 1 or minus 1, and the same is true if there is no carry. Compare the branch instruction address with the target address. It can be seen that the difference between the branch instruction address and the target address in Figure 5 is mainly the neighbor of the variation range, and the part above the variation range of the target address, if No carry will be the same as the original ^ branch instruction address, if there is a carry, there will be a 2 or minus change ''.
另外byte of f set這部分是不會改變的（因為pc每次 4)，所以只需要儲存變動範圍再加上兩個額外的位元，用來^ 錄有無進位以及是做加或減調整的動作，即可利用這些部分^ 生出32位元的目標位址（32-bit target addi*ess)。 本發明適用於各種指令集的分支目標緩衝器（ΒΤβ)，以下 說明全部都以32位元ARM指令集為例，其他指令集同理，在 本發明中，使用偏移目標(offset target)取代了原本儲存在 分支目標緩衝器（BTB)中的32位元目標位址，偏移目標的格式 請參考圖6 ’其中目標位址之變動範圍這個部分很明^ 再說明。 ‘ 進位(Carry)這個位元是判斷有無進位到目標位址之變動 8 ^ Μ 較分支指令位址與目標位址的第31位 το到第25位元，這之間的每一個位元，若有某一個位 ^ 則判斷結果就是有進位，_ 6中進她元的計算 ° 是判斷這兩部分的每—餘元有無鱗的作法 ^ ，，為0，表示沒有進位，若不相等騎錄位 表不有進位，而減/加(Sub/Add)這個位元，則是依昭原分皮 令的偏移量為正數或負數來決定，若是正數則、、0原^ =以:來是說明如何利用偏移目標得龍位2 target address[24:2] = offset target[24：2]In addition, the byte of f set will not change (because pc is 4 each time), so you only need to store the range of variation plus two extra bits, which are used to record whether there is a carry and whether to add or subtract. Action, you can use these parts to generate a 32-bit target address (32-bit target addi*ess). The present invention is applicable to branch target buffers (ΒΤβ) of various instruction sets. The following description all takes the 32-bit ARM instruction set as an example, and other instruction sets are similar. In the present invention, an offset target is used instead. For the 32-bit target address originally stored in the branch target buffer (BTB), please refer to Figure 6 for the format of the offset target. The part of the target address is very clear. 'Carry' bit is to determine whether there is a carry-to-target address change 8 ^ 较 compared to the branch instruction address and the target address 31st το to the 25th bit, each bit between, If there is a certain bit ^, the result of the judgment is that there is a carry, and the calculation of the _ 6 into her yuan is to judge whether each of the two parts has a scale of ^, and is 0, indicating that there is no carry, if not equal riding The location table does not have a carry, and the Sub/Add bit is determined by the positive or negative offset of the Zhaoyuan splitting order. If it is a positive number, 0 is ^^ to: To illustrate how to use the offset target to get the dragon position 2 target address[24:2] = offset target[24:2]
If (( Carry == 1 ) M ( Sub/add == 1 ))* target address[31:25] = pc[31：25] - l； else if (( Carry == 1 ) M ( Sub/add == 〇 )’) target address[31:25] = pc[31：25] + l； else ’ target address[31:25] = pc[31：25]； target address[l:0] = pc[l：〇]； ’ 圖7為一般的分支目標緩衝器（BTB)的讀取過程，其過程 土致為先解碼(decode)選出要讀SRAM的哪一個集合(se^)，再 2出在SRAM所對應集合中的每一筆資料，比較各筆資料的標 籤（tag)，在依照標籤比較之後的結果，用多工器選出我們^ 正要讀取的目標位址，之後就將目標位址送到Npc(Next pc)。 本發明對目標位址之變動範圍以上的部分，做加丨與減 1運算之調整需在比較標籤（tag)之前做完，這樣子的作法沒 ^増加時間延遲（time delay)。圖8、圖9、圖10為本發明的 ，取32位元目標位址的作法，圖8說明了本發明讀取分支目 標緩衝器（BTB)的過程’在一開始用指令位址去查〇〇〇k叩） 分支目標緩衝器（BTB)時，同時也將指令位址送到「指令位址 [31:25]+1」與「指令位址[31:25]-1」，這兩功能單元對指令 1332626 位址[31:25]部分執行加ι與減ι的運算，且將運算結果輸入 回分支目標緩衝器（ΒΤΒ)。 圖9說明，一開始先依據進位與減/加這兩個位元，選擇 目標位址之變動範圍以上的部分（目標位址[31:25])，再盥目 標位址之變動範圍（目標位址[24:〇])合併’其中目標位;止的 第〇個位元與第1個位元的值，直接設定為〇。然後由標籤（tag) 比較的結果，從集合（set)中選擇某一個要讀取的目標位址 輸出，即為此分支指令所對應的32位元目標位址（32 bit target address) ° 圖10為#曰令位址[31:25]+1」功能單元的内部電路，各 個位元的運算都是獨立的，而且運算時間並不長，可以在預定 時間内做完，圖11與圖1〇同理，不過是執行減丨的運算。 本案之圖式、元件符號或名詞定義可參考如下： 1. 目標位址（target address)為分支指令（branch instruction)跳躍的目的地位址。 2. 指令位址[31:25]的意思為32位元的指令位址中的第25位 元到第31位元，總共有7個位元，其餘以此類推。 3. 分支目標緩衝器（BTB ; Branch Target Buffer)為存放分支 指令對應的目標位址。 4. MIPS指令集之分支指令格式中的攔位與arm指 令集之分支指令格式中的offset攔位的值就是本發明提到 的偏移量(offset)。 5·偏移目標(〇f fset target)為本發明用來取代32位元目標位 址’儲存在分支目標緩衝器中，以此來達到降低儲存的位元 個數。偏移目標的總位元個數為變動範圍的位元數再增加2 個位元。 6. 分支預測器（branch predictor)，根據分支指令的跳躍歷 史’來判斷此分支指令是否會跳躍（taken or not)。 7. 變動範圍為分支指令位址與目標位址比較的主要差異部分， 10 日修正替換 ^'—~~-__ί 根據本發明的設計’變動範圍的位元個數為指令集之分支指 令格式(branch instruction format)中的偏移量之攔位位 元個數減去符號位元（sign bit)。If (( Carry == 1 ) M ( Sub/add == 1 ))* target address[31:25] = pc[31:25] - l; else if (( Carry == 1 ) M ( Sub/add == 〇)') target address[31:25] = pc[31:25] + l; else ' target address[31:25] = pc[31:25]; target address[l:0] = pc[ l:〇]; ' Figure 7 is the general branch target buffer (BTB) read process, the process is to decode first (decode) select which set of SRAM to read (se ^), then 2 out Each piece of data in the set corresponding to the SRAM compares the tags of each piece of data. After the comparison according to the tags, the multiplexer selects the target address that we are going to read, and then the target address. Send to Npc (Next pc). In the present invention, the adjustment of the addition and subtraction operations of the part above the target address range needs to be done before the comparison tag (tag), so that the method does not increase the time delay. 8 , FIG. 9 and FIG. 10 are diagrams showing the operation of taking a 32-bit target address, and FIG. 8 illustrates the process of reading the branch target buffer (BTB) of the present invention. 〇〇〇k叩) When branching the target buffer (BTB), the instruction address is also sent to "instruction address [31:25]+1" and "instruction address [31:25]-1". The two function units perform the operations of adding and subtracting the instruction part 1332626 address [31:25], and input the operation result back to the branch target buffer (ΒΤΒ). Figure 9 illustrates that, starting from the two bits of carry and subtract/add, the part above the range of variation of the target address (target address [31:25]) is selected, and then the range of the target address is changed. The address [24:〇]) merges with the target bit; the value of the first bit and the first bit is directly set to 〇. Then, by the result of the tag comparison, a target address output to be read is selected from the set, that is, the 32-bit target address corresponding to the branch instruction (32 bit target address) 10 is the internal circuit of the #曰令 address [31:25]+1" function unit, the operation of each bit is independent, and the operation time is not long, and can be completed within a predetermined time, Figure 11 and Figure The same is true, but it is the operation of performing the reduction. The schema, component symbol or noun definition of this case can be referred to as follows: 1. The target address is the destination address of the branch instruction jump. 2. The instruction address [31:25] means the 25th bit to the 31st bit in the 32-bit instruction address, for a total of 7 bits, and so on. 3. Branch Target Buffer (BTB) is the destination address corresponding to the branch instruction. 4. The value of the offset block in the branch instruction format of the branch instruction format of the MIPS instruction set and the branch instruction format of the arm instruction set is the offset (offset) mentioned in the present invention. 5. The offset target (〇f fset target) is used in the present invention to replace the 32-bit target address 'stored in the branch target buffer, thereby achieving the number of bits of reduced storage. The total number of bits of the offset target is increased by 2 bits for the number of bits in the range of variation. 6. The branch predictor determines whether the branch instruction will take or not based on the branch history of the branch instruction. 7. The range of variation is the main difference between the branch instruction address and the target address. The 10th correction replaces ^'-~~-__ί. According to the design of the present invention, the number of bits in the variation range is the branch instruction format of the instruction set. The number of intercept bits of the offset in the branch instruction format minus the sign bit.
8. byte offset為指令位址的第〇個位元與第ί個位元，在32 位元指令集中是固定不會變動的部分，而如果是64位元指 令集byte offset則會有3個位元是不會變動的。（本發明 舉的位元例子都是從〇開始） X 9·示意圖中，如果線與線之間有圓點，表示兩條線有互相連 接’右沒有圓點’表示兩條線沒有互相連接。 雖然本發明已以較佳實施例揭露如上’然其並非用以限定 本發明，任何熟習此技術者，在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 田 【圖式簡單說明】 圖1 圖2 圖3 圖4 圖5 圖6 圖7 圖8 圖 S知的分支目標緩衝器（conventi〇nai btb)之示意圖。 32位元MIPS指令集的分支指令格式之示意圖。心θ 32位元ARM指令集的分支指令格式之示意圖。 MIPS指令集的分支指令位址與目標位址比較之示意圖。 ARM指令集的分支指令位址與目標位址比較之示g圖。 ARM指令集的偏移目標(〇ffset target)格式之示音、圖。 習知的分支目標緩衝器（BTB)讀取時間之示意圖Γ 本發明的分支目標緩衝器（BTB)具體實施例之示意圖。 9 :本發明的分支目標緩衝器（BTB)第二具體實施例^示意 圖ίο:本發明的指令位址[31:25]+1功能單元的内部電路之示 意圖。 /' 圖11:本發明的指令位址[31:25]-1功能單元的内部電路 意圖。 μ 【主要元件符號說明】8. The byte offset is the third bit and the twth bit of the instruction address, which is fixed in the 32-bit instruction set, and there are three in the 64-bit instruction set byte offset. Bits are not subject to change. (The examples of the bits in the present invention are all starting from 〇.) In the schematic diagram, if there is a dot between the line and the line, it means that the two lines are connected to each other. 'There is no dot on the right', indicating that the two lines are not connected to each other. . While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. Field [Simple diagram of the diagram] Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Schematic diagram of the branch target buffer (conventi〇nai btb). Schematic diagram of the branch instruction format of the 32-bit MIPS instruction set. Schematic diagram of the branch instruction format of the heart θ 32-bit ARM instruction set. Schematic diagram of the comparison of the branch instruction address of the MIPS instruction set with the target address. The g map of the branch instruction address of the ARM instruction set compared with the target address. The sound and map of the offset target (〇ffset target) format of the ARM instruction set. A schematic diagram of a conventional branch target buffer (BTB) read time. A schematic diagram of a specific embodiment of a branch target buffer (BTB) of the present invention. 9: Branch Object Buffer (BTB) of the present invention. Second Embodiment FIG. 1 is an illustration of the internal circuit of the instruction address [31:25] +1 functional unit of the present invention. /' Figure 11: The internal circuit intent of the instruction address [31:25]-1 functional unit of the present invention. μ [Main component symbol description]