TW486618B - A low-power instruction decoding method for microprocessors - Google Patents

Abstract

The present invention relates to a low power instruction decoding method for microprocessors, employing extraction of statical instruction and instruction decode lookaside buffer (I-DLB) to lower the system power. The invention is characterized to comprise; the first step of extracting a statically extracted set (SES), in which a small number of instructions are fetched most frequently during executing application programs at the stage of microprocessor design simulation, and in which bits the instructions cause power consumption resulting from logic transitions in the instruction decoder; the second step of comparing an instruction read from the memory to the SES extracted in the first step; the third step of holding the signal connected to the instruction decode lookaside buffer (I-DLB) to prohibit a logic transition in the instruction decoder, if the instruction in the second step is determined to correspond to the SES, and of extracting signals that require no decoder logic transitions from the instructions by generating the control signal stored in the I-DLB assuming the form of read only memory (ROM); and the fourth step of disabling the I-DLB, if the instruction in the second step is determined not to correspond to the SES, and of performing a normal instruction decoding process by replacing the signal connected to the I-DLB with the same value as the instruction read form the memory.

Description

486618 V. Description of the invention (1) ----- The present invention refers to a low-power instruction _ k processor system to perform instruction decoding process ^ 2 method 'in order to use micro-type static instruction using micro-processing' invitation , Its power loss: especially (I-DLB) to reduce the system power of the micro-processing two instruction decoding look-aside buffer method. & Decoding with low-power instructions Recently, the demand for portable information access products such as portable audio generators, mobile phones, and personal digital assistants (PDAs) has been increasing, and some people have tried to find ways to extend The life of these products. However, because it is difficult to reduce the size of large-capacity batteries, technology has been developed in the direction of reducing the power loss of internal components. Since the microprocessor accounts for a large part of the total power loss of the internal components, some manufacturing techniques have been proposed to reduce the processor power loss. _ For example, at the upstream design level, some people have proposed to implement one, ^ The widely used 32-bit program has no restrictions on the execution of the ^ 'Three 7-bit code reduced to 16-bit THUMB instructions, Or implement an instruction set that reduces frequency and reduces power loss. In the circuit ten times, a low-power strategy has been developed that reduces or eliminates unnecessary avoidance conversions in useless areas in the microprocessor by virtue of static CMOS (complementary metal half f,) electrical timing schemes. Although the instructions of the 32-bit microprocessor are composed of 32-bit microprocessors, the THUMB instructions described above are used in 32-bit microprocessors. Therefore, the method of reducing the power consumption of the THUMB instruction is to reduce / lower the memory access frequency, because a program coded with 16 bits occupies less memory than a 32-bit program.

486618 V. Description of the invention (2) However, from the perspective of memory access frequency, although the THUMB instruction can reduce power, because the internal decoding circuit converts 6-bit to 32-bit, it will add extra Complexity, so the microprocessor using the THUMB instruction has a higher power loss than a normal 32-bit decoder. As a result, if the central processing unit (CPU) is designed to reduce the power of all instructions, then for some commonly used applications, this conventional technique cannot be advanced-further reducing power consumption. Therefore, in order to reduce power The 'loss' may have to be trial-and-error simulated and the instruction decoder redesigned from the beginning. The first figure is a schematic diagram of each block inside a general microprocessor. Referring to the first figure of y, an instruction read from the memory (1) is decoded in the instruction decoding (2) block, and then converted into a required one in the data path (3) of the subsequent block. Control signal. At this step, the circuit in the instruction decode (2) will cause many logic transitions, thus causing power loss. The chart of the first figure shows the analysis results of the power loss of a general microprocessor proposed in "IEEE Micro Publication, page 18, July / August 1997", which shows a microprocessor The percentage of power consumed by various applications running on the Internet. Referring to the second figure, the total system clock conversion accounts for 43% of the power loss, the arithmetic logic unit (ALU) power consumption accounts for 22%, and the instruction decoding block power loss accounts for 15%. Therefore, it is advisable to minimize the instruction decoding (2) block, as well as the system clock conversion and the power loss of the ALU. The chart in the third figure shows the "Computer Architecture A Quantitative Approach" by John L. Hennessy and David A. Patterson et al., Second Edition, 105

486618 V. Description of the Invention (3) page, 1996, Morgan Kaufmann Publishing Company "Analysis results of the frequency of an instruction set used to execute various applications on a microprocessor, which shows that the intensive period during the actual execution of the program Take the trend of several specific instructions. Referring to the third figure, specific instructions like data load, conditional branch, add, compare, and store are used intensively. In other words, because lightweight products using low-power microprocessors are used for specific purposes, certain specific applications are often used, so the frequency trend closely matches the typical results in the third figure. The fourth diagram is a schematic diagram of a method for extracting an S E S. In general, in the design phase of low-power microprocessors for lightweight systems, instruction sets, compilers, and various applications are mostly determined. Therefore, the instructions obtained by compiling various applications during the design phase are simulated by an instruction set simulator (Is S) to analyze performance and verify operations. Measure the use frequency of the instruction set to select the most commonly used instruction group, and then select and store only the parts that require heavy logical conversion in a few instruction bits. This is called "static extraction instruction set (SES). " Because the rest of the instruction decoding circuit that does not require logic conversion is not stored, the transistor area and power required to store the SES are minimized. In other words, refer to the instruction shown in the fourth, because R 1 and R 2 are binary values representing the number of registers in the microprocessor, and they are also directly transferred to the register file in the decoding step, so no logic is required Conversion.

486618 V. Description of the invention (4) On the other hand, since the bits extracted to SES need to be transformed into the control signals used by the data path (3) in the first figure, the power will be caused by the heavy logic conversion of the decoding process. loss. As a result, S E S can be used to increase the speed of program execution in general microprocessors. This plan of fetching instructions at the design stage before executing the microprocessor chip is compared with a dynamic plan of dynamically fetching and storing instructions while executing a program. The fifth figure is a block diagram showing the structure of an instruction decoding block using SES extraction and an instruction decoding look-aside buffer (I_DLB). Refer to the fifth figure, which shows two separate blocks, one for extracting SES and the other for I-DLB. First, in the SES extraction block, a command read from the memory will be compared with the SES determined by simulation. If the command is determined to be consistent with the SES, the signal connected to the I-DLB will be Reserved to prohibit logic conversions in the instruction decoder. Then, the I-DLB signal activates the I-DLB, and thus the control signal stored in the I-DLB in the form of a read-only memory (ROM) is generated. At this time, the number of registers that are masked and not stored depending on the control signal when the SES is stored, and therefore do not need to decode the logic conversion, will be extracted from the instruction with the same number of registers. . If the instruction read from the memory does not match the SES, the I-DLB is suppressed, and the signal connected to the I-DLB is replaced with the value of the instruction read from the memory to perform the normal instruction decoding process. The I-DLB structure formed according to the present invention is different from the conventional structure

486618 V. Description of the invention (5) is to use a look-aside buffer to reduce power. The microprocessor uses a look-aside buffer or cache memory to increase the execution rate, but I-DLB1 in the present invention is used to reduce the power consumption during execution.

Another difference between the I-DLB structure of the present invention and the structure of conventional techniques lies in the static characteristics of the I-DLB structure. During the execution of the program, the various registrations of the conventional technology are dynamically changed in the side-view buffer or cache memory to improve the execution speed of the microprocessor. The I-DLB structure of the present invention is determined in advance at the design stage. So I-DLB entries are not changed during the execution of the microprocessor. Therefore, compared with the dynamic storage of conventional techniques, the space occupied by the I-DLB structure of the present invention and the power loss can be minimized. In addition, although a random access memory (RAM) or a flip-flop (f 1 i p-f 1 ο p) is used to perform dynamic storage, the static storage I-D L B of the present invention can serve as a ROM structure. Since the instruction decoding block includes complex circuits, it is usually designed using design automation such as logic synthesis or compilation of microcode ROM. Therefore, it consumes more power than a fully customized design that is manually optimized. On the other hand, the I-DLB of the present invention is a simple buffer that can only be used by a small number of S E S instructions. Therefore, it can be more suitable for reducing power through a completely customized design and shortened lead time.

In other words, when designing the instruction decoding block, if the fully customized I-DLB structure is combined with the custom instruction decoding block implemented by design automation, then the specific application is completely customized to obtain the advantage of low power consumption. And the reduced design lead time of design automation,

Page 10 486618 V. Description of Invention (6). Although specific embodiments have been described to illustrate the present invention, it will be apparent to those skilled in the art that various modifications and changes can still be made. Those who do not violate the spirit of the present invention fall within the scope of the present invention. As mentioned above, the low-power instruction decoding method constructed according to the present invention can reduce power loss by using static extraction SES to perform low-power decoding and using the I-DLB structure when executing certain commonly used specific programs. Therefore, this method can provide excellent results for systems that require low-power operation of microprocessors, such as portable sound generators, mobile phones, and personal digital assistants (PDAs). Another effect of the present invention is that, while maintaining the instruction decoding block of the existing design, an S ES and an I-D L B can be conveniently added, so as to reduce the time required for the design. An object of the present invention is to provide a low-power instruction decoding method for a microprocessor, in which an instruction decoding look-aside buffer (I-DLB) is used to achieve a static extraction instruction at a low power used by a specific program frequently accessed. Set (SES) decoding, thereby reducing system power. According to the characteristics of the present invention that achieve the foregoing objectives, the low-power instruction decoding method for a microprocessor includes: a first step of extracting a static extraction instruction set (SES), which is executed in the design phase of the microprocessor during the execution of various During the application, a few of the most commonly used instructions are taken out, and some instructions will cause power loss due to the logic conversion of the instruction decoder; the first instruction read from the memory is compared with the SES extracted in the first step. Two steps; if the instructions of the second step are determined to be consistent with SES, connect

486618 V. Description of the invention (7) The signal to the instruction decoding look-aside buffer (I-DLB) is retained and it is forbidden to engage in logic conversion in the instruction decoder, and to take the form of read-only memory (R 0 M). The control signal stored in I-DLB is generated to extract the third step of the signal that does not need to be decoded and logically converted from the instruction; and if the instruction in the second step is determined to be inconsistent with SES, I-DL Β is suppressed At the same time, the signal connected to I-DL Β is replaced with the same value as the instruction read from the memory to perform the fourth step of the normal instruction decoding process. The foregoing and other features and advantages of the present invention will be better understood by those skilled in the art from the following detailed description made in conjunction with the drawings.

Page 486618 The diagram briefly illustrates the first diagram is a schematic diagram of the internal blocks of a general microprocessor; the diagram in the second diagram shows the analysis result of the power loss of a general microprocessor; the diagram in the third diagram shows Analysis results on the frequency of an instruction set used to execute various applications on a microprocessor; the fourth diagram is a schematic diagram of a method of extracting an SES; and the fifth diagram is a block diagram showing the use of an SES And the structure of an instruction decoding block of an instruction decoding look-aside buffer (I-DLB).

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Claims (1)

486618 VI. Application Patent Scope 1. A method for decoding low-power instructions for a microprocessor, which includes: The first step of extracting a static extraction instruction set (SES), which is executed during the design phase of the microprocessor during the execution of various applications During the program, a few of the most commonly used instructions are taken out, and some instructions will cause power loss due to the logic conversion of the instruction decoder; the second one is comparing one instruction read from the memory with the SE1S extracted in the first step Step; if the instruction of the second step is determined to be compatible with SES, the signal connected to the instruction decoding look-aside buffer (I-DLB) is retained to prohibit logic conversion in the instruction decoder, and the use of read-only memory (ROM) form of the control signal is generated in the DLB to extract the third step of the signal which does not need to be decoded and logically converted from the instruction; and if the instruction of the second step is determined to be inconsistent with SES, I -DLB is suppressed, and the signal connected to I-DLB is replaced with the same value as the command read from the memory to perform normal command decoding. The fourth step. Page 14