200834415 ^ 九、發明說明： 【發明所屬之技術領域】 、本發明屬於計算機架構（computer architecture)之領 域、，是針對處理器（processor)中的分支目標缓衝器（BTB)，提 出減少目標位址攔位（target address field)位元個數的方 【先前技術】 •分支目標缓衝器（BTK是用來儲存分支指令（branch 的目標位址（target address)，並常被利用來判 • =是否為分支指令，如果某-指令已被認定為分支指令，再由 分支預測益（branch predi ctor)根據此分支指令跳躍的歷 史’來判辦此分支指令是否會跳躍（taken or not)，若分支預 測為預測執行方向改變並非循序執行，則由分支目標緩衝器的 目標位址攔位(target address field)提供目標位址，讓程式 、 繼續執行下去。 而一般的作法是目標位址攔位直接儲存全部的位元個 數，可以參考圖1。 【發明内容】 _ 本發明提出一個新方法，讓分支目標緩衝器（BTB)之目標 位址欄位（target address field)，不需要儲存目標位址的全 部位兀個數，而是儲存本發明設計的偏移目標（offset target) ’且產生32位元的目標位址（target address)的過 程，不會增加時間延遲。 利用較少的位元數，達成相同功能，可以降低晶片的面 積，^更省電。以32位元MIPS指令集為例，利用此方法每一 個目標位址攔位（target address field)，可以減少15個位 元，也就是原本需要儲存32個位元，使用本發明只需要儲存 17個位元減少了 46.88%。再以32位元ARM指令集為例，利 用此方法母一個目標位址欄位（target address fieid)，可以 5 200834415 減少7個位元，也就是原本需要儲存32個位元，使用本發明 只需要儲存25個位元，減少了 21· 88%。任何指令集都可以適 用本發明，不同的指令集可以節省的最大位元個數也不同。 以512-entry的分支目標缓衝器（BTB)為例，若是32位元 MIPS指令集總共可以減少7680個位元，32位元ARM指令集總 共可以減少3584個位元。64位元或是更高位元的架構，應該 可以節省更多位元。200834415 ^ IX. Description of the invention: [Technical field to which the invention pertains] The present invention belongs to the field of computer architecture, and proposes a reduction target bit for a branch target buffer (BTB) in a processor. The number of bits in the target address field. [Prior Art] • Branch target buffer (BTK is used to store branch instructions (the target address of the branch) and is often used to determine = Is it a branch instruction, if a - instruction has been identified as a branch instruction, then the branch predi ctor will determine whether the branch instruction will jump or not according to the history of the branch instruction jump. If the branch prediction is that the prediction execution direction change is not sequential execution, the target address field is provided by the target address field of the branch target buffer, so that the program continues to execute. The general practice is to target the address block. The bit directly stores all the number of bits, and can refer to FIG. 1. [Summary of the Invention] _ The present invention proposes a new method for letting branches The target address field of the buffer (BTB) does not need to store all the bits of the target address, but stores the offset target of the design of the present invention and generates 32 bits. The process of the target address does not increase the time delay. With fewer bits, the same function can be achieved, which can reduce the area of the chip, and save power. Take the 32-bit MIPS instruction set as an example. By using this method, each target address field can be reduced by 15 bits, that is, 32 bits need to be stored. With the invention, only 17 bits need to be stored, which is reduced by 46.88%. For example, the 32-bit ARM instruction set uses this method to target a target address fieid, which can reduce 7 bits in 5 200834415, that is, it needs to store 32 bits. The invention only needs to be stored. The 25 bits are reduced by 21.88%. Any instruction set can be applied to the present invention, and the maximum number of bits that can be saved by different instruction sets is also different. The 512-entry branch target buffer (BTB) is , If the MIPS instruction set 32 yuan a total of 7680 bits can be reduced, a 32-bit ARM instruction set can reduce a total of 3584 bits .64-bit or higher-bit architecture, should be able to save more bits.
如果分支目標缓衝器（BTB)的entry數目越多，可以省得 位元個數也會越多，但本發明增加的電路卻是固定的。不過 entry數目小於16，可能就不適用本發明了。 本發明為一種節省分支目標緩衝器（BTB)的目標位址攔位 之位元個數的方法，包括： (a) 不儲存目標位址的全部位元個數，而儲存位元個數較少的 偏移目標（Offset target)，偏移目標分成三個部分，目 標位址之變動範圍、進位位元（Carry bit)、減/加位元 (Sub/Add bit) 〇 (b) 增加兩個功能單元，使在查（L〇〇k即）分支目標緩衝器 (BTB)的同時，對分支指令位址之變動範圍以上的部分做 加及減的運算； ^中（a)部分中的偏移目標的目標位址之變動範圍的位元 錄並==定：為指令集的妓齡格式的偏移攔位之位元個 數減去符號位元，若偏移目標的目標位址之變動範 個位元，相對地，兩個對指令位址之變動範圍以上的 及減的運^早凡，所運算的位元個數即可減少幾個位元。 成 分對分支指令位址之變動範圍以上的部分做加 ^減的ι异’也可以用加法器(Adder)或計數器(Counter)來達 位址======== 6 200834415 • 整的目標位址，並且沒有效能損失。 【實施方式】 本發明利用分支指令位址與目標位址有部分相似的部 分，兩者相似的部分就不儲存在分支目標緩衝器（βΤΒ)中，利 用這一點來達到減少目標位址攔位（target address fieid) 的位元個數，至於兩者相似之部分為何，就要從指令集的分支 指令格式來說明。 圖2為32位元MIPS指令集的分支指令格式、圖3為32 位元ARM指令集的分支指令格式，以下例1為32位元mips指 令集分支指令的跳躍範圍說明，例2為32位元ARM指令集分 支才曰々的跳躍範圍a兄明。由這兩例子可以知道分支指令跳躍的 距離是有固定範圍的，偏移量(〇ffset)的值會受到限制，而且 不同指令集的分支指令S兆躍範圍也不盡相同。 例1 : . BNE R3, R4, name if (Regs[R3]!=Regs[R4]) PC —name; ((PC+4)-217) ◊ name < ((PC+4)+217) 例2 : BEQ name • if (Z set) PC <- name; ((PC+8)-225) <= name < ((PC+8)+225) 以32位元MIPS指令集為例，兩個位元個數不相同的二進 制數字相加，例3是一個位元個數較少的簡單例子，其中casei 為偏移量之正數最大，case2為偏移量之負數最小。變動範圍 為指令集分支指令格式(branch instruction format)中的偏 移攔位之位元個數減去一個符號位元(sign bit)。偏移量的變 動範圍以上部分’最右邊的位元是偏移量的符號位元，其餘^ 符號延伸（sign extended)。 # 7 200834415 符元 變動範圍110000 1011 + 0000 111111 1100 祖ill 1011 iioooo • +1111 〇〇〇〇〇〇 1010 110000 儀移量 分龙指令位址+4^ 偏移量 8標位址 分支指令位址+4If the number of entries in the branch target buffer (BTB) is larger, the number of bits can be saved, but the circuit added by the present invention is fixed. However, the number of entries is less than 16, and the invention may not be applicable. The present invention is a method for saving the number of bits of a target address block of a branch target buffer (BTB), including: (a) not storing all the number of bits of the target address, and storing the number of bits The offset target is divided into three parts. The offset target is divided into three parts. The range of the target address, the carry bit, the Sub/Add bit, and the (b) increase. A functional unit that adds and subtracts the portion above the range of the branch instruction address while checking (L〇〇k is) the branch target buffer (BTB); ^ in part (a) The bit number of the range of the target address of the offset target is == fixed: the number of bits of the offset block of the age format of the instruction set minus the sign bit, if the target address of the offset target In the case of a change in the number of bits, relatively, the number of bits above and below the range of the change of the instruction address is reduced, and the number of bits to be operated can be reduced by a few bits. The component can add or subtract the part above the range of the branch instruction address. You can also use the Adder or Counter to reach the address ======== 6 200834415 • The whole Target address and no loss of performance. [Embodiment] The present invention utilizes a portion in which the branch instruction address is partially similar to the target address, and the similar parts are not stored in the branch target buffer (βΤΒ), and the point is used to reduce the target address block. The number of bits in the (target address fieid), as to the similarity between the two, is explained from the branch instruction format of the instruction set. Figure 2 shows the branch instruction format of the 32-bit MIPS instruction set, and Figure 3 shows the branch instruction format of the 32-bit ARM instruction set. The following example 1 shows the jump range of the 32-bit mips instruction set branch instruction. Example 2 is 32-bit. The jump range of the meta-ARM instruction set branch is a brother. It can be seen from these two examples that the distance of the branch instruction jump has a fixed range, the value of the offset (〇ffset) is limited, and the range of the branch instruction S mega-jump of different instruction sets is also different. Example 1: . BNE R3, R4, name if (Regs[R3]!=Regs[R4]) PC —name; ((PC+4)-217) ◊ name < ((PC+4)+217) Example 2 : BEQ name • if (Z set) PC <- name; ((PC+8)-225) <= name < ((PC+8)+225) Take the 32-bit MIPS instruction set as an example. A binary number with two different numbers of bits is added. Example 3 is a simple example with a small number of bits, where casei is the largest positive of the offset and case2 is the least negative of the offset. The range of change is the number of bits of the offset block in the instruction set branch instruction format minus one sign bit. The uppermost part of the shifting range of the offset is the sign bit of the offset, and the remaining ^ symbols are extended. # 7 200834415 Symbol range 110000 1011 + 0000 111111 1100 Zu ill 1011 iioooo • +1111 〇〇〇〇〇〇1010 110000 Instrument shift minute instruction address +4^ Offset 8 target address branch instruction address +4
Casa 2 由此可知，如果有進位產生，會造成兩者 的部分有加丨錢1的差異，若沒有進侧_ 圍以上 將分支指令位址與目標位址來拿—起做比較，可見 圖5 ’分支指令位址與目標位址的差異主要是在變動簕^ 4部 目標位址之變動範圍以上的部^若沒有進 /刀支才曰令位址相同，若有進位，則會有加（或減i的變化二 另外byte of f set這部分是不會改變的（因為pc 4)，所以只需要儲存變動範圍再加上兩個額外的位元， 錄有無進位以及是做加或減調整的動作，即可利 δ 生出32位元的目標位址（32-bit target addr*H°。二 產 本發明適用於各種指令集的分支目標緩衝器（BTB)，以 說明全部都以32位元ARM指令集為例，其他指^令集同理，在 本發明中，使用偏移目標(offset target)取代了原本儲存在 分支目標緩衝器（BTB)中的32位元目標位址，偏移目標的格式 請參考圖6，其中目標位址之變動範圍這個部分报明^ 再說明。 … 而 進位(Carry)這個位元是判斷有無進位到目標位址之變動 8 200834415 城=上的部分，要比較分支指令位址與目標位址的第3i位 兀到第25位元，這之間的每―個位元，若有某—個位元不同， ，判斷結果就是有進位，而目6中進位4立元的計算方程式，即 疋判斷廷兩部分的每一個位元有無相等的作法，若相等則進位 位元的值為0，表示沒有進位，若不相等則進位位元的值為i， 表示有進位’而減/加（Sub/Add)這個位元，則是依昭焉分去# 令的偏移量為正數或錄來決定，紋正數難為 數則值為1，接下來是說明如何利用偏移目標得到兕位元目 標位址的演算法。 target address[24:2] = offset target[24:2]Casa 2 knows that if there is a carry, it will cause the difference between the two parts to increase the amount of money. If there is no side _, the branch instruction address and the target address are compared. The difference between the 5' branch instruction address and the target address is mainly in the part above the range of the change of the target address of the 4th part. If there is no entry/knife, the address is the same. If there is a carry, there will be Add (or subtract i from the change of the other byte of f set this part will not change (because pc 4), so only need to store the range of variation plus two additional bits, recorded with no carry and is added or By reducing the adjustment action, the 32-bit target address (32-bit target addr*H°) can be generated. The present invention is applicable to branch target buffers (BTBs) of various instruction sets to illustrate that all The 32-bit ARM instruction set is taken as an example, and the other instructions are similar. In the present invention, the offset target is used instead of the 32-bit target address originally stored in the branch target buffer (BTB). For the format of the offset target, please refer to Figure 6, where the target address is The part of the range of change is reported ^ again. ... and the carry (Carry) bit is to determine whether there is a carry to the change of the target address 8 200834415 City = upper part, to compare the branch instruction address with the target address of the 3i When it is located at the 25th position, if there is a certain bit different for each bit between the two, the result of the judgment is that there is a carry, and the calculation formula of the carry 4 in the head 6 is the judgment formula. Whether each bit of the two parts has an equal method. If they are equal, the value of the carry bit is 0, indicating that there is no carry. If they are not equal, the value of the carry bit is i, indicating that there is carry 'and minus/add (Sub/ Add) This bit is determined by the deviation of the #定令 as a positive number or recorded. The positive number of the pattern is difficult to be 1, the next step is to show how to use the offset target to obtain the target position. Algorithm of the address. target address[24:2] = offset target[24:2]
If (( Carry == 1 ) && ( Sub/add == 1 )) target address[31:25] = pc[31：25] - 1· else if (( Carry 二二 1 )鉍（Sub/add 〇 )’） target address[31:25] = pc[31：25] + 1； else ’ target address[31:25] = pc[31：25]； target address[l:0] = pc[l：〇]； 圖7為一般的分支目標緩衝器（BTB)的讀取過程，其過程 大致為先解碼(decode)選出要讀SRAM的哪一個集合，再 讀出在SRAM所對應集合中的每一筆資料，比較各^資料的桿 籤(tag)，在依照標籤比較之後的結果，用多工器選出我們^ 正要讀取的目標位址，之後就將目標位址送到NpC(Next PC)。 而本發明對變動範圍以上的部分，做加1與減丨運算之調 整需在比較標籤(tag)之前做完，這樣子的作法沒有增=時^ 延遲(time delay)。圖8、圖9、圖1〇為本發明的讀取32 ^ 元目標位址的作法，圖8說明了本發明讀取分支目標緩衝器 (BTB)的過程，在一開始用指令位址去查（1〇〇k叩）分支目g 緩衝器（BTB)時，同時也將指令位址送到「指令位址[31:25 ] 與「指令位址[31:25]-1」，這兩功能單元對指令位址[guy 200834415 部分執行加1與減1的運算。 圖9說明當變動範圍以上的部分運算做完之後，再依 位與減/加兩位元，選擇變動範圍以上的部分，再由標鐵 比較的結果’選擇某一個目標位址輸出，即為32位1元的目 位址（32-bit target address)。 ' 不 圖10為4曰令位址[31:25]+1」功能單元的内部電路，夂 個位元的運算都是獨立的，而且運算時間並不長，可二 時間内做完。 本案之圖式、元件符號或名詞定義可參考如下： 1.目標位址（target address)為分支指令（branch instruct ion)跳躍的目的地位址。 2·才曰令位址[31:25]的意思為32位元的指令位址中的第π位 元到第31位元，總共有7個位元，其餘以此類推。 3· ^支目標緩衝器（Branch Target Buffer)為存放分支指令對 4· MIPS指令集之分支指令格式中的immediate攔位盘纖 ====式中的Gifset攔位的值就是本發明提到 5.偏移目標(0ffset target)為本發明用來取代32位元目標位 =儲存在分支目標緩衝H巾，以絲麵降低儲存的:元 ，數。一偏移目標的總位元個數為變動範圍的位域再增加2 個位元。 曰 6· J气員測器(branch predictor) ’根據分支指令的跳躍歷 史，，判斷此分支指令是否會跳躍(taken 〇r n〇t)。 7. 為分支指令位址與目標位址比較的主要差異部分。 你If本ί Γ的設計，變動範_位元個數為指令集的偏移攔 位位兀個數減去符號位元(sign bit) 8· 為指令位址的第0個位元與第1個位元，在32 集巾是固定不會魏的部分，*如果是64位元指 200834415 $集byte Qffset則會有3個位元是不會變動的。（本發明 舉的位元例子都是從0開始） 9. Ϊ意Ϊ中’如果線與線之财81點，表示兩條線有互相連 接，若沒有圓點，表示兩條線沒有互相連接。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技術者，在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保護範 附之申請專利範圍所界定者為準。 旻 【圖式簡單說明】If (( Carry == 1 ) && ( Sub/add == 1 )) target address[31:25] = pc[31:25] - 1· else if (( Carry 2 2 1 )铋 (Sub /add 〇)') target address[31:25] = pc[31:25] + 1; else ' target address[31:25] = pc[31:25]; target address[l:0] = pc[ l: 〇]; Figure 7 is a general branch target buffer (BTB) read process, the process is roughly to decode (decode) which set of SRAM to read, and then read in the corresponding set of SRAM For each piece of data, compare the tag of each piece of data. After the comparison according to the tag, use the multiplexer to select the target address that we are going to read, and then send the target address to NpC (Next PC). However, in the present invention, the adjustment of the addition and subtraction operations of the portion above the variation range is completed before the comparison tag (tag), so that the sub-operation does not increase the time delay. 8 , FIG. 9 and FIG. 1 are the operation of reading the 32 ^ unit target address of the present invention, and FIG. 8 illustrates the process of reading the branch target buffer (BTB ) of the present invention, starting with the instruction address at the beginning. When checking (1〇〇k叩) branch g buffer (BTB), the instruction address is also sent to "instruction address [31:25] and "instruction address [31:25]-1", which The two functional units perform the operation of adding 1 and subtracting 1 to the instruction address [guy 200834415 part. Figure 9 shows that after the partial operation above the variation range is completed, the part above the variation range is selected according to the bit and the subtraction/addition two-digit element, and the result of the comparison of the standard object is selected to select a target address output. 32-bit target address (32-bit target address). 'Figure 10 is the internal circuit of the 4曰[ address address [31:25]+1” function unit. The operation of each bit is independent, and the operation time is not long, and it can be completed in two time. The schema, component symbol or noun definition of this case can be referred to as follows: 1. The target address is the destination address of the branch instruction jump. 2. The address [31:25] means that the π bit to the 31st bit in the 32-bit instruction address has a total of 7 bits, and so on. 3·^Branch Target Buffer is the value of the Gifset block in the branch block format of the branch instruction format in the branch instruction format of the 4· MIPS instruction set. 5. Offset target (0ffset target) is used to replace the 32-bit target bit = stored in the branch target buffer H towel, to reduce the storage: element, number. The number of total bits of an offset target is a bit field of the variation range and further increased by 2 bits.曰 6· J. The brain predictor ’ judges whether or not this branch instruction will jump (taken 〇r n〇t) according to the jump history of the branch instruction. 7. The main difference between the branch instruction address and the destination address. The design of your If Γ ,, the number of change _ bits is the offset of the instruction set 兀 the number minus the sign bit (sign bit) 8 · is the 0th bit of the instruction address and the first 1 bit, in 32 sets of towels is fixed will not be Wei, * If it is 64 bit refers to 200834415 $ set byte Qffset will have 3 bits will not change. (The examples of the bits in the present invention are all starting from 0.) 9. In the meantime, if the line and the line of money are 81 points, it means that the two lines are connected to each other. If there is no dot, it means that the two lines are not connected to each other. . While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the patent application scope of the protection patent is subject to change.旻 [Simple description]
圖1 ·習知的分支目標緩衝器（conventional BTB)之示意圖。 圖2 : 32位元MIPS指令集的分支指令格式之示意圖。μ曰 圖3 : 32位元ARM指令集的分支指令格式之示意圖。 圖4 .MIPS指令集的分支指令位址與目標位址比較之示意圖。 圖5 : ARM指令集的分支指令位址與目標位址比較之示意^圖7。 圖6 · ARM指令集的偏移目標(0ffsef target)格式之示音圖。 圖7:習知的分支目標緩衝器（BTB)讀取時間之示意圖、。 圖8 :本發明的分支目標缓衝器（BTB)具體實施例之示魚圖。 圖9:本發明的分支目標緩衝器（BTB)第二具體實施例^°示意 圖。 心、Figure 1 - Schematic diagram of a conventional branch target buffer (conventional BTB). Figure 2: Schematic diagram of the branch instruction format for the 32-bit MIPS instruction set. μ曰 Figure 3: Schematic diagram of the branch instruction format for the 32-bit ARM instruction set. Figure 4. Schematic diagram of the comparison of the branch instruction address and the target address of the MIPS instruction set. Figure 5: Schematic diagram of the comparison of the branch instruction address and the target address of the ARM instruction set. Figure 6 · A sound map of the offset target (0ffsef target) format of the ARM instruction set. Figure 7: Schematic diagram of a conventional branch target buffer (BTB) read time. Figure 8 is a fish diagram of a specific embodiment of a branch target buffer (BTB) of the present invention. Figure 9 is a schematic illustration of a second embodiment of a branch target buffer (BTB) of the present invention. heart,
圖10 :本發明的指令位址[31:25]+1功能單元的内部 意圖。 電路之示 圖11:本發明的指令位址[31:25]-1功能單元的内部電路 意圖。 不 【主要元件符號說明】 1.目標位址（target address)為分支指令（branch instruction)跳躍的目的地位址。 2·指令位址[31:25]的意思為32位元的指令位址中的第25位 元到第31位元，總共有7個位元，其餘以此類推。 立 3·分支目標緩衝器（Branch Target Buffer)為存放分支指令對 11 200834415 應的目標位址。 人集之分支指令格式中的immediate攔位與arm指 的ί梦：，日令格式中的Qf f set欄位的值就是本發明提到 町獨私i(offset)。 5.1!移if(offset target)為本發明用來取代32位元目標位 她諸f在分支目標緩衝器中’以此來達到降低儲存的位元 數L偏移目標的總位元個數為變動範圍的位元數再增加2 個位元。Figure 10: Internal intent of the instruction address [31:25] +1 functional unit of the present invention. Circuit Diagram Figure 11: Internal circuit intent of the instruction address [31:25]-1 functional unit of the present invention. No [Main component symbol description] 1. The target address is the destination address of the branch instruction jump. 2. The instruction address [31:25] means the 25th to the 31st in the 32-bit instruction address, for a total of 7 bits, and so on. The Branch Target Buffer is the target address for storing the branch instruction pair 11 200834415. The immediate block in the branch instruction format of the person set and the arm of the arm point: the value of the Qf f set field in the Japanese format is the one mentioned in the present invention. 5.1! shift if (offset target) is used to replace the 32-bit target bit, and her f is in the branch target buffer, so that the total number of bits of the bit number L offset target is reduced. The number of bits in the range of change is further increased by 2 bits.
6· ^支?測器(branch predictor)，根據分支指令的跳躍歷 史’ ^判斷此分支指令是否會跳躍(taken or ησ〇。 7.變動範圍為分支指令位址與目標紐味社要差異部分。 ^康本巧的設計’變動範_位元個數為指令集的偏移搁 位位兀個數減去符號位元(sign bit) 8々16(^361：為指令位址的第〇個位元與第1個位元，在32 位元扣令集中是固定不會變動的部分，而如果是料位元指 令集byte 0ffset則會有3個位元是不會變動的。（本發明 舉的位元例子都是從〇開始） 9·示意f中，如果線與線之間有_，表示兩條線有互相連 接’若沒有圓點，表示兩條線沒有互相連接。 126·^branch predictor, according to the jump history of the branch instruction '^ determine whether the branch instruction will jump (taken or ησ〇. 7. The range of variation is the difference between the branch instruction address and the target New Zealand community) ^Kang Benqiao's design 'variation _ bit number is the offset number of the instruction set 兀 number minus the sign bit (sign bit) 8々16 (^361: the third bit of the instruction address The bit and the first bit are fixed and will not change in the 32-bit deduction set, and if the bit instruction set byte 0ffset has 3 bits, it will not change. The examples of the bits in the invention are all starting from ). 9. In the f, if there is a _ between the lines, it means that the two lines are connected to each other. 'If there is no dot, it means that the two lines are not connected to each other. 12