丄 331675 九、發明說明： 【發明所屬之技術之領域】 一種具溫度感測元件之電路板及其製法，尤指—種嵌 埋有半導體晶片之電路板中具有溫度感測元件之結^ 其製法。 【先前技術】 =著電子產業的蓬勃發展，提供主被動元件及線路载丄331675 IX. Description of the invention: [Technical field of invention] A circuit board having a temperature sensing element and a method of manufacturing the same, in particular, a circuit board having a semiconductor chip embedded with a temperature sensing element System of law. [Prior technology] = The booming development of the electronics industry, providing active and passive components and line loading
接之電路板亦逐漸由雙層板演變為多層板，俾於有限的空 ^下L藉由層間連接技術擴大電路板上可利用的電路面積 ，供高電子密度之積體電路的使用需求，以符合該電子】 。口 J 31化、南性能、高功能、高運算能力的發展趨勢。 為因應上述之趨勢，於是發展出—種增層連接技術， J於-電路板表面交互堆疊多層介電層與線路層，再於 =介電層中形成導電盲孔或貫穿之電料通孔，俾以電性 路Γ且於該電路板中嵌埋有半導體晶片，該半 V體a曰片亚與相對應之線路層電性連接。 工作導體晶片於運作時’其會產生相當程度的 又右^工作溫度過高時，則須對該電路板 行散熱的動作，俥以卩方益# 1道 篮進 +導體w過熱㈣損，而該 啟…力革之凋整，通常僅能藉由外部量測，並提供 制外：的冷卻裳置之提高散熱功免半工 體晶片運作溫度過高而損壞。 避免該+導 但°亥半導體晶片係嵌埋在電路;^> 哕丰導體曰Η认π ^ 牡电峪板中，亚热法真實量測 片於運作時的實際溫度，必須要藉由量測該電 110304 6 1331675 路板外部環境之溫度，而量測外部溫度因外在變數大，導 致該半導體晶片於運作時的溫度與外部量測所得之誤差 甚大，無法對嵌埋於電路板之半導體晶片溫度進行正確的 :·監控，而無法確保半導體晶片正常的運作，甚至可能因無 :-法適時提高散熱功率而導致該半導體晶片過熱毀損。 此外，若直接將半導體晶片的晶背面的熱點導接至外 部，再藉由熱電偶等溫度感測器量測溫度，不僅熱傳路徑 過長，且外部溫度仍會影響量測溫度的準確性，無法如實 籲顯現嵌埋晶片的實際溫度，亦無法經由回饋線路，對嵌埋 晶片之電路板進行監控。 因此，如何量測該電路板本體中的半導體晶片之實際 溫度，或進行監控，俾使該半導體晶片得以正常運作，並 防範其過熱毀損的情況產生，而，為當今亟待思考之課題。 【發明内容】 鑒於以上所述習知技術之缺點，本發明之一目的在於 $提供一種具溫度感測元件之電路板及其製法，得以監控設 於電路板本體中的半導體晶片之實際溫度，俾使該半導體 晶片得以於正常工作溫度下運作，並防止該半導體晶片產 生過熱毀損的情況。 本發明之又一目的為提供一種具溫度感測元件之電 路板及其製法，得以利用電阻值的改變下，而得知設於該 電路板本體中的半導體晶片之實際溫度。 為達上揭目的，本發明提供一種具溫度感測元件之電 路板，係包括：基板本體，係具有一第一表面與第二表面， 7 110304 1331675 並具有一貫穿該第一及第二表面之開口；半導體晶片，係 容置於該開口中，且具有一主動面及非主動面，於該主動 面具有複數電極墊；第一介電層，係設於該基板本體之第 :· 一表面及該半導體晶片之非主動面，且具有至少一第一開 •-孔以露出該半導體晶片之非主動面；導熱結構，係設於該 第一介電層之第一開孔中；複數電阻，係設於該些導熱結 構及第一介電層表面，且該些電阻分別對應連接該些導熱 結構，其中，該電阻係作為溫度感測元件；第三介電層， 籲係設於該第一介電層表面及電阻表面，並具有複數第三開 孔，其中部份成對之第三開孔露出該電阻之部份表面；第 一線路層，係設於該第三介電層表面，並於該些第三開孔 中形成具有複數成對之電極結構以電性連接該電阻；以 及第一絕緣保護層，係設於該第三介電層及第一線路層表 面，並具有開孔以露出該電極結構之部份表面，以作為電 阻量測點。 Φ 依上述結構，本發明復包括：第二介電層，係設於該 基板本體之第二表面及該半導體晶片之主動面，且具有複 數第二開孔以對應露出該些半導體晶片之電極墊；第一 導電結構，係設於該第二介電層之第二開孔中以電性連接 該電極墊；第四介電層，係設於該第二介電層及第一導電 結構表面，並具有複數第四開孔，其中部份之第四開孔露 出該第一導電結構之部份表面；第二線路層，係設於該第 四介電層表面’並於該弟四開孔中形成弟二導電結構以電 性連接該第一導電結構；電鍍導通孔，係貫穿該基板本 8 110304 ^二第二、第三及第四介電層以電性連接該第〜及 二：、、，？層，以及第二絕緣保護層，係設於該第四介電声 及弟-線路層表面，並具有開孔 曰 份表面。 ^弟一線路層之部 美板：2結構’該基板本體為一絕緣板、金屬板、陶究 有線路之内層電路板；該第一及第二介 於該開口中；；=:=以將該半導體晶片固定 阻材料，對溫度反應快速之熱電 阻材科，而該熱電阻材料係為鉑、銅或鎳。 勺括本二月讀供Γ種具溫度感測元件之電路板製法’係 上一./、一具有第一表面與第二表面之基板本體，益且 L二一及第二表面之開口，於該開口中容置有-=體晶片，該半，體晶片具有-主動面及非主動面且 、主動面具有硬數電極墊；於該基板本體之第一表面 及該半導體晶片之非主動面形成有一第一介電層，且該第 1之;中形成有至少一第一開孔以露出該半導體晶片 φ又於該基板本體之第二表面及該半導體晶月 之主動面形成有一筮-入+a 弟一"電層，且於該第二介電層t形成 、弟—開孔以對應露出該些半導體晶片之電極墊； :該第▲開孔中之半導體晶片的非主動面形成有導熱結 +亚於5亥第二開孔中形成有第一導電結構；於該第二介 ::表面形成有第四阻層以覆蓋該第一導電結構，於該 二匕結構及第-介電層表面形成有對應之電阻，其中， 該電阻係作為溫度感測元件；移除該第四阻層以露出該 110304 9 1331675 第一導電結構及第二介電層；於該第一介電層表面及電 阻表面形成有一第三介電層，並形成有複數第三開孔，且 部份成對之第三開孔露出該電阻之部份表面，又於該第二 | 介電層及第一導電結構表面形成有一第四介電層，且形成 ;•有複數第四開孔，其中部份之第四開孔露出該第一導電結 構之部份表面，並形成有貫穿該基板本體、第一、第二、 第三及第四介電層之通孔；於該第三介電層表面形成有 第一線路層，並於該些第三開孔中形成具有複數成對電極 籲結構以電性連接該電阻，又於該第四介電層表面形成有第 二線路層，並於該第四開孔中第二導電結構以電性連接該 第一導電結構，且於該通孔中形成有電鍍導通孔以電性連 接該第一及第二線路層；以及於該第三介電層及第一線 路層表面形成有一第一絕緣保護層，並形成開孔以露出該 電極結構之部份表面，又於該第四介電層及第二線路層表 面形成有第二絕緣保護層以露出該第二線路層之部份表 • 面。 依上述之製法，該基板本體係為一絕緣板、金屬板、 陶瓷基板或具有線路之内層電路板；該第一及第二介電 層係填充於該開口與半導體晶片之間以將該半導體晶片 固定於該開口中；該電阻係為電阻值對溫度反應快速之 熱電阻材料，而該熱電阻材料係為鉑、銅或鎳。 又依上述之製法，該導熱結構及第一導電結構之製 法，係包括：於該第一介電層表面及其第一開孔中之半導 體晶片的非主動面形成有一第一導電層，並於該第二介電 10 110304 1331675 層表面及其第二開孔中之電極墊表面形成有一第二導電 層；於該第一導電層表面形成有一第一阻層，並形成有第 一開口以露出該第一開孔中之第一導電層，又於該第二導 夂電層表面形成有第二阻層，且形成有第二開口以露出該第 :·二開孔中之第二導電層；於該第一開孔中之第一導電層 及第一開口中之表面形成該導熱結構，並於該第二開孔中 之第二導電層及第二開口中之表面形成該第一導電結 構；以及移除該第一及第二阻層以露出該第一及二導電 鲁層。 該電阻之製法，係包括：於該第一導電層表面形成有 一第三阻層，且該第三阻層中形成有第三開口以露出該第 一導電層及導熱結構；於該第三開口中形成該電阻，使該 電阻連接該導熱結構；以及移除該第三阻層及其所覆蓋 之第一導電層，與該第四阻層及其所覆蓋之第二導電層。 該第一、第二線路層及電鍍導通孔之製法，係包括： Φ於該第三介電層表面、該第三介電層之第三開孔中的表面 及該第三開孔中之電阻的部份表面、該第四介電層表面、 該第四介電層之第四開孔中的表面及該第四開孔中之第 一導電結構的部份表面、該通孔中形成有一第三導電層； 於該第三導電層表面形成有一第五阻層，且該第五阻層中 形成有第五開口以露出該第三開孔、第四開孔及通孔；於 該第五開口中電鍍形成該第一、第二線路層及電鍍導通 孔，且使該第一線路層中形成該電極結構以電性連接該電 阻，該第二線路層中形成該第二導電結構以電性連接該第 11 110304 -導電結構；以及移除該 電層。 也層及其所覆盍之第三導 本發明之半導許θ 4 •度變化，並藉由電極、項該電阻感測運作時的溫 • ^ ^ ^ ；X "J# 1 ^ + 量測監控，俾時對該半導體晶片溫度進行 【實施方式】㈣該+導體q的正常運作。 以下係藉由特定的具體實施例說 式，所屬技術領域中具有通常知識者可由本說4;斤;方 之内：輕“瞭解本發明之其他優點與功效。所揭- 電路：：:：上A至1 N圖’係為本發明具溫度感測元件之 電路板衣法之貫施例剖面示意圖。 如第1A圖所示’提供一具有第一表面1〇 面·，基板本體10，該基板本體1〇為一絕緣板、= ，、陶究基板或具有線路之内層電路板，並具有一貫穿該 第及第一表面1〇a，10b之開口 1〇〇，於該開口 1〇〇中容 置有一半導體晶片U，該半導體晶片U具有一主動面山 及非主動面lib’且於該主動面lla具有複數電極塾⑴； 於該基板本體10之第一表面1〇a及該半導體晶片n之非 主動面lib形成有一第一介電層12a’又於該基板本體1〇 之f二表面10b及該半導體晶片u之主動面lla形成有 一第二介電層12b’且該第一及第二介電層12al2b係填 充於該開口 100與半導體晶片u之間，俾將該半導體晶 片11固定於該開口 1〇〇中。 110304 12 1331675 如第1B圖所示，於該第—介電層12a中形成有至少 一第一開孔121a以露出該半導體晶片n之非主動面 lib’且於該第二介電層12b中形成有複數第二開孔12別 以對應露出該些半導體晶片1 i之電極墊n J。 如第1C圖所示，於該第—介電層12a表面及其第一 開孔121a中之半導體晶片u的非主動面llb形成有一第 一導電層13a，於該第一導電層13a表面形成有一第一阻 層14a，並形成有第一開口 141a以露出該第一開孔i2ia 中之第一導電層13a:又於該第二介電層12b表面及其第 一開孔122b中之半導體晶片11的電極墊111表面形成有 一第二導電層13b，並於該第二導電層13b表面形成有第 二阻層14b，且形成有第二開口 142b以露出該第二開孔 122b中之第二導電層13b。 如第1D圖所示，接著，藉由該第一導電層13&以於 該弟一開孔121a及第一開口 14la中之表面形成導熱結構 15,使該導熱結構15接觸該半導體晶片u之非主動面 11M並於該第二開孔122b及第二開口 14此中之表面形 成該第一導電結構16，使該第一導電結構16電性連接該 半導體晶片11之電極墊111。 如第1E圖所示，之後移除該第一及第二阻層14&，14b =路出該第一及二導電層13a，13b，以及導熱結構15及 第〜導電結構16。 —一如第1F圖所示，於該第一導電層13a表面形成有一 第三阻層14c，且該第三阻層14c中形成有第三開口 U3c 110304 13 以露出該第一導電；η el3a及蛉熱結構15,並於哕篦-八 電層m表面形成有第四阻 於：弟-介 16及第二導電層l3b。 ^盍該弟-導電結構 如第1°圖所示’藉由該第一導 阻層i4c之第三開口 143c ，二3a以於该弟三 阻17連接該導熱处構 又4私阻17’使該電 溫度反應快速之j電1材V、中該電阻17係為電阻值對 熱電阻材料係為以作為溫度感測元件，而該 第4= 所:V移除該第三阻層i4c及其所覆蓋之 及矛W: a以路出該第一介電層12a及電阻17,以 出該第二介電Λ二 之第二導電層13b以露 产1先層12b及第一導電結構16。 辛面圖所不’於該第-介電層12a表面及電阻17 123c* 0 s 12c，亚形成有複數第三開孔 * .刀對之第三開孔123c露出該電阻17之部份 二介電層12b及第-導電結構16表面形 中部份之:；1 %層12d’且形成有複數第四開孔124d，其 、，四開孔124d露出該第一導電結構16之部份表 四=成有貫穿該基板本體1〇、第一、第二、第三及 ^介，層叫121)，此12(1之通孔1〇1。 介電^21J，示’於該第三介電層12C表面、該第三 中之帝c之第二開孔123c中的表面及該第三開孔123c to人且17的部份表面、該第四介電層12d表面、該第 9 之第四開孔124d中的表面及該第四開孔 110304 14 1331675 - _^之第—導電結構16的部份表面、該通孔ι01中形 成有一弟三導電層13c。 =1K圖所示，接著於該第三導電層I3c表面形成 •，… J5且層14e’且該第五阻層14e中形成有第五開口 • L以路出該第三開孔123c、第四開幻24d及通孔⑻。 第:L圖所示:於該第三介電層12c表面之第三導 广曰c，且位於該弟五開口 145e中形成有第一線路層 in些第三開孔123c中形成具有複數成對電極結 以％性連接該電p且17,又於該第四介電層12 2形成有第二線路層18b ’並於該第四開孔md中形成: 有弟-導電結構職以電性連接該第—導電結構16，且 於=通孔101中形成有電錢導通孔18c以電性連接 接塾職路層和H玄弟二線路層18b具有電性連The connected circuit board is gradually evolved from a double-layer board to a multi-layer board. Under the limited space, the circuit area available on the circuit board is expanded by the interlayer connection technology, and the use of the integrated circuit with high electron density is required. In order to comply with the electronic]. The development trend of J 31, South performance, high function and high computing power. In order to cope with the above trend, a layer-adding connection technology has been developed, and a plurality of dielectric layers and circuit layers are alternately stacked on the surface of the circuit board, and conductive via holes or through-holes are formed in the dielectric layer. The semiconductor wafer is embedded in the circuit board, and the semiconductor body is electrically connected to the corresponding circuit layer. When the working conductor chip is in operation, it will generate a considerable degree of right and the working temperature is too high, then the circuit must be dissipated from heat, and then the side of the circuit will be overheated (four). However, the spurt of the sturdy, usually can only be measured by external measurement, and provides the external cooling: the cooling heat is increased to avoid the damage of the semi-worker wafer operating temperature is too high. Avoid the +-guided but the semiconductor chip is embedded in the circuit; ^> 哕 曰Η 曰Η 曰Η π π π 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡 牡Measure the temperature of the external environment of the circuit 110304 6 1331675, and measure the external temperature due to the external variable, resulting in a large error in the temperature and external measurement of the semiconductor wafer during operation, and cannot be embedded in the circuit board. The temperature of the semiconductor wafer is correctly monitored: it is not possible to ensure the normal operation of the semiconductor wafer, and may even cause the semiconductor wafer to overheat and damage due to the absence of a suitable heat dissipation power. In addition, if the hot spot of the crystal back surface of the semiconductor wafer is directly connected to the outside, and the temperature is measured by a temperature sensor such as a thermocouple, not only the heat transfer path is too long, but the external temperature still affects the accuracy of the measured temperature. The actual temperature of the embedded wafer cannot be accurately predicted, and the circuit board embedded with the wafer cannot be monitored via the feedback line. Therefore, how to measure or monitor the actual temperature of the semiconductor wafer in the body of the board, so that the semiconductor wafer can operate normally, and prevent the occurrence of overheating and damage, is an urgent problem to be considered today. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, it is an object of the present invention to provide a circuit board having a temperature sensing element and a method of manufacturing the same, which can monitor the actual temperature of a semiconductor wafer disposed in the body of the circuit board. The semiconductor wafer is allowed to operate at a normal operating temperature and prevents the semiconductor wafer from being damaged by overheating. It is still another object of the present invention to provide a circuit board having a temperature sensing element and a method of fabricating the same that utilizes a change in resistance value to know the actual temperature of a semiconductor wafer disposed in the body of the circuit board. In order to achieve the above, the present invention provides a circuit board having a temperature sensing component, comprising: a substrate body having a first surface and a second surface, 7 110304 1331675 and having a first and second surface extending therethrough The semiconductor wafer is disposed in the opening and has an active surface and an inactive surface. The active surface has a plurality of electrode pads. The first dielectric layer is disposed on the substrate body: a surface and an inactive surface of the semiconductor wafer, and having at least one first opening to expose an inactive surface of the semiconductor wafer; a heat conducting structure disposed in the first opening of the first dielectric layer; a resistor is disposed on the surface of the heat conducting structure and the first dielectric layer, and the resistors are respectively connected to the heat conducting structures, wherein the resistor is used as a temperature sensing component; and the third dielectric layer is The first dielectric layer surface and the resistive surface have a plurality of third openings, wherein the third pair of openings open a portion of the surface of the resistor; the first circuit layer is disposed on the third dielectric Layer surface, and a plurality of pairs of electrode structures are formed in the third opening to electrically connect the resistors; and a first insulating protective layer is disposed on the third dielectric layer and the surface of the first circuit layer, and has openings to expose the Part of the surface of the electrode structure to serve as a resistance measurement point. According to the above structure, the second dielectric layer is disposed on the second surface of the substrate body and the active surface of the semiconductor wafer, and has a plurality of second openings to correspondingly expose the electrodes of the semiconductor wafers. a first conductive structure is disposed in the second opening of the second dielectric layer to electrically connect the electrode pad; the fourth dielectric layer is disposed on the second dielectric layer and the first conductive structure a surface having a plurality of fourth openings, wherein a portion of the fourth opening exposes a portion of the surface of the first conductive structure; and a second circuit layer is disposed on the surface of the fourth dielectric layer Forming a second conductive structure in the opening to electrically connect the first conductive structure; plating a via hole through the substrate, the second, third, and fourth dielectric layers are electrically connected to the first and two:,,,? The layer and the second insulating protective layer are disposed on the surface of the fourth dielectric sound and the circuit layer, and have an opening surface. ^弟一线层的美板: 2 structure 'the substrate body is an insulating plate, a metal plate, a ceramic circuit with an inner circuit board; the first and second are interposed in the opening;; =:= The semiconductor wafer is fixed with a resistive material, which is a thermoelectric resistor material that reacts rapidly to temperature, and the thermal resistance material is platinum, copper or nickel. The method of manufacturing a circuit board for reading a temperature sensing component in February is a substrate body having a first surface and a second surface, and an opening of the second surface and the second surface. Having a -= body wafer in the opening, the half body wafer has an active surface and an inactive surface, and the active surface has a hard electrode pad; the first surface of the substrate body and the semiconductor wafer are inactive Forming a first dielectric layer on the surface, and forming at least one first opening to expose the semiconductor wafer φ and forming a defect on the second surface of the substrate body and the active surface of the semiconductor crystal moon -in the +a 一一" electric layer, and formed in the second dielectric layer t, the brother-opening to correspondingly expose the electrode pads of the semiconductor wafer;: the inactive of the semiconductor wafer in the ▲th opening a first conductive structure is formed in the second opening of the surface of the second layer: a second resist layer is formed on the surface of the second dielectric layer to cover the first conductive structure, and the second conductive structure is a surface of the first dielectric layer is formed with a corresponding resistor, wherein the resistor is used as a temperature a sensing device; removing the fourth resist layer to expose the first conductive structure and the second dielectric layer; forming a third dielectric layer on the surface of the first dielectric layer and the resistive surface, and forming a plurality of third openings, and a portion of the third openings expose a portion of the surface of the resistor, and a fourth dielectric layer is formed on the second dielectric layer and the surface of the first conductive structure, and is formed; a plurality of fourth openings, wherein a portion of the fourth openings expose a portion of the surface of the first conductive structure and are formed through the substrate body, the first, second, third and fourth dielectric layers a through hole; a first circuit layer is formed on the surface of the third dielectric layer, and a plurality of pairs of electrode structures are formed in the third openings to electrically connect the resistor, and the fourth dielectric layer a second circuit layer is formed on the surface, and the second conductive structure is electrically connected to the first conductive structure in the fourth opening, and a plating via is formed in the through hole to electrically connect the first and the first a second circuit layer; and forming on the surface of the third dielectric layer and the first circuit layer a first insulating protective layer is formed with an opening to expose a portion of the surface of the electrode structure, and a second insulating protective layer is formed on the surface of the fourth dielectric layer and the second wiring layer to expose the second wiring layer Part of the table • face. According to the above method, the substrate is an insulating plate, a metal plate, a ceramic substrate or an inner circuit board having a line; the first and second dielectric layers are filled between the opening and the semiconductor wafer to form the semiconductor The wafer is fixed in the opening; the resistor is a thermal resistance material whose resistance value reacts rapidly to temperature, and the thermal resistance material is platinum, copper or nickel. According to the above method, the thermally conductive structure and the first conductive structure are formed by: forming a first conductive layer on the inactive surface of the semiconductor wafer on the surface of the first dielectric layer and the first opening thereof, and Forming a second conductive layer on the surface of the second dielectric layer 10110304 1331675 and the surface of the electrode pad in the second opening; forming a first resist layer on the surface of the first conductive layer and forming a first opening Exposing the first conductive layer in the first opening, forming a second resist layer on the surface of the second conductive layer, and forming a second opening to expose the second conductive in the second opening Forming the heat conducting structure on the surface of the first conductive layer and the first opening in the first opening, and forming the first surface on the second conductive layer and the second opening in the second opening a conductive structure; and removing the first and second resist layers to expose the first and second conductive layers. The resistor is formed by: forming a third resist layer on the surface of the first conductive layer, and forming a third opening in the third resist layer to expose the first conductive layer and the heat conducting structure; Forming the resistor to connect the resistor to the thermally conductive structure; and removing the third resist layer and the first conductive layer covered thereby, and the fourth resist layer and the second conductive layer covered thereby. The first and second circuit layers and the plating vias are formed by: Φ on the surface of the third dielectric layer, the surface in the third opening of the third dielectric layer, and the third opening a surface of the resistor, a surface of the fourth dielectric layer, a surface of the fourth opening of the fourth dielectric layer, and a surface of the first conductive structure in the fourth opening, formed in the through hole a third conductive layer is formed on the surface of the third conductive layer, and a fifth opening is formed in the fifth resistive layer to expose the third opening, the fourth opening and the through hole; Forming the first and second circuit layers and the plated via holes in the fifth opening, and forming the electrode structure in the first circuit layer to electrically connect the resistor, and forming the second conductive structure in the second circuit layer Electrically connecting the 11110304-conductive structure; and removing the electrical layer. The third layer and the third layer of the present invention are modified by the semi-conductance of the invention, and the temperature of the operation is sensed by the electrode and the resistance. ^ ^ ^ ^; X "J# 1 ^ + Monitoring and monitoring, the semiconductor wafer temperature is carried out [Embodiment] (4) The normal operation of the + conductor q. The following is a specific embodiment, and those having ordinary knowledge in the technical field can be said by the present invention; within the square; within the light: "understand the other advantages and effects of the present invention." - Circuit:::: The upper A to 1 N diagram is a schematic cross-sectional view of a circuit board coating method with a temperature sensing element according to the present invention. As shown in FIG. 1A, a substrate having a first surface 1 is provided, and the substrate body 10 is provided. The substrate body 1 is an insulating plate, =, a ceramic substrate or an inner circuit board having a line, and has an opening 1 贯穿 extending through the first and first surfaces 1a, 10b. The semiconductor wafer U has a semiconductor surface U and an inactive surface lib', and the active surface 11a has a plurality of electrodes 塾 (1); the first surface 1 〇 a of the substrate body 10 The inactive surface lib of the semiconductor wafer n is formed with a first dielectric layer 12a', and a second dielectric layer 12b' is formed on the two surfaces 10b of the substrate body 1 and the active surface 11a of the semiconductor wafer u. The first and second dielectric layers 12al2b are filled in the opening 100 and half Between the bulk wafers u, the semiconductor wafer 11 is fixed in the opening 1 110. 110304 12 1331675 As shown in FIG. 1B, at least one first opening 121a is formed in the first dielectric layer 12a. Exposing the inactive surface lib' of the semiconductor wafer n and forming a plurality of second openings 12 in the second dielectric layer 12b to correspondingly expose the electrode pads n J of the semiconductor wafers 1 i. As shown in FIG. 1C A first conductive layer 13a is formed on the surface of the first dielectric layer 12a and the first conductive layer 13a, and a first resistive layer is formed on the surface of the first conductive layer 13a. 14a, and having a first opening 141a to expose the first conductive layer 13a in the first opening i2ia: an electrode pad of the semiconductor wafer 11 in the surface of the second dielectric layer 12b and the first opening 122b thereof A second conductive layer 13b is formed on the surface of the 111, and a second resist layer 14b is formed on the surface of the second conductive layer 13b, and a second opening 142b is formed to expose the second conductive layer 13b in the second opening 122b. As shown in FIG. 1D, the first conductive layer 13 & The surface of the hole 121a and the first opening 14la forms a heat conducting structure 15 such that the heat conducting structure 15 contacts the inactive surface 11M of the semiconductor wafer u and forms the surface on the surface of the second opening 122b and the second opening 14 a conductive structure 16 electrically connects the first conductive structure 16 to the electrode pad 111 of the semiconductor wafer 11. As shown in FIG. 1E, the first and second resist layers 14 & 14b are subsequently removed. First and second conductive layers 13a, 13b, and a heat conducting structure 15 and a first conductive structure 16. - as shown in FIG. 1F, a third resist layer 14c is formed on the surface of the first conductive layer 13a, and a third opening U3c 110304 13 is formed in the third resist layer 14c to expose the first conductive; η el3a And the thermal structure 15, and a fourth resistance is formed on the surface of the 哕篦-eight electrical layer m: the dielectric layer 16 and the second conductive layer 13b. ^盍 The younger-conducting structure is as shown in Fig. 1 'by the third opening 143c of the first conductive layer i4c, the second 3a is such that the third resistor 17 is connected to the heat conducting structure and the private resistance 17' The electrical temperature is fast reacted, and the resistor 17 is a resistance value to the thermal resistance material as a temperature sensing element, and the fourth=:V removes the third resistive layer i4c And the covered spears W: a to pass out the first dielectric layer 12a and the resistor 17 to form the second dielectric layer 13b of the second dielectric layer to expose the first layer 12b and the first conductive layer Structure 16. The surface of the first dielectric layer 12a and the resistor 17 123c* 0 s 12c are sub-formed with a plurality of third openings*. The third opening 123c of the blade exposes a portion of the resistor 17 The dielectric layer 12b and the surface portion of the first conductive structure 16 are: 1% layer 12d' and formed with a plurality of fourth openings 124d, wherein the four openings 124d expose portions of the first conductive structure 16 Table 4 = formed through the substrate body 1 第一, first, second, third and 介, layer called 121), this 12 (1 through hole 1 〇 1. dielectric ^ 21J, shown in the first a surface of the third dielectric layer 12C, a surface of the second opening 123c of the third middle c and a partial surface of the third opening 123c to the person 17 and a surface of the fourth dielectric layer 12d, the first a surface of the fourth opening 124d of the second opening and a fourth surface of the fourth opening 110304 14 1331675 - _^, a surface of the conductive layer 16 is formed, and a third conductive layer 13c is formed in the through hole ι01. Then, a surface of the third conductive layer I3c is formed, and a fifth opening L is formed in the fifth resist layer 14e to form the third opening 123c and the fourth opening 24d. And through holes (8). : L is shown in the third conductive layer c on the surface of the third dielectric layer 12c, and the first circuit layer is formed in the third opening 145e in the third opening 123c to form a plurality of pairs The electrode junction is connected to the electric p and 17 in a % manner, and the second wiring layer 18b' is formed in the fourth dielectric layer 12 2 and formed in the fourth opening md: The first conductive structure 16 is connected, and the electric money conducting hole 18c is formed in the through hole 101 to electrically connect the contact road layer and the HXuandi circuit layer 18b to be electrically connected.
2弟1M圖所示’移除該第五阻層14e及其所覆蓋之 “電層13C以露出該第-線路層18a、第二線路層18b 及電鍍導通孔18c。 如第IN圖所示，於該第三介電層…及第一線路声 …表面形成有-[絕緣保護層心，並形成開孔^ 以露出該電極結構181a之部份表面以作為電阻量測點， 又於該第四介電層12d及第二線路層⑽表面形成有第二 絕緣保護層19b，並形成有開孔⑽以露出該第二線路 層18b之部份表面（如電性連接墊i8ib)。 本發明復提供-種具溫度感測元件之電路板，係包 110304 15 1331675 括：基板本體10,係具有一第一表面1〇a與第二表面i〇b， 亚具有-貫穿該第一及第二表面1〇a l〇b之開口 ι〇〇，該 基板本體1〇為-絕緣板、金屬板、陶究基板或具有線路 之内層電路板’半導體晶片】卜係容置於該開口⑽尹， 且具有-主動面lla及非主動面llb’於該主動面⑴且 有複數電極塾⑴；第-介電層12a，係設於該基板本體 之第-表面10a及該半導體晶片u之非主動面心 且具有至少一第一開孔121a以露出該半導體晶片U之非 主動面iib;導熱結構15,係設於該苐一介電層i2a之第 一，孔121a中；複數電阻17 ’係設於該些導熱結構15 及弟一介電層12a表面，且該些電阻17分別對應連接該 些導熱結構15;第三介電I 12c，係設於該第一介電層 12a表面及電阻17表面，並具有複數第三開孔a允，苴 :部份成對之第三開孔123c露出該電阻17之部份表面:、 第=線路層18a，係設於該第三介電層12c表面，並於該 些第三開1 123c中形成具有複數成對之電極結構⑻& 以，性連接該電阻17;以及第一絕緣保護層19a，係設於 該第三介電層12c及第一線路層18a表面，並具有開孔 胸以露出該電極結構ma之部份表面作為電阻量測 點。 依上述之結構，復包括：第二介電層12b，係設於該 基板本體10之第二表面1〇b及該半導體晶片丨丨之主動面 lla’且具有複數第二開孔122b以對應露出該些半導體晶 片1 1之电極墊111，第一導電結構i 6，係設於該第二介 110304 16 1331675 電層12b之第二開孔122b中以電性連接該電極塾⑴· 第四介電層12d，係設於該第二介電層咖及第 ”士 構16表面’並具有複數第四開孔md，其中部份之二。 開孔124d露出該第一導電結構16之部份表面二 層⑽，係設於該第四介電層12d表面，並於該第 124d中形成第二導電結構182b以電性連接該第一導"士 構16;電鍍導通孔18c，係貫穿該基板本體1〇 :、。 第二、第三及第四介電層12a，12b l2c l2d 第一及第二線路層18】8 电汪連接該 A 絕緣保護層⑽， 知叹於該第四介電声彳β铱_ 包層12d及弟一線路層18b表 開孔190b以露出嗜筮-妗,々故… 卫具有 接塾竭。 層⑽之部份表面（如電性連 當該半導體晶片^於運作而產生高 於該半導體晶片U之非主叙而^猎由接觸 m Ρ ΛΑ ^ ,, ., b的導熱結構15直接减 應咖度的變化亚傳導至兮雷 信H u A 而該電阻17係為電阻 值對 >皿度反應快速之熱電轉料，藉由該電極 以1測電阻1 7的電卩且佶蜱, 、。構181 a a t 阻值變化，或直接由第一、第-綠，々 層18a，18b直接量測泰阳〗7 AA兩 弟一線路 使里而电阻17的電阻值，即得知 晶片11於運作時的溫度變化 ”導組 時的溫度監控，以確㈣主、“對該+ ¥粗晶片11做即 t以確保该+導體晶片u 五避免該半導體晶片n 吊運作， ,nH 於同連運异時因高熱而損壞。 本發明之具溫度感測 半導體晶片連置有電阻路板及其製法，係於該 導體晶片於運作時實卜量測電阻值’以得知該半 m 皿度，進而可對該半導體晶片做即 17 110304 日:的溫度監控’以確保該半導體晶片可以正 免該半導體晶片於高速運算時因高熱而損壞。丨工避 惟以上所述之具體實施例，僅係用以例釋本發明之特 點及功效，而非用以限定本發明之可實施範疇，在未脫離 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 範圍所涵蓋。 【圖式簡單說明】 第1A至1N圖係為本發明之埋入式晶片溫度感測器製 法之剖面示意圖。 【主要元件符號說明】 10 基板本體 10a 第 一表面 10b 第二表面 100 開 π 101 通孔 11 半導體晶片 11a 主動面 lib 非主動面 111 電極墊 12a 第 一介電層 121a 第一開孔 12b 第 二介電層 122b 第二開孔 12c 第 三介電層 123c 第三開孔 12d 第 四介電層 124d 第四開孔 13a 第 一導電層 13b 第二導電層 13c 第 三導電層 14a 第一阻層 141a 第 -開D 14b 第二阻層 142b 第 二開口 14c 苐三阻層 143c 第 三開口 110304 18 1331675 14d 第四阻層 14e 第五阻層 145e 第五開口 15 導熱結構 16 %一導電結構 17 電阻 18a 第一線路層 181a 電極結構 18b 第二線路層 181b 電性連接墊 182b 第二導電結構 18c 電鍍導通孔 19a 第一絕緣保護層 190a 開孔 19b 第二絕緣保護層 190b 開孔 19 110304The second resistor layer 14e and the "electric layer 13C covered by the fifth resistor layer 14e and the "electric layer 13C" are exposed to expose the first wiring layer 18a, the second wiring layer 18b, and the plating via hole 18c as shown in Fig. 1M. And the surface of the third dielectric layer ... and the first line is formed with - [insulating protective layer core, and forming an opening ^ to expose a part of the surface of the electrode structure 181a as a resistance measuring point, and A second insulating protective layer 19b is formed on the surface of the fourth dielectric layer 12d and the second wiring layer (10), and an opening (10) is formed to expose a part of the surface of the second wiring layer 18b (such as the electrical connection pad i8ib). The invention provides a circuit board for a temperature sensing component, the package 110304 15 1331675 includes: a substrate body 10 having a first surface 1a and a second surface i〇b, having a through-the first The opening of the second surface 1〇al〇b, the substrate body 1 is an insulating board, a metal plate, a ceramic substrate or an inner layer circuit board having a line, and a semiconductor wafer is placed in the opening (10) And having an active surface 11a and a non-active surface 11b' on the active surface (1) and having a plurality of electrodes 塾 (1); The electrical layer 12a is disposed on the first surface 10a of the substrate body and the inactive surface of the semiconductor wafer u and has at least one first opening 121a to expose the inactive surface iib of the semiconductor wafer U; The first resistor is disposed in the first hole 110a of the first dielectric layer i2a; the plurality of resistors 17' are disposed on the surface of the heat conducting structure 15 and the dielectric layer 12a, and the resistors 17 respectively connect the heat conducting portions The third dielectric I 12c is disposed on the surface of the first dielectric layer 12a and the surface of the resistor 17, and has a plurality of third openings a, and a portion of the third opening 123c is exposed. a part of the surface of the resistor 17 is provided on the surface of the third dielectric layer 12c, and formed in the third opening 1 123c with a plurality of pairs of electrode structures (8) & The resistor 17; and the first insulating protective layer 19a are disposed on the surface of the third dielectric layer 12c and the first wiring layer 18a, and have an opening chest to expose a part of the surface of the electrode structure ma as a resistance measuring point. According to the above structure, the second dielectric layer 12b is disposed on the substrate body 10 a surface 1〇b and an active surface 11a' of the semiconductor wafer and having a plurality of second openings 122b corresponding to the electrode pads 111 exposing the semiconductor wafers 11. The first conductive structure i6 is disposed in the first The second dielectric hole 12b of the second layer 110b 16 1331675 is electrically connected to the electrode 塾 (1) · the fourth dielectric layer 12d, and is disposed on the second dielectric layer and the surface of the first dielectric layer There are a plurality of fourth openings md, two of which are part. The opening 124d exposes a portion of the surface of the first conductive structure 16 (10), is disposed on the surface of the fourth dielectric layer 12d, and forms a second conductive structure 182b in the 124d to electrically connect the first conductive "School structure 16; electroplating via hole 18c, through the substrate body 1 〇:,. Second, third and fourth dielectric layers 12a, 12b l2c l2d first and second circuit layers 18] 8 electrically connected to the A insulating protective layer (10), knowing the fourth dielectric sonar β铱_ package The layer 12d and the first circuit layer 18b open the hole 190b to expose the embarrassing-妗, so that the guard has exhausted. A portion of the surface of the layer (10) (such as an electrical connection when the semiconductor wafer is operated to produce a higher thermal conductivity than the semiconductor wafer U is directly reduced by the contact of m Ρ , ^ , , , b The change in the degree of coffee is sub-conducted to 兮Rayson H u A and the resistor 17 is a resistance value pair > the thermoelectric conversion of the fast response of the dish, by which the electrode is measured with a resistance of 1 7 and 佶蜱, 181 aat resistance change, or directly from the first, first-green, 々 18a, 18b directly measured Taiyang 〗 7 AA two brothers a line to make the resistance of the resistor 17, that is, the wafer 11 temperature change during operation "temperature monitoring at the time of the group, to confirm (4) main, "doing the + 粗 粗 11 to ensure that the + conductor wafer u five to avoid the semiconductor wafer n hang operation, nH The same time difference is caused by high heat. The temperature sensing semiconductor wafer of the present invention is connected with a resistance circuit board and a manufacturing method thereof, and the resistance value of the conductor wafer is measured during operation to know the half. The degree of the dish, which in turn can be used to ensure the temperature of the semiconductor wafer, that is, 17 110304: The semiconductor wafer can be prevented from being damaged by high heat during high-speed operation. The specific embodiments described above are merely used to illustrate the features and functions of the present invention, and are not intended to limit the implementation of the present invention. Any equivalent changes and modifications made by the disclosure of the present invention should be covered by the following claims without departing from the spirit and scope of the invention. 1A to 1N are schematic cross-sectional views showing a method of manufacturing a buried wafer temperature sensor of the present invention. [Main element symbol description] 10 substrate body 10a first surface 10b second surface 100 is opened π 101 through hole 11 semiconductor wafer 11a active surface lib inactive surface 111 electrode pad 12a first dielectric layer 121a first opening 12b second dielectric layer 122b second opening 12c third dielectric layer 123c third opening 12d fourth dielectric layer 124d Fourth opening 13a first conductive layer 13b second conductive layer 13c third conductive layer 14a first resistive layer 141a first-open D 14b second resistive layer 142b second opening 14c Layer 143c third opening 110304 18 1331675 14d fourth resistive layer 14e fifth resistive layer 145e fifth opening 15 heat conducting structure 16% conductive structure 17 resistor 18a first circuit layer 181a electrode structure 18b second circuit layer 181b electrical connection pad 182b second conductive structure 18c plating via 19a first insulating protective layer 190a opening 19b second insulating protective layer 190b opening 19 110304