1328842 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作應變矽金氧半導體電晶體的方法。 【先前技術】 隨著半導體製程之線寬的不斷縮小，MOS電晶體之尺 寸亦不斷地朝向微型化發展，然而目前半導體製程之線寬 籲 已發展至瓶頸的情況下，如何提升載子遷移率以增加MOS 電晶體之速度已成為目前半導體技術領域中之一大課題。 在目剞已知的技術中，已有使用應變石夕（strained siiicon)作 為基底的MOS電晶體’例如利用矽鍺（SiGe)的晶格常數與 單晶石夕（single crystal Si)不同的特性，使矽鍺磊晶層產生結 構上應變而形成應變矽。由於矽鍺層的晶格常數(lattice constant)比石夕大’這使得石夕的帶結構（band structure)發生改 變，而造成載子移動性增加，因此可增加PMOS電晶體的 • 載子遷移速度。 請參考第1圖至第4圖，第1圖至第4圖為習知利用 選擇性磊晶成長製作一應變矽金氧半導體電晶體的方法示 .意圖。如第1圖所示’首先提供一半導體基底1〇，例如一 石夕基底，且半導體基底10上包含有一閘極結構12。其中， 閘極結構12包含有一閘極介電層（gate dielectric) 14以及一 • 位於閘極介電層14上的閘極16。接著進行一離子佈植製 7 1328842 — 程，將一較低劑量的P型或N型摻質以較低的佈植能量植 入半導體基底中，以於閘極結構12周圍的半導體基底 中形成一輕摻雜没極(lightly doped drain，LDD)24。然後 形成一偏位側壁子18於閘極結構12的侧壁，並接著形成 一側壁子2〇於偏位側壁子18的周圍。一般而言，閘極介 電層14係由二氧化石夕（silicon dioxide, Si〇2)所構成，閘極 16係由推雜多晶石夕（doped polysilicon)所構成，而偏位側壁 φ 子18與側壁子2〇則係分別由氧化物與氮化物-氧化物所構 成。此外，閘極結構12所在之主動區域(active area)外圍的 半導體基底10内另環繞有一淺溝隔離(shallow trench isolation, STI)22。 如第2圖所示，隨後進行另一離子佈植製程，將一較 高劑量的P型或N型摻質以較高的佈植能量植入半導體基 底1〇中，以於輕摻雜汲極24周圍形成一源極/汲極區域 • 26,進而完成一 P型金氧半導體(PMOS)電晶體或N型金氧 半導體(NM0S)電晶體的製作。緊接著於p型或N型摻質 植入後進行一快速升溫退火製程’利用9〇〇。〇至i〇〇〇°c的 溫度來活化植入半導體基底1〇的摻質，並同時修補於離子 佈植製程中受損之半導體基底10表面的晶格結構。 如第3圖所示’接著進行一蝕刻製程，利用閘極結構 . 12、偏位側壁子18與側壁子20當作遮罩，以於閘極16頂 8 1328842 部以及源極/沒極區域26中形成一凹槽28。然後進> 烤（baking)製程，以利用約700。(：至95(TC的溫度來^一供 留於凹槽28表面的氧化物並修補原本粗糙的凹^ 28 如第4圖所示，接著於烘烤製程結束後進行一選擇性 磊晶成長（selective epitaxial growth, SEG)製程，以於凹柃 28内形成一由鍺化矽或碳化矽所構成的磊晶層3〇，進而二 成習知一應變矽金氧半導體電晶體的製作。其中，所形= 的磊晶層可根據電晶體的型態分別由不同物質所構成，兴 例來說，如所製作的電晶體係為_ PM〇s電晶體，所形成 的蠢晶層可由錄化石夕所構成’而如製作的電晶體係為一 NMOS電晶體，則所形成的磊晶層可由碳化矽所構成。 值得注意的是，上述之製程步驟通常具有以下缺點。 首先，習知在形成磊晶層之前會進行一蝕刻製程以於基底 # 的源極/没極區域中形成一凹槽，如第3圖所示。此步驟雖 可提供一成長的表面給後續形成的磊晶層，佴會同時使源 極/及極區域的摻質集中在凹槽的邊緣區域，造成摻質分佈 不均並影響MOS電晶體的效能。 其次，習知在源極/沒極區域形成後會進行一快速升溫 退火製程來將摻雜於源極與沒極區域的掺質擴散出來，達 到活化(activation)摻質的目的。在正常情況下，活化的摻 9 1328842 質均需具有完美的鍵結。然而，在形成磊晶層前所進行的 烘烤製程通常會使用一較快速升溫退火製程更低的後溫來 去除凹槽表面殘留的氧化物並修補原本較粗糖的凹槽表面 (surface roughness)。雖然此烘烤製程可提供後續形成磊晶 層時一個良好的成長表面，但烘烤製程所伴隨的後溫會破 壞摻質中的鍵結，造成阻值的提昇並導致去活化 (deactivation)的現象。 請參照第5圖與第6圖，第5圖為習知PMOS電晶體 於不同烘烤溫度下之操作電流(Ion)與漏電流(I〇ff)示意 圖。第6圖則為PMOS電晶體於不同烘烤溫度下的阻值 (resistance)示意圖。如第5圖所示，隨著烘烤製程溫度的 提升，PMOS電晶體中的操作電流會呈現相對的遞降 (degradation)。舉例來說，在相同漏電流的條件下，如將未 進行任何烘烤製程的元件當作一參考點（reference p〇int)， 進行750 C烘烤製程的元件會呈現約7%的操作電流遞降， 而進行850 C烘烤製程的元件則會呈現約13 6%的遞降。由 於在相同的電壓下’元件中的電阻值會隨著操作電流的降 低而提升，因此隨著烘烤製程溫度的增加，元件中的電阻 值也會隨著增加。如第6圖所示’隨著烘烤製程的溫度提 升到約850 C ’PMOS電晶體的阻值也會跟著增加到一最高 點。如同先前所述，阻值的提升會導致去活化的現象並破 裒摻貝中的鍵結。然而’由於進行選擇性蟲晶成長前的烘 U28842 ::=:=:::= 【發明内容】 本發明之主要目的係提供一種製作應變矽金氧半導體 的方法’以解決上述於進行烘烤製程後容易因摻質中鍵結 的破壞而導致去活化現象的問題。 本發明係揭露一種製作應變矽金氧半導體電晶體的方 法。首先提供一半導體基底，然後形成一閘極結構於該半 導體基底上、一側壁子於該閘極結構周圍以及一源極/汲極 區域於該侧壁子周圍之該半導體基底中。接著進行一第一 快速升溫退火(rapid thermal anneal，RTA)製程，以活化該源 極/汲極區域中之摻質。然後進行一蝕刻製程，以於該閘極 結構上及周圍分別形成一凹槽，並進行一選擇性磊晶成長 (selective epitaxial growth，SEG)製程，以於該等凹槽中形成 一蠢晶層。緊接著進行一第二快速升溫退火製程，以重新 定義該源極/汲極區域中摻質的分佈並修復摻質中受損的 鍵結。 根據本發明之較佳實施例，本發明係於磊晶層形成後 再進行另一快速升溫退火製程來改善習知因烘烤製程所伴 隨的後溫而容易導致摻質去活化的問題。值得注意的是， 1328842 本發明所進行的第二次快速升溫退火製程除了可用來重新 定義（redefine)基底中摻質的分佈，又可同時修復摻質中因 烘烤製程的後溫而毁損的鍵結，進而提昇M〇s電晶體的整 體效能。 【實施方式】 凊參考第7圖至第10圖，第7圖至第1()圖為本發明 較佳實施例洲選擇性蠢晶成長製作_應變_金氧半導體 電晶體的方法示意圖。如第7圖所示，首先提供一半導體 基底4〇，例如一石夕基底，且半導體基底40上包含有-閘 極結構42。其中’閘極結構42包含有—閘極介電層（柳 此以㈣44以及—位於閘極介電層44上的閘極46。接著 進灯離子佈植，將__較低劑量的p型或N型推質以 較低的佈植能量植入半導體基底4〇中以於問極結構心 周圍的半導體基底40中形成一輕穆雜沒極(M_y doped drain，LDD)54。然後形志一值 的側壁，並接著形成一侧壁子=子48 一 埜于50於偏位側壁子48的周圍。 -般而言’閘極介電層44可由二氧化石夕⑽⑽一， Si02)等絕緣材料所構成，閘極46可由摻雜多晶州㈣ polysili⑽)等導電材料所構成，而偏位側壁子Μ與側壁子 5 0則可分別由氧化物與i化物.氧化物等絕緣材料所構 成。此外，閘極結構42所在之主動區域啡耕圍的 半導體基底4G内另賴有—淺溝隔離(sti)52等之絕緣材料。 12 1328842 • 如第8圖戶斤示’然後進行另-離子佈植製程，將一較 兩劑量的P型或N型摻質以較高的佈植能量植入半導體基 底40中，以於輕摻雜沒極54周圍形成一源極/及極區域 56’進而完成- P型金氧半導體(pM〇s)電晶體或n型金氧 半導體(NMOS)電晶體的製作。緊接著於p型或n型擦質 植入後進行一快速升溫退火製程，利用9〇〇。(：至的 溫度來活化植入半導體基底4〇的摻質，並同時修補於離子 修佈植製程中受損之半導體基底4〇表面的晶格結構。根據本 發明之較佳實施例，快速升溫退火製程的時間係介於忉秒 至30秒。 y 如第9圖所示，接著進行一蝕刻製程，利用閘極結構 42、偏位側壁子48與側壁子50當作遮罩，以於閘極仏頂 部以及源極/汲極區域56中分別形成一凹槽58。然後進行 一烘烤(baking)製程，以利用約了㈧它至今咒七的溫度來去 _ 除殘留於凹槽58表面的氧化物並修補原本粗輪的凹槽58 表面。 如第10圖所示，接著於烘烤製程結束後進行一選擇 性磊晶成長（selective epitaxial growth，Seg)製程，以於各凹 槽58内形成一由鍺化矽或碳化矽所構成的磊晶層6〇。其 • 所形成的蟲晶層60可根據電晶體的型態分別由不同物 貝所構成。舉例來說，如所製作的電晶體係為一 PM〇s電 13 1328842 •日日日體，所形成的遙晶層可由鍺切等物f所構成，而如製 作的電晶體係為-NM〇S電晶體，則所形成㈣晶層可由 碳化矽等物質所構成。 接著於蟲晶層60形成後進行另一快速升溫退火製程， 利用900C至1UKTC的溫度來再次活化植入基底的推質。 如同先⑽來形成源極/沒極區域所進行的快速升溫退火 製程，此快速升溫退火製程的時間同樣係介於1〇秒至％ 秒。隨後，本發明可於快速升溫退火製程完成後再進行一 毫秒退火（millisecond anneal)製程，以利用1〇〇〇。〇至135〇 °C的高溫在不加賴面深度的條件下將所有摻質的固溶度 ⑽ubiHty)提昇到最高。根據本發明之較佳實施例，此毫= 退火製程可為-雷射退火製程，且毫秒退火製程的時間係 介於100毫秒至1微秒。 籲值的疋由於形成i晶層前所進行的供烤製程 通常會破壞換質中的鍵結並造成去活化的現象，因此本發 明係於蟲晶層形成後再進行另一快速升溫退火製程來改善 此問題。根據本發明之較佳實施例，此第二次快速升溫退 火製程除了可用來重新定義（redefine)基底中摻質的分佈， 又可同時修復換質中因埃烤製程的後溫而毀損的鍵結，進 而提升電晶體的整體效能。 14 1328842 根據本發明之另一實施例，上述製程又可應用於互補 式金氧半導體電晶體的製作。如第11圖至第13圖所示， 首先形成一個以淺溝隔離（shallow trench isolation，STI) 106 區隔出NMOS電晶體區i〇2以及PMOS電晶體區104的半 導體基底100，且各NMOS電晶體區102及PMOS電晶體 區104上設有一閘極結構。其中，nm〇S閘極結構包含一 NMOS閘極108以及一設於NMOS閘極108與半導體基底 _ 1〇0之間的閘極介電層114，PMOS閘極結構則包含一 PMOS閘極110以及一設於pM〇s雜11〇與半導體基底 100之間的閘極介電㉟114。接著分別進行一離子佈植製 程’將一較㈣4的？型與N獅質各植人半導體基底100 中以於ISfMOS Pg極結構與pM〇s間極結構周圍的半導體 基底100中各形成—輕摻雜没極US與Up。缺後於丽 閘極108與PMOS閘坧11Λ 蚀110的側壁表面依序形成一偏位側 壁子112與側壁子U3。 然後依序進行另—離子佈植製程，分別將一較高劑量 的P U1摻質植入半導體基底1⑽中，以於輕摻雜汲 極118與119周圍形成—; ^ 原極/汲極區域116與117。接著 進行一快速升溫退火制炉 教矛芏’利用900〇C至1UKTC的溫度來 活化植入基底的摻質，廿 並同時修補於離子佈植製程中受損 之半導體基底100表面的晶格結構。 15 1328842 •如第12圖所示，接著進行一蝕刻製程，以於nm〇s 閘極108的頂部與源極/汲極區域116中形成一凹槽12〇， 以及於PMOS閘極110的頂部與源極/汲極區域117中分別 形成一凹槽122。隨後進行一烘烤製程，利用約7〇〇它至 950°C的溫度來去除殘留於凹槽120及122表面的氧化物並 修補原本粗糙的凹槽表面。 如第13圖所示，接著於烘烤製程結束後分別進行一選 擇性磊晶成長（selective epitaxial growth，SEG)製程，以於 NMOS電晶體區102的凹槽120内形成一由碳化矽所構成 的磊晶層124，以及於PM0S電晶體區1〇4的凹槽122内 形成一由緒化矽所構成的磊晶層126。 接著於磊晶層124與126形成後進行另一快速升溫退 火製程，利用90(TC至1100Ϊ的溫度來再次活化植入基底 • 的摻質。如同先前用來形成源極/汲極區域所進行的快速升 溫退火製程，此快速升溫退火製程的時間同樣係介於1〇秒 至30秒。隨後，本發明可於第二次快速升溫退火製程完成 後再進行一毫秒退火(millisecond anneai)製程，利用1〇⑽ °C至1350eC的高溫在不加深接面深度的條件下將所有摻質 的固溶度（solubility)提昇到最高。根據本發明之較佳實施 例，此毫秒退火製程可為一雷射退火製程，且毫秒退火製 '裎的時間係介於100毫秒至1微秒。至此即完成本發明另 1328842 一實施例互補式金氧半導體電晶體的製作。 綜上所述，由於習知在源極/汲極區域形成凹槽來填入 磊晶層的步驟通常會造成摻質分佈不均，且形成磊晶層前 所進行的烘烤製程會破壞摻質中的鍵結並造成去活化的現 象，因此本發明係於磊晶層形成後再進行另一快速升溫退 火製程來改善此問題。根據本發明之較佳實施例，此第二 次快速升溫退火製程除了可用來重新定義（redefine)基底中 摻質的分佈，又可同時修復摻質中因烘烤製程的後溫而毁 損的鍵結，進而提昇MOS電晶體的整體效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第4圖為習知利用選擇性磊晶成長製作一應變矽 金氧半導體電晶體的方法示意圖。 第5圖為PMOS電晶體於不同烘烤溫度下之操作電流與漏 電流示意圖。 第6圖為PMOS電晶體於不同烘烤溫度下的阻值示意圖。 第7圖至第10圖為本發明較佳實施例利用選擇性磊晶成長 製作一應變矽金氧半導體電晶體的方法示意圖。 第11圖至第13圖為本發明另一實施例利用選擇性磊晶成 17 1328842 長製作一互補式金氧半導體電晶體的方法不意圖。1328842 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a strained gold-oxide semiconductor transistor. [Prior Art] As the line width of the semiconductor process continues to shrink, the size of the MOS transistor is constantly moving toward miniaturization. However, how to improve the carrier mobility in the case where the line width of the semiconductor process has been developed to the bottleneck Increasing the speed of MOS transistors has become a major issue in the field of semiconductor technology. Among the known techniques, there have been MOS transistors using strained siiicon as a substrate, for example, using lattice constants of germanium (SiGe) different from single crystal Si. So that the germanium epitaxial layer is structurally strained to form strain enthalpy. Since the lattice constant of the ruthenium layer is larger than that of Shi Xia, which changes the band structure of Shi Xi, and the carrier mobility increases, the carrier migration of the PMOS transistor can be increased. speed. Please refer to FIG. 1 to FIG. 4, and FIG. 1 to FIG. 4 are diagrams showing a conventional method for fabricating a strain 矽 MOS transistor by selective epitaxial growth. As shown in Fig. 1, a semiconductor substrate 1 is first provided, such as a substrate, and a semiconductor structure 10 includes a gate structure 12. The gate structure 12 includes a gate dielectric 14 and a gate 16 on the gate dielectric layer 14. An ion implantation process is then performed to implant a lower dose of P-type or N-type dopant into the semiconductor substrate with lower implantation energy for formation in the semiconductor substrate surrounding the gate structure 12. A lightly doped drain (LDD) 24. A biasing sidewall 18 is then formed on the sidewall of the gate structure 12 and a sidewall 2 is then formed around the deflecting sidewall 18. In general, the gate dielectric layer 14 is composed of silicon dioxide (Si 2 ), and the gate 16 is composed of doped polysilicon, and the lateral sidewall φ The sub- 18 and the side wall 2 are respectively composed of an oxide and a nitride-oxide. In addition, a shallow trench isolation (STI) 22 is surrounded by the semiconductor substrate 10 on the periphery of the active area where the gate structure 12 is located. As shown in Fig. 2, another ion implantation process is subsequently performed to implant a higher dose of P-type or N-type dopant into the semiconductor substrate 1 with higher implantation energy for light doping. A source/drain region 26 is formed around the pole 24 to complete the fabrication of a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NM0S) transistor. Immediately after implantation of the p-type or N-type dopant, a rapid thermal annealing process was performed using 9 〇〇. The temperature of i〇〇〇°c is applied to activate the dopant implanted in the semiconductor substrate and simultaneously repair the lattice structure of the surface of the damaged semiconductor substrate 10 in the ion implantation process. As shown in Fig. 3, 'an etching process is followed by a gate structure. 12. The biased sidewalls 18 and the sidewalls 20 are used as masks to cover the top of the gate 16 and the source/drain region. A recess 28 is formed in 26. Then go to the > baking process to take about 700. (: to 95 (the temperature of TC is used to leave the oxide on the surface of the groove 28 and repair the original rough recess ^ 28 as shown in Fig. 4, followed by a selective epitaxial growth after the end of the baking process) (selective epitaxial growth, SEG) process for forming an epitaxial layer 3〇 composed of antimony telluride or tantalum carbide in the concavity 28, and then forming a conventional strained germanium oxynitride transistor. The epitaxial layer of the shape = can be composed of different substances according to the type of the transistor. For example, if the fabricated electro-crystal system is _ PM〇s transistor, the formed stupid layer can be recorded. If the electromorphic system is made of an NMOS transistor, the epitaxial layer formed may be composed of tantalum carbide. It is worth noting that the above-mentioned process steps generally have the following disadvantages. An etching process is performed before the epitaxial layer is formed to form a recess in the source/nothotropic region of the substrate #, as shown in Fig. 3. This step provides a grown surface to the subsequently formed epitaxial layer. , 佴 will also make the source / and polar regions doping In the edge region of the groove, uneven distribution of dopants is affected and the performance of the MOS transistor is affected. Secondly, after the formation of the source/drain region, a rapid temperature annealing process is performed to dope the source with The dopant in the immersed region diffuses out to achieve the purpose of activating the dopant. Under normal conditions, the activated doped 9 1328842 material needs to have perfect bonding. However, the baking is performed before the epitaxial layer is formed. The baking process usually uses a lower temperature of the faster temperature annealing process to remove residual oxide on the surface of the groove and repair the surface roughness of the original coarser sugar. Although this baking process can provide subsequent formation of epitaxial grains. The layer has a good growth surface, but the post-temperature associated with the baking process destroys the bond in the dopant, causing an increase in resistance and deactivation. Please refer to Figure 5 and Figure 6. Figure 5 is a schematic diagram of the operating current (Ion) and leakage current (I〇ff) of a conventional PMOS transistor at different baking temperatures. Figure 6 is the resistance of a PMOS transistor at different baking temperatures ( Resistance) As shown in Figure 5, as the baking process temperature increases, the operating current in the PMOS transistor exhibits a relative degradation. For example, under the same leakage current conditions, if not Any baking process component is used as a reference point (reference p〇int), the component for the 750 C baking process will exhibit about 7% of the operating current drop, while the component for the 850 C baking process will show approximately 13 6% of the descending. Since the resistance value in the component will increase with the decrease of the operating current at the same voltage, the resistance value in the component will increase as the baking process temperature increases. As shown in Figure 6, the resistance of the PMOS transistor increases to a maximum as the temperature of the baking process increases to approximately 850 C'. As previously stated, an increase in resistance results in deactivation and breaks the bond in the shell. However, 'Because of drying U28842 before selective worm growth> The main object of the present invention is to provide a method for producing a strained strontium oxynitride to solve the above-mentioned baking. After the process, the problem of deactivation is easily caused by the destruction of the bond in the dopant. The present invention discloses a method of fabricating a strained germanium oxynitride transistor. A semiconductor substrate is first provided, and then a gate structure is formed on the semiconductor substrate, a sidewall is disposed around the gate structure, and a source/drain region is in the semiconductor substrate around the sidewall. A first rapid thermal anneal (RTA) process is then performed to activate the dopant in the source/drain region. An etching process is then performed to form a recess on and around the gate structure, and a selective epitaxial growth (SEG) process is performed to form a stray layer in the grooves. . A second rapid temperature annealing process is then performed to redefine the distribution of dopants in the source/drain regions and repair damaged bonds in the dopant. In accordance with a preferred embodiment of the present invention, the present invention is directed to the formation of an epitaxial layer followed by another rapid thermal annealing process to improve the conventional post-temperature associated with the bake process and which tends to cause deactivation of the dopant. It is worth noting that the second rapid temperature annealing process performed by the present invention can be used to redefine the distribution of dopants in the substrate while simultaneously repairing the damage in the dopant due to the post-temperature of the baking process. Bonding, which in turn improves the overall performance of the M〇s transistor. [Embodiment] Referring to Figs. 7 to 10, Figs. 7 to 1() are schematic views showing a method of fabricating a _ strain-metal oxide semiconductor transistor in accordance with a preferred embodiment of the present invention. As shown in Fig. 7, a semiconductor substrate 4, such as a slab substrate, is first provided, and the semiconductor substrate 40 includes a gate structure 42. Wherein the gate structure 42 comprises a gate dielectric layer (the fourth layer 44 and the gate 46 on the gate dielectric layer 44. Then the ion implantation is carried out, and the lower dose p-type is __ Or a N-type pusher is implanted into the semiconductor substrate 4 with a lower implantation energy to form a M_y doped drain (LDD) 54 in the semiconductor substrate 40 around the interpolar structure core. A value of the sidewall, and then forming a sidewall = sub-48 a field 50 around the biased sidewall 48. - Generally speaking, the gate dielectric layer 44 can be made of dioxide (10) (10), Si02, etc. The insulating material is composed of a gate electrode 46 which is made of a conductive material such as doped polycrystalline (4) polysili (10)), and the bias sidewall spacer and the sidewall spacer 50 are respectively made of an insulating material such as an oxide and an oxide. Composition. In addition, the semiconductor substrate 4G in the active region where the gate structure 42 is located has an insulating material such as a shallow trench isolation (s) 52. 12 1328842 • As shown in Figure 8, then perform another ion implantation process to implant a higher dose of P-type or N-type dopant into the semiconductor substrate 40 with higher implantation energy. A source/pole region 56' is formed around the doped pole 54 to complete the fabrication of a p-type gold oxide semiconductor (pM〇s) transistor or an n-type gold oxide semiconductor (NMOS) transistor. Immediately after the p-type or n-type smear implantation, a rapid temperature annealing process was performed, using 9 〇〇. (: a temperature of up to activate the dopant implanted in the semiconductor substrate 4 while simultaneously repairing the lattice structure of the surface of the damaged semiconductor substrate 4 in the ion repair process. According to a preferred embodiment of the present invention, The temperature of the annealing process is between leap seconds and 30 seconds. y, as shown in Fig. 9, an etching process is followed by using the gate structure 42, the lateral sidewalls 48 and the sidewalls 50 as masks. A recess 58 is formed in the top of the gate and the source/drain region 56. Then, a baking process is performed to take advantage of the temperature of the eighth (the eighth) which remains to the surface of the recess 58. The oxide and repair the surface of the groove 58 of the original coarse wheel. As shown in Fig. 10, a selective epitaxial growth (Seg) process is performed after the end of the baking process for each groove 58. An epitaxial layer 6 构成 formed of bismuth telluride or tantalum carbide is formed therein, and the formed wormhole layer 60 may be composed of different kinds of shells according to the type of the transistor. For example, as produced The electro-crystalline system is a PM〇s electricity 13 1328842 • In the Japanese body, the formed crystal layer can be composed of a material such as tantalum, etc., and if the fabricated electro-crystal system is a -NM〇S transistor, the formed (four) crystal layer can be composed of a material such as tantalum carbide. After the formation of the worm layer 60, another rapid temperature annealing process is performed, and the temperature of the implanted substrate is reactivated by using a temperature of 900 C to 1 UKTC. As in the rapid temperature annealing process of forming the source/drain region first (10), this The time for the rapid thermal annealing process is also between 1 sec and % sec. Subsequently, the present invention can be subjected to a millisecond anneal process after the rapid thermal annealing process is completed to utilize 1 〇〇〇 to 135. The high temperature of 〇°C raises the solid solubility (10) ubiHty of all dopants to the highest without increasing the depth of the surface. In accordance with a preferred embodiment of the present invention, the aging process can be a laser annealing process and the time of the millisecond anneal process is between 100 milliseconds and 1 microsecond. The 吁 吁 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋To improve this issue. According to a preferred embodiment of the present invention, the second rapid temperature annealing process can be used to redefine the distribution of the dopant in the substrate, and simultaneously repair the bond damaged by the post-temperature of the eucalyptus process. The junction further enhances the overall performance of the transistor. 14 1328842 In accordance with another embodiment of the present invention, the above process can be applied to the fabrication of a complementary MOS transistor. As shown in FIGS. 11 to 13, first, a semiconductor substrate 100 in which a NMOS transistor region i 〇 2 and a PMOS transistor region 104 are separated by a shallow trench isolation (STI) 106 region is formed, and each NMOS is formed. A gate structure is provided on the transistor region 102 and the PMOS transistor region 104. The gate structure of the nm〇S includes an NMOS gate 108 and a gate dielectric layer 114 disposed between the NMOS gate 108 and the semiconductor substrate _1〇0, and the PMOS gate structure includes a PMOS gate 110. And a gate dielectric 35114 disposed between the pM〇s and the semiconductor substrate 100. Then carry out an ion implantation process respectively, which will be a (four) 4? The type and the lion-like implanted semiconductor substrate 100 are each formed in the semiconductor substrate 100 around the ISfMOS Pg pole structure and the pM〇s interpolar structure—lightly doped U.S. and Up. After the absence of the sidewalls of the gate 108 and the PMOS gate 11 etch 110, a side wall 112 and a side wall U3 are sequentially formed. Then, a further ion implantation process is sequentially performed, and a higher dose of P U1 dopant is implanted into the semiconductor substrate 1 (10) to form a lightly doped gate 118 and 119. 116 and 117. Then, a rapid temperature annealing furnace is used to activate the implanted substrate by using a temperature of 900 〇C to 1 UKTC, and simultaneously repair the lattice structure of the surface of the damaged semiconductor substrate 100 in the ion implantation process. . 15 1328842 • As shown in FIG. 12, an etching process is then performed to form a recess 12〇 in the top and source/drain regions 116 of the nm〇s gate 108, and at the top of the PMOS gate 110. A groove 122 is formed in the source/drain region 117, respectively. A baking process is then carried out, using a temperature of about 7 Torr to 950 ° C to remove oxides remaining on the surfaces of the grooves 120 and 122 and repairing the otherwise rough groove surface. As shown in FIG. 13, a selective epitaxial growth (SEG) process is then performed after the end of the baking process to form a tantalum carbide in the recess 120 of the NMOS transistor region 102. The epitaxial layer 124 and the epitaxial layer 126 formed by the germanium germanium are formed in the recess 122 of the PMOS transistor region 〇4. Then, another epitaxial annealing process is performed after the epitaxial layers 124 and 126 are formed, and the dopant of the implanted substrate is reactivated by using a temperature of 90 (TC to 1100 Å) as previously used to form the source/drain regions. The rapid temperature annealing process, the time of the rapid temperature annealing process is also between 1 sec and 30 sec. Subsequently, the present invention can perform a millisecond anneai process after the second rapid temperature annealing process is completed. The solid solubility of all dopants is raised to a maximum without using a deep junction depth using a high temperature of 1 〇 (10) ° C to 1350 ° C. According to a preferred embodiment of the present invention, the millisecond annealing process can be one The laser annealing process, and the millisecond annealing time is between 100 milliseconds and 1 microsecond. Thus, the fabrication of the complementary MOS semiconductor transistor of the embodiment of the invention is completed. It is known that the step of forming a groove in the source/drain region to fill the epitaxial layer usually causes uneven distribution of the dopant, and the baking process performed before the formation of the epitaxial layer destroys the bond in the dopant and In order to improve the phenomenon, the present invention is based on the formation of an epitaxial layer and another rapid thermal annealing process to improve the problem. According to a preferred embodiment of the present invention, the second rapid thermal annealing process can be used in addition to Redefine the distribution of the dopant in the substrate, and simultaneously repair the bond in the dopant due to the post-temperature of the baking process, thereby improving the overall performance of the MOS transistor. The above is only the preferred embodiment of the present invention. For the embodiments, the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. [Simplified Schematic] Figures 1 to 4 are conventionally fabricated by selective epitaxial growth. Schematic diagram of a method for straining a ruthenium-oxygen semiconductor transistor. Figure 5 is a schematic diagram of the operating current and leakage current of a PMOS transistor at different baking temperatures. Figure 6 is a diagram showing the resistance of a PMOS transistor at different baking temperatures. 7 to 10 are schematic views showing a method of fabricating a strained gold-oxide semiconductor transistor by selective epitaxial growth according to a preferred embodiment of the present invention. Figs. 11 to 13 are the present invention. Another embodiment of the method for making a complementary MOS transistor using selective epitaxial growth to a length of 17 1328842 is not intended.
[ 主要元件符號說明】 10 半導體基底 12 閘極結構 14 閘極介電層 16 閘極 18 偏位側壁子 20 側壁子 22 淺溝隔離 24 輕換雜汲極 26 源極/汲極區域 28 凹槽 30 蟲晶層 40 半導體基底 42 閘極結構 44 閘極介電層 46 閘極 48 偏位側壁子 50 側壁子 52 淺溝隔離 54 輕摻雜汲極 56 源極/汲極區域 58 凹槽 60 為晶層 100 半導體基底 102 NMOS電晶體區 104 PMOS電晶體區 106 淺溝隔離 108 NMOS閘極 110 PMOS閘極 112 偏位側壁子 113 側壁子 114 閘極介電層 116 源極/汲極區域 117 源極/汲極區域 118 輕摻雜沒極 119 輕摻雜没極 120 凹槽 122 凹槽 124 蠢晶層 126 蠢晶層 18[Main component symbol description] 10 Semiconductor substrate 12 Gate structure 14 Gate dielectric layer 16 Gate 18 Bias side wall 20 Side wall 22 Shallow trench isolation 24 Light-changing germanium 26 Source/drain region 28 Groove 30 worm layer 40 semiconductor substrate 42 gate structure 44 gate dielectric layer 46 gate 48 offset sidewall spacer 50 sidewall spacer 52 shallow trench isolation 54 lightly doped drain 56 source/drain region 58 recess 60 Crystal layer 100 semiconductor substrate 102 NMOS transistor region 104 PMOS transistor region 106 shallow trench isolation 108 NMOS gate 110 PMOS gate 112 bias sidewall spacer 113 sidewall spacer 114 gate dielectric layer 116 source/drain region 117 source Pole/drain region 118 light doped immersion 119 light doped immersion 120 groove 122 groove 124 stray layer 126 stupid layer 18