TWI415194B - Method of fabricating strained silicon transistor - Google Patents

Abstract

A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive stressor, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization.

Description

Method for manufacturing strained germanium crystal

The present invention relates to a semiconductor device, and more particularly to a method of fabricating a strained germanium transistor.

As semiconductors move toward miniaturized sizes, the size of the gate, source, and drain of the transistor continues to shrink as the feature size decreases. However, due to the inherent physical properties of the material, the reduction in the size of the gate, source, and drain causes a decrease in the amount of the current-determining carrier in the transistor component, which in turn affects the performance of the transistor. Therefore, increasing the carrier mobility to increase the speed of the MOS transistor has become a major issue in the field of semiconductor technology.

Among the currently known techniques, there is a method of manufacturing mechanical stress in a channel to enhance carrier mobility. For example, epitaxial formation of a germanium germanium (SiGe) channel layer on a germanium substrate to form a compressive strained channel can significantly increase hole mobility. Or by epitaxially forming a silicon channel on the germanium telluride layer to form a tensile strained channel, the electron mobility can be significantly increased.

In addition, a selective epitaxial growth method is also used. After the gate is formed, a doped germanium is embedded in the source/drain region to form a squeezed strained germanium structure to enhance the electron mobility of the PMOS. Alternatively, a carbon-doped germanium-selective epitaxy is embedded in the source/drain region in an NMOS process to form a tensile strain 矽 structure to enhance electron mobility.

Alternatively, or in addition, a stress is applied in the contact etch stop layer (CESL) to cause strain of the channels of the transistors on the semiconductor substrate to expand or compress, thereby improving the mobility of the carrier.

However, as the size of the gold-oxygen MOS transistor continues to be toward miniaturization, the speed demand for the MOS transistor is also increasing, and it is difficult to achieve the required degree by using the compressive stress or the tensile stress formed by the above-mentioned conventional techniques. .

In view of this, the applicant proposes a method of fabricating a strained germanium crystal to improve the disadvantages of the above-mentioned prior art, thereby improving the performance of the MOS transistor.

The present invention provides a method for fabricating a strained germanium crystal. First, a substrate is provided comprising a first transistor region, a second transistor region, and a An edge is located between the first transistor region and the second transistor region, and then a first strained germanium layer is formed in the substrate of the first transistor region, and then, in the second transistor region A second strained layer is formed in the substrate, and then a first conductivity type transistor is formed in the first transistor region, and finally a second conductivity type transistor is formed in the second transistor region.

The present invention further provides a method for fabricating a strained germanium crystal. First, a substrate is provided with an oxide region and an insulator is disposed at a periphery of the transistor region, and then a strain is formed in the substrate of the transistor region. a layer, and then forming a first conductivity type of transistor in the transistor region.

The invention further provides a method for fabricating a strained germanium crystal, firstly providing a substrate comprising a transistor region and an insulator located at a periphery of the transistor region, and secondly performing an amorphous germanium formation process in the transistor region, and then, Forming a doping well in the transistor region, then forming a stress layer covering the transistor region, and then performing a tempering process to form a strained germanium layer in the substrate of the transistor region and activating the doping The dopant in the well finally removes the stress layer and forms a first conductivity type of transistor in the transistor region.

The strain enthalpy transistor process of the present invention is characterized in that the time at which the strain enthalpy layer formed in the transistor region is formed by the stress memory technique (SMT) is after the isolation structure, such as the shallow trench isolation structure, is completed, and the transistor Before it was formed. In addition, with the process of the present invention, the same mask can be used in the doping well ion implantation process and the amorphous deuteration process. Furthermore, in the strain 矽 transistor process of the present invention, the dopant in the doping well can be simultaneously introduced and activated in a tempering step and a strain enthalpy layer is formed in the substrate.

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic diagrams showing a process for fabricating a strained germanium crystal according to a first preferred embodiment of the present invention.

As shown in FIG. 1, a substrate 10 such as a germanium substrate or an insulating layer overlying germanium (SOI) substrate is provided first, and a surface of the substrate 10 defines a first transistor region 12 and a second transistor region 14. Then, an isolation process such as a shallow trench isolation structure (STI) is performed, for example, etching is performed on the substrate 10 by an etching step, and then an oxide deposition process is performed to deposit a layer of oxide to fill the trench and cover the surface of the substrate, followed by chemical mechanical processing. The foregoing oxide is ground to form an insulating layer of the shallow trench isolation structure 16 or the like in the substrate 10 to isolate the transistor regions 12, 14, wherein the first transistor region 12 is used to form the first conductivity type. The active region of the transistor, that is, the transistor disposed in the first transistor region 12 is in a first conductivity type, such as an N-type MOS transistor; and the second transistor region 14 is used to form a second region. The active area of the conductive type of transistor, that is, set in the second The transistor in transistor region 14 is of a second conductivity type, such as a P-type MOS transistor. The following embodiments will be exemplified by the fact that the transistor on the first transistor region 12 is N-type and the transistor on the second transistor region 14 is P-type.

Then an amorphous deuteration process is performed, for example, by a single ion implantation process using a xenon (Xe), argon (argon) or germanium (Ge) plasma. The first transistor region 12 and the second transistor region 14 are implanted. Wherein, when the single ion implantation process is performed, the concentration of cesium ions, argon ions or cesium ions used is greater than 1E14, and the energy thereof is greater than 10 keV.

Then, as shown in FIG. 2, a first stressor layer 18 and a second stressor layer 20 are formed on the first transistor region 12 and the second transistor region 14 of the substrate 10, respectively. The first stressor layer 18 includes a first silicon oxide layer 22 and a first tantalum nitride layer 24, wherein the first tantalum nitride layer 24 has a tensile stress and is located on the first silicon oxide layer 22, and the first germanium layer The function of the oxygen layer 22 is to serve as an etch stop layer or a buffer layer to prevent excessive stress in the first tantalum nitride layer 24, resulting in structural damage of the substrate 10. The first silicon oxide layer 22 can be selectively formed according to different product requirements. That is, the first stressor layer 18 may also include only the first tantalum nitride layer 24. Similarly, the second stressor layer 20 includes a fourth silicon oxide layer 26 and a second tantalum nitride layer 28, wherein the second tantalum nitride layer 28 has a compressive stress. The function of the fourth silicon oxide layer 26 is also to avoid excessive stress in the second tantalum nitride layer 28, resulting in structural damage of the substrate 10. Bad or as an etch stop layer of the second tantalum nitride layer 28, further, like the first silicon oxide layer 22, the fourth silicon oxide layer 26 may also be selectively formed. In addition, the first tantalum nitride layer 24 and the second tantalum nitride layer 28 may be formed by, for example, forming an antimony oxide layer on the substrate 10 and then forming a first tantalum nitride layer having a tensile stress. 24, further removing the first tantalum nitride layer 24 on the second transistor region 14 via a lithography and etching step, since the foregoing silicon oxide layer is utilized as a process for removing the first tantalum nitride layer 24 Etching the stop layer to etch a portion of the germanium oxide layer on the second transistor region 14, thereby forming the unetched first germanium oxide layer 22 and the second transistor region 14 on the first transistor region 12 Etched second silicon oxide layer. Next, a third silicon oxide layer is formed on the first tantalum nitride layer 24 and the second tantalum oxide layer as another etching stop layer, and then the second tantalum nitride layer 28 having compressive stress is formed to be completely covered. a tantalum nitride layer 24 and a third tantalum oxide layer on the second tantalum oxide layer, after which the second tantalum nitride layer 28 on the first tantalum nitride layer 24 is removed by a lithography, etching step, and The second silicon oxide layer and the third silicon oxide layer remaining on the second transistor region 14 are the same material, so the second silicon oxide layer and the third silicon oxide layer are regarded as one in FIG. The fourth oxygen layer 26 is. It is added that the second tantalum nitride layer 28 on the first tantalum nitride layer 24 may not be removed, that is, the third silicon oxide layer described in the foregoing step is not formed, directly in the first The second tantalum nitride layer 28 may be formed on the tantalum nitride layer 24 and the second tantalum oxide layer, and the second tantalum nitride layer 28 covers the first tantalum nitride layer 24 and the second tantalum oxide layer simultaneously. Furthermore, the thickness of the first tantalum nitride layer 24 should be designed such that the total area of the first transistor region 12 is received. The stress is the stress provided by the first tantalum nitride layer 24.

In addition, the first silicon oxide layer 22 and the first tantalum nitride layer 24 may be formed in the same chamber; and the fourth silicon oxide layer 26 and the second tantalum nitride layer 28 may be formed in the same chamber, That is, it is possible to avoid the situation in which the substrate needs to leave the vacuum state due to the transformation chamber. In addition, the adjustment of the stress can be achieved by matching the deposition process parameters or by surface treatment such as ion implantation, tempering, ultraviolet light (UV), etc., which are familiar to those skilled in the art and those of ordinary knowledge, so Repeat more.

As shown in FIG. 3, a tempering process is performed while the germanium atoms in the surface layer of the substrate 10 are rearranged according to the stretching/compression directions provided by the first stress layer 18 and the second stress layer 20 to form the first transistor region. A first strained layer 30 and a second strained layer 32 are formed in the substrate 10 below the second and second transistor regions 14, respectively. Thus, a stress straining technique (SMT) is used to form a first strain enthalpy layer 30 having a tensile stress and a second strain enthalpy layer 32 having a compressive stress, respectively, in the substrate 10. Next, the first stressor layer 18 and the second stressor layer 20 are removed and a patterned photoresist 34 is formed, exposing the first transistor region 12 and a portion of the shallow trench isolation structure 16, followed by doping well ions The implantation process utilizes a P-type dopant to form a P-type doping well 36 in the substrate 10 within the first transistor region 12.

Next, as shown in FIG. 4, after the photoresist 34 is removed, a patterned photoresist 38 is formed to expose the second transistor region 14 and a portion of the shallow trench isolation structure 16, followed by doping the ion cloth. The implant process utilizes an N-type dopant to form an N-type doped well 40 in the substrate 10 within the second transistor region 14.

As shown in FIG. 5, a high temperature thermal process, such as a tempering process, is performed to entangle and activate the dopants in the P-type doping well 36 and the N-type doping well 40. Next, gates 42, 44 and corresponding N-type source/drain doping regions 46 and P-type source/drain doping regions are formed on P-type well 36 and N-type well 40, respectively. 48. Thus far, the CMOS transistors having the strained germanium layer of the present invention, such as the N-type transistor 50 and the P-type transistor 52, have been completed.

Please refer to FIG. 6 to FIG. 9 . FIG. 6 to FIG. 9 are schematic diagrams showing a process for fabricating a transistor according to a second preferred embodiment of the present invention. Elements having the same function are still denoted by the same reference numerals as the first preferred embodiment.

As shown in FIG. 6, first, a substrate 10 having a first transistor region 12 and a second transistor region 14 is provided thereon, and then an insulator such as a shallow trench isolation structure (STI) 16 is formed in the substrate 10. The transistor regions 12, 14 are isolated. The process of the shallow trench isolation structure 16 has been described in the first embodiment and will not be described herein. In addition, the first transistor region 12 is an active region of a transistor for forming a first conductivity type, that is, the transistor disposed in the first transistor region 12 is in a first conductivity type, such as N. type The MOS transistor; the second transistor region 14 is a transistor for forming a second conductivity type, such as a P-type MOS transistor.

Then forming a patterned photoresist 34, exposing the first transistor region 12 and a portion of the shallow trench isolation structure 16, and then performing a first amorphous deuteration process to implant the first transistor region 12 by the ion implantation process. The ions used in ion implantation include strontium ions, argon ions, strontium ions, etc., and then, using the photoresist 34 as a mask, a first doping well ion implantation process is performed, for example, using a P-type dopant. A P-type doping well 36 is formed in the substrate 10 in the first transistor region 12. According to another preferred embodiment of the present invention, the processing sequence of the first amorphous germanium forming process and the first doping well ion implantation process may be exchanged, for example, the first doping well ion implantation process is first performed to form The P-type doping well 36 is further subjected to a first amorphous deuteration process, but both are patterned with a photoresist 34 as a mask.

As shown in FIG. 7, the photoresist 34 is removed, and a patterned photoresist 38 is formed to expose the second transistor region 14 and a portion of the shallow trench isolation structure 16, and then a second amorphous germanium formation process is performed. The ion implantation process implants a second transistor region 14. Similarly, the ions used in ion implantation include strontium ions, argon ions, and strontium ions, and the concentrations of strontium ions, argon ions, or krypton used in the two amorphous crystallization processes are respectively greater than 1E14, and the energy is More than 10Kev. Then, using the patterned photoresist 38 as a mask, a second doping well ion implantation process is performed, for example, using N-type dopants in the second An N-type doping well 40 is formed in the substrate 10 within the transistor region 14. According to another preferred embodiment of the present invention, in the same manner, the processing sequence of the second amorphous germanium forming process and the second doped ion ion implantation process may be exchanged, but still patterned with the photoresist 38 as Mask.

The steps of the sixth to seventh embodiments of the second preferred embodiment of the present invention can be changed to a third preferred embodiment if it is slightly changed: first before the photoresist 34 is formed, before the first Amorphous deuteration process is performed in the crystal region 12 and the second transistor region 14, and then, as shown in FIG. 6, a photoresist 34 is formed to perform ion implantation in the first doping well in the first transistor region 12. The process is to form a P-type doping well 36, and then, as shown in FIG. 7, the photoresist 34 is removed, a photoresist 38 is formed, and a second doping well ion implantation process is performed in the second transistor region 14, To form an N-type doping well 40. The subsequent steps of the third preferred embodiment are the same as those of the second preferred embodiment.

As shown in FIG. 8, a first stressor layer 18 and a second stressor layer 20 are formed on the first transistor region 12 and the second transistor region 14 of the substrate 10, respectively. The first stressor layer 18 includes a first silicon oxide layer 22 and a first tantalum nitride layer 24, wherein the first tantalum nitride layer 24 has a tensile stress and is located on the first silicon oxide layer 22. The first silicon oxide layer 22 is selectively formed according to different product requirements. Similarly, the second stressor layer 20 includes a fourth silicon oxide layer 26 and a second tantalum nitride layer 28, wherein the second tantalum nitride layer 28 has a compressive stress. Furthermore, like the first silicon oxide layer 22, the fourth silicon oxide layer 26 can also Formed selectively. In addition, the first oxygen layer 22, the fourth silicon oxide layer 26, the first tantalum nitride layer 24, and the second tantalum nitride layer 28 are formed in the same manner as in the first preferred embodiment, and are not described herein again. .

As shown in FIG. 9, a high temperature thermal process, such as a tempering process, is performed to entangle and activate the dopants in the P-type doping well 36 and the N-type doping well 40, and simultaneously in the first transistor region. A first strained layer 30 and a second strained layer 32 are formed in the substrate 10 below the second and second transistor regions 14, respectively. Then, after removing the first stress layer 18 and the second stress layer 20, the gates 42 and 44 and the N-type source/drain doping are formed on the P-type doping well 36 and the N-type doping well 40, respectively. Region 46, P-type source/drain doping region 48. To this end, the CMOS transistors having the strained germanium layer of the present invention, such as the N-type transistor 50 and the P-type transistor 52, have been completed.

Figure 10a is a flow chart showing the steps of the first preferred embodiment of the present invention, and Figure 10b is a flow chart showing the steps of the second preferred embodiment of the present invention. Figure 10c is a flow chart showing the steps of the third preferred embodiment of the present invention.

With reference to the above description, and the figures 10a, 10b and 10c, the first embodiment, the second embodiment and the third embodiment of the present invention are characterized in that the amorphous germanium process is implemented after the shallow trench isolation structure is completed, and Before starting the fabrication of the transistor, so that it can be on the substrate of the transistor region The strain enthalpy layer is fully formed.

In addition, an advantage of the second embodiment of the present invention is that the same amorphous photoresist is used in performing the first amorphous germanium process and the first high-concentration ion implantation process, and the second amorphous germanium process and the second are performed. Another high-density ion implantation process uses another identical patterned photoresist. Furthermore, the doping and activation of the doping well and the formation of the first strained layer and the second strained layer use the same tempering process and can be performed in the same chamber, so there is no need to leave the vacuum state . Furthermore, as shown in FIG. 10b, if the amorphous germanium process and the doping well implant process are sequentially exchanged in the first transistor region, the amorphous germanium process and the second transistor region are performed. The sequential exchange of the doped well implant process can change the process steps of another strained transistor of the invention.

Please refer to FIG. 11 to FIG. 13 . FIG. 11 to FIG. 13 are schematic diagrams showing a process for fabricating a transistor according to a fourth preferred embodiment of the present invention.

As shown in FIG. 11, first, a substrate 110 is provided with an oxide region 112, and then an insulator such as a shallow trench isolation structure (STI) 116 is formed in the substrate 110 to surround the transistor region 112, and the shallow trench isolation structure (STI) The manner of forming 116 is as described in the first preferred embodiment, and details are not described herein again. The transistor region 112 can be used to form an active region of a transistor of a particular conductivity type, that is, the transistor disposed in the transistor region 112 can be of a first conductivity type, such as a P-type or an N-type. .

Next, an amorphous deuteration process is performed, for example, in a comprehensive single ion implantation process, using a helium, argon or helium ion, etc., to fully implant the transistor region 112. Wherein, when the single ion implantation process is performed, the concentration of the cesium ion, the argon ion or the strontium ion used is greater than 1E14, and the energy thereof is greater than 10Kev.

As shown in FIG. 12, a stress layer 118 is formed on the transistor region 112 of the substrate 110. The stress layer 118 may include a germanium oxide layer 122 and a tantalum nitride layer 124. If the first conductivity type is N-type, the tantalum nitride layer 124 is adjusted to have a tensile stress, and if the second conductivity type is a P-type, the tantalum nitride layer 124 is adjusted to have a compressive stress, wherein the stress is adjusted. It can be achieved by matching the deposition process parameters or by surface treatment such as ion implantation, tempering, ultraviolet light (UV), etc., which are well known to those skilled in the art and those of ordinary knowledge, and therefore will not be described in detail. According to another preferred embodiment of the present invention, the stressor layer 118 may also include only the tantalum nitride layer 124, and the silicon oxide layer 122 may be selectively formed. Furthermore, the germanium oxide layer 122 and the tantalum nitride layer 124 can be formed by successive deposition in the same chamber.

As shown in FIG. 13, a tempering process is performed while the germanium atoms are rearranged in accordance with the stretch/compression direction provided by the stressor layer 118 to form a strained germanium layer 130 in the substrate 110 below the transistor region 112. So far, a strain enthalpy layer is formed in the substrate 110 by using a stress memory technique (SMT). 130. It should be noted that if the first conductivity type is N-type, the strain enthalpy layer 130 is a tensile strain; and if the second conductivity type is a P-type, the strain enthalpy layer 130 is a compressive strain.

Then, in the transistor region 112, a well ion implantation process is then performed to form a doping well 136 in the substrate 110 in the transistor region 112 using N-type or P-type dopants. Subsequently, a high temperature thermal process, such as a tempering process, is performed to entangle and activate the dopant in the doping well 136. Next, a gate 142 and a source/drain doping region 146 are formed over the doping well 136. So far, the MOS transistor 150 having the strained germanium layer of the present invention has been completed.

Please refer to FIG. 14 to FIG. 16 . FIG. 14 to FIG. 16 are schematic diagrams showing a process for fabricating a transistor according to a fifth preferred embodiment of the present invention. Elements having the same functions are still denoted by the same reference numerals as the fourth preferred embodiment.

As shown in FIG. 14, first, a substrate 110 is provided with an oxide region 112, and then an insulator such as a shallow trench isolation structure (STI) 116 is formed in the substrate 110 to surround the transistor region 112, wherein the transistor region 112 can be The active region of the transistor used to form a particular conductivity type, that is, the transistor disposed within the transistor region 112 is a first conductivity type transistor, such as a PMOS or NMOS.

Then, a patterned photoresist 134 is formed in the transistor region 112, followed by an amorphous germanium process to implant the transistor region 112 by ion implantation, wherein the ions used for ion implantation comprise helium ions and argon. The ions, cesium ions, etc., have a concentration of cerium ions, argon ions or cerium ions of greater than 1E14, respectively, and an energy of more than 10 KeV. Subsequently, the doping well ion implantation process is continued with the photoresist 134 as a mask, and a doping well 136 is formed in the substrate 110 in the transistor region 112 by using the dopant, notably: if the first conductive If the type transistor is an NMOS, the ions implanted in the high-concentration ion implantation are P-type; if the second conductivity type transistor is a PMOS, the ions implanted in the high-concentration ion implantation are N-type. According to another preferred embodiment of the present invention, the process sequence of the amorphous dimination process and the high concentration ion implantation process may be exchanged, for example, the doping well ion implantation process is first performed to form the doping well 136, and then The amorphous deuteration process, but with the patterned photoresist 134 as a mask.

The step of Fig. 14 of the fifth preferred embodiment of the present invention can be changed to a sixth preferred embodiment if it is slightly changed. First, before the photoresist 134 is formed, it is comprehensive before the transistor region 112. The amorphous germanium forming process is performed, and then a photoresist 134 is formed to perform a doping well ion implantation process in the transistor region 112 to form a doping well 136. The subsequent steps of the sixth preferred embodiment are the same as those of the fifth preferred embodiment.

As shown in FIG. 15, a transistor region 112 is formed on the substrate 110. The stress layer 118 includes a tantalum layer 122 and a tantalum nitride layer 124. If the first conductivity type is N type, the tantalum nitride layer 124 is adjusted to have a tensile stress; if the second conductivity type is The P-type adjusts the tantalum nitride layer 124 to have a compressive stress. According to another preferred embodiment of the present invention, the stressor layer 118 may also include only the tantalum nitride layer 124, and the silicon oxide layer 122 may be selectively formed. Furthermore, the tantalum layer 122 and the tantalum nitride layer 124 can be formed by continuous deposition using the same chamber.

As shown in FIG. 16, a tempering process is performed to rearrange the germanium atoms in accordance with the stretching/compression direction provided by the stress layer 118 to form a strained layer 130 in the substrate 110 below the transistor region 112, and At the same time, the dopant in the doping well 136 is infiltrated and activated. So far, a strain enthalpy layer 130 is formed in the substrate 110 by using a stress memory technique, and then the stress layer 118 is removed. It should be noted that if the first conductivity type is N-type, the strain enthalpy layer 130 is a tensile strain; and if the second conductivity type is a P-type, the strain enthalpy layer 130 is a compressive strain. Next, a gate 142 and a source/drain doping region 146 are formed over the doping well 136. So far, the MOS transistor 150 having the strained germanium layer of the present invention has been completed.

Figure 17a is a flow chart showing the steps of the fourth preferred embodiment of the present invention, Figure 17b is a flow chart showing the steps of the fifth preferred embodiment of the present invention, and Figure 17c is a view of the present invention. A flow chart of the steps of the sixth preferred embodiment.

From the 17th, 17b, 17c and the above description, the fourth, fifth and sixth embodiments of the present invention are characterized in that the amorphous germanium process is implemented after the shallow trench isolation structure is completed, and This is done before the fabrication of the transistor, so that a strained layer can be formed over the substrate of the transistor region.

Further, an advantage of the fifth embodiment of the present invention is that the same patterned photoresist is used in performing the amorphous deuteration process and the high concentration ion implantation process. Furthermore, the doping and activation of the doping well and the formation of the strained layer use the same tempering process and can be performed in the same chamber, so there is no need to leave the vacuum state. Moreover, as shown in FIG. 17b, if the order of the amorphous germanium process and the doping well implant process is exchanged, the process steps of another strained transistor of the invention can be changed.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

12‧‧‧First transistor area

14‧‧‧Second transistor area

16‧‧‧Shallow trench isolation structure

18‧‧‧First stress layer

20‧‧‧Second stress layer

22‧‧‧First oxygen layer

24‧‧‧First tantalum layer

26‧‧‧ fourth oxygen layer

28‧‧‧Second tantalum layer

30‧‧‧First strain layer

32‧‧‧Second strain layer

34‧‧‧Light resistance

36‧‧‧P type doping well

38‧‧‧Light resistance

40‧‧‧N type doping well

42‧‧‧ gate

44‧‧‧ gate

46‧‧‧N type source/drain doping area

48‧‧‧P type source/drain doping area

50‧‧‧N type transistor

52‧‧‧P type transistor

110‧‧‧Base

112‧‧‧Optocrystalline area

16‧‧‧Shallow trench isolation structure

118‧‧‧First stress layer

122‧‧‧First oxygen layer

124‧‧‧First tantalum nitride layer

130‧‧‧First strain layer

134‧‧‧Light resistance

136‧‧‧Doped well

142‧‧‧ gate

146‧‧‧ source/drain doping

150‧‧‧Optoelectronics

1 to 5 are schematic views showing a process for fabricating a transistor according to a first preferred embodiment of the present invention.

6 to 9 are diagrams showing the fabrication of a transistor according to a second preferred embodiment of the present invention. Process schematic.

Figure 10a is a flow chart showing the steps of the first preferred embodiment of the present invention.

Figure 10b is a flow chart showing the steps of the second preferred embodiment of the present invention.

Figure 10c is a flow chart showing the steps of the third preferred embodiment of the present invention.

11 to 13 are schematic views showing a process for fabricating a transistor according to a fourth preferred embodiment of the present invention.

14 to 16 are schematic views showing the process of fabricating a transistor according to a fifth preferred embodiment of the present invention.

Figure 17a is a flow chart showing the steps of a fourth preferred embodiment of the present invention.

Figure 17b is a flow chart showing the steps of the fifth preferred embodiment of the present invention.

Figure 17c is a flow chart showing the steps of the sixth preferred embodiment of the present invention.

10‧‧‧Base

16‧‧‧Shallow trench isolation structure

36‧‧‧P type doping well

40‧‧‧N type doping well

42‧‧‧ gate

44‧‧‧ gate

46‧‧‧ source/drain doping

48‧‧‧ source/drain doping

50‧‧‧N type transistor

52‧‧‧P type transistor

Claims (21)

A method for fabricating a strained germanium crystal, comprising: providing a substrate having a first transistor region, a second transistor region, and an insulator in the first transistor region and the second transistor region Forming a first strain 矽 layer in the substrate of the first transistor region; forming a second strain 矽 layer in the substrate of the second transistor region, wherein the first strain 矽 layer is formed and The step of forming the second strain layer includes: forming a first stress layer covering the first transistor region; forming a second stress layer covering the second transistor region, the first stress layer and the second stress layer The stress is one of a tensile stress and a compressive stress, respectively, and is different from each other; forming a first conductive type of transistor on the first strained layer; and forming a first layer on the second strained layer A two-conducting type of transistor. The manufacturing method as described in claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The manufacturing method as described in claim 2, wherein the forming the first strained layer and the second strained layer further comprises: before forming the first stress layer and the second stress layer, Performing an amorphous deuteration process in the first transistor region and the second transistor region; Performing a first tempering process, respectively forming the first strained layer and the second strained layer in the substrate of the first transistor region and the second transistor region; and removing the first stress a layer and the second stressor layer. The manufacturing method described in claim 3, after the first stress layer and the second stress layer are removed, before the forming the transistor, further comprising: forming a region in the first transistor region a first doping well; forming a second doping well in the second transistor region; and performing a second tempering process to activate dopants in the first doping well and the second doping well . The manufacturing method as described in claim 1, wherein the first stress layer and the second stress layer respectively comprise tantalum nitride. The manufacturing method as described in claim 1, wherein the first stress layer and the second stress layer comprise a structure in which a lower layer is a germanium oxide layer and an upper layer is a tantalum nitride layer. The manufacturing method as described in claim 1, wherein the first stress layer has a tensile stress and the second stress layer has a compressive stress. The manufacturing method as described in claim 3, wherein the amorphous deuteration process is an ion implantation process, and the ion implantation process comprises implanting cerium ions, argon ions or cerium ions. The manufacturing method as described in claim 2, wherein the forming the first strained layer and the second strained layer further comprises: forming a first doping well in the first transistor region; Performing a first amorphous deuteration process in the first transistor region; forming a second doping well in the second transistor region; and performing a second amorphous deuteration process in the second transistor region; Forming the first stress layer and the second stress layer after the doping wells and the amorphous deuteration processes; performing a tempering process to form the first strain relief layer and the second strain relief layer, And advancing and activating the dopants in the first doping well and the second doping well; and removing the first stressor layer and the second stressor layer. The manufacturing method as described in claim 9, wherein the amorphous deuteration process is performed after the formation of the doped wells. The manufacturing method as described in claim 9, wherein the doping wells are formed after the amorphous deuteration process. The manufacturing method as described in claim 9, wherein the first amorphous deuteration process and the second amorphous deuteration process respectively comprise an ion implantation process using helium ions, argon ions or helium ions. A method for fabricating a transistor, comprising: providing a substrate comprising a transistor region and an insulator surrounding the transistor region; forming a strained germanium layer in the substrate of the transistor region, wherein the strained germanium layer is formed The step of: performing an amorphous germanium forming process in the transistor region; forming a stress layer covering the transistor region after the amorphous germanium forming process; and removing the stress layer; and forming a layer on the strained germanium layer Transistor. The manufacturing method as described in claim 13, wherein the step of forming the strained layer further comprises: performing a first tempering process after removing the stress layer after the amorphous deuteration process, The strained layer is formed in the substrate of the crystal region. The manufacturing method as described in claim 14, after removing the stress layer and before forming the transistor, further comprising: forming a doping well in the transistor region; A second tempering process is performed to activate the dopant in the doped well. The manufacturing method as described in claim 13, wherein the stress layer comprises a tantalum nitride layer or a tantalum oxide layer. The manufacturing method as described in claim 13, wherein the transistor is an N-type transistor, and the stress layer has a tensile stress. The manufacturing method as described in claim 13, wherein the transistor is a P-type transistor, and the stress layer has a compressive stress. The manufacturing method as described in claim 13, wherein the step of forming the strained layer further comprises: forming a doping well in the transistor region before forming the stress layer; and performing a tempering process Forming the strained layer and activating the dopant in the doped well. The manufacturing method as described in claim 19, wherein the amorphous deuteration process is performed after the doping well is formed. The fabrication method as recited in claim 19, wherein the amorphous deuteration process is performed prior to formation of the doped well.