B143 骱 1440未劃線版 九、發明說明： 發明所屬之枝術頜域 本發明是有關於一種場效電晶體結構（Field Effect Transistor，FET)，且特別是有關於一種具有氮化鎵基礎閘 極絕緣層（GaN-based Gate insulating layer)之場效電晶體結 構。 先前技術 數位時代來臨，各電子業者皆針對此波數位化改革投 注莫大心力，其中又以半導體產業由早期代工至目前邁向 硏發的腳步最爲顯著。對於半導體產業中所製造的積體電 路可略分爲數位電路佈局與類比電路佈局兩大型態’而數 j立_體電路佈局中最常見的電子兀件即屬場效電晶體結構 0ΕΤ)，其可廣泛地應用於微處理器(micro-Processor)、邏 輯元件（logical device)、記憶體(memory)，或其他積體電路 元件中。此外，由於場效電晶體結構所應用的領域不同， 古夂其墓材的材料亦相異，一般的積體電路通常是使用矽基 材，但針對高速運算或高操作功率之積體電路則採用以氮 化鎵(GaN)、碑化錄(GaAs)或是碟化銦(InP)爲主要材料的半 導體化合物基材。 ' 第1圖繪示爲習知採用氮化鎵基材之場效電晶體結 構的示意圖。請參照第1圖，習知的場效電晶體結構主要 係由氮化鎵基材100、氮化鎵基礎（GaN_based)半導體層 W2、源極104、汲極1〇6，以及閘極108所構成。其中’ Λ化鎵基礎半導體層102配置於氮化鎵基材100上’而氮 &鎵棊礎半導體層102通常係藉由幕晶的方式形成於 化鎵棊材100 ’且氮化鎵基礎半導體層102之材質爲 未劃線版B143 骱 1440 unlined version IX, invention description: the invention belongs to the branch jaw field The present invention relates to a field effect transistor structure (FET), and in particular to a GaN-based sluice gate Field effect transistor structure of GaN-based Gate insulating layer. Prior Art The digital era is coming, and all electronics companies are paying great attention to this wave of digitalization reforms. Among them, the semiconductor industry has been the most prominent in its footsteps from the early foundry to the present. For the integrated circuit manufactured in the semiconductor industry, it can be divided into two large states of digital circuit layout and analog circuit layout. The most common electronic components in the circuit layout are the field-effect transistor structure. It can be widely used in micro-processors, logical devices, memory, or other integrated circuit components. In addition, due to the different fields of application of the field-effect transistor structure, the materials of the ancient burial materials are also different. The general integrated circuit is usually a germanium substrate, but the integrated circuit for high-speed operation or high operating power is A semiconductor compound substrate mainly composed of gallium nitride (GaN), intaglio (GaAs) or indium (InP) is used. Fig. 1 is a schematic view showing a conventional field effect transistor structure using a gallium nitride substrate. Referring to FIG. 1 , the conventional field effect transistor structure is mainly composed of a gallium nitride substrate 100, a gallium nitride based (GaN) based semiconductor layer W2, a source 104, a drain 1〇6, and a gate 108. Composition. Wherein the "gallium gallium base semiconductor layer 102 is disposed on the gallium nitride substrate 100" and the nitrogen & gallium base semiconductor layer 102 is generally formed by a curtain crystal in the gallium germanium 100' and the gallium nitride base The material of the semiconductor layer 102 is an unlined version
AlxGh—χΝ，其中1 2 xg 0。此外，源極104、汲極106，以 及閘極108係配置於氮化鎵基礎半導體層102上，且源極 104、汲極106分別位於閘極108的兩側。 第2圖繪示爲習知高功率操作之場效電晶體結構的示 意圖。請同時參照第1圖與第2圖，第1圖所繪示之場效 電晶體結構中，由於閘極108係直接位於氮化鎵基礎半導 體層102上，故在高溫、高功率操作的情況下，元件的閘極 漏電流並無法有效的抑制，進而影響其特性。針對元件耐高 溫與高操作功率的需求而言，若能在閘極108與氮化鎵基 礎半導體層102之間配置一閘極絕緣層110 (繪示於第2 圖广’預期將可大幅提昇元件的崩潰電壓，進而降低其閘 極漏電流。然而，習知的場效電晶體結構中，閘極絕緣層 no係直接使用二氧化矽（si〇2)、氮化矽（smx)、氧化鎵 (Ga2〇3)等絕緣材質，這些絕緣材質之閘極絕緣層110在實 際生產之後發現其與氮化鎵基礎半導體層102之間的晶格 匹配度不佳，故元件的操作特性便無法準確的評估。正由 於III-V族材料中缺乏品質良好的絕緣層，故要製作出電氣 特性穩定之金屬-絕緣層-半導體場效電晶體結構(MISFET) 相當困難。 爲了改善上述絕緣層不適當的問題，一種在砷化鎵基 材(GaAs substrate)上使用半絕緣同質材料取代絕緣層的作 法已被fee出’此作法試圖提商閘極絕緣層與基材之間的晶 格匹配特性，以使得金屬-絕緣層-半導體場效電晶體結構 (MISFET)具有良好的電氣特性。由於形成砷化鎵係採用低 溫成長的製程，故在閘極與基材之間以低溫製程形成的絕 緣層仍須經過高溫熱處理(post annealing)，才會具有良好的 5 1314360 92 10 1440未劃線版 絕緣特性，但因爲高溫製程中仍會對砷化鎵基材造成部份 的破壞，且高溫製程的步驟較爲繁雜，不僅耗時且增加成 本。 發明內容 因此，本發明的目的就是在提供一種場效電晶體結 構，其可藉由改善閘極絕緣層與氮化鎵基礎半導體層之間 晶格匹配程度，以降低元件之閘極漏電流。 本發明的另一目的就是在提供一種場效電晶體結 構，其製造成本低廉且製程步驟簡易。 本發明的另再一目的就是在提供一種耐高溫且適於 高功率操作之場效電晶體結構。 爲達上述目的，本發明提供一種場效電晶體結構，主 要係由氮化鎵基材、氮化鎵基礎半導體層、氮化鎵基礎閘 極絕緣層、源極/汲極以及閘極所構成。其中，氮化鎵基礎 半導體層係位於氮化鎵基材上；氮化鎵基礎閘極絕緣層係 配置於氮化鎵基礎半導體層上，且氮化鎵基礎閘極絕緣層 爲一 AlxInyGarx.yN 層，其中 x20，y20，12 x+y ;源極/ 汲極係配置於氮化鎵基礎半導體層上，且位於氮化鎵基礎 閘極絕緣層旁；而閘極則配置於氮化鎵基礎閘極絕緣層上。 依照本發明的較佳實施例所述，氮化鎵基礎閘極絕緣 層中例如具有一摻質，以增進氮化鎵基礎閘極絕緣層的電 阻値，且此摻質例如爲碳、鎂、鐵等金屬或是這些材質之 組合或以低溫成長（攝氏300至900度）。 依照本發明的較佳實施例所述，氮化鎵基礎半導體層 例如爲一 AlalribGak—bN 層，其中 a20，b20，12 a+b，a<x。 依照本發明的較佳實施例所述，場效電晶體結構例如 6 131431。未劃線版 爲g周製摻雜場效電晶體結構（Modulation Doped FET， MODFET) ’因此本實施例中的氮化鎵基礎半導體層例如是 由緩衝層、通道層、間隙層以及阻障層所構成。其中，緩 衝層與通道層例如爲一未摻雜之AlalribGa^-bN層，且 0 ’ b 2 0，1 2 a+b，x>a ;間隙層例如爲—未摻雜之 AlxInyGarx-yN 層，且 x2〇，yg〇，ig x+y ;阻障層例如爲 一石夕摻雜的 AlxIiiyGa^x-yN 層，且 xg〇，yg〇，x+y。 承上述’本貫施例之場效電晶體結構中，在緩衝層與 通道層之間例如配置有一隔絕層，此隔絕層之材質例如爲 一碳、鎂、鐵摻雜的或低溫成長的（攝氏300至900度） AlxInyGaux.yN 層，且 xgO，yg〇，I; x+y。 本發明因採用氣化錄基礎材質（GaN-based material)作 爲閘極絕緣層’其與氮化鎵基礎半導體層之間具有良好的 晶格匹配特性，且在摻雜適當的摻質（碳、鎂、鐵等金屬） 之後具有良好的絕緣特性’故本發明之場效電晶體結構具 有優越的電器特性。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 實施方式 第3圖繪示爲依照本發明第一較佳實施例場效電晶體 結構之示意圖。請參照第3圖，本實施例之場效電晶體結 構主要係由氮化鎵基材200、氮化鎵基礎半導體層202、氮 化鎵基礎閘極絕緣層210、源極204、汲極206以及閘極208 所構成。其中，氮化鎵基礎半導體層202係位於氮化鎵基 材200上，其材質例如爲AlaInbGai_a.bN，其中agO, b2 0， 7 434Q 440未劃線版 lga+b。氮化鎵基礎閘極絕緣層210係配置於氮化鎵基礎 半導體層202上’且氮化鎵基礎閘極絕緣層21〇之材質 AlxInyGai.x-yN ’ 其中 xg 0 ’ yg 〇 ’ 1 g x+y ’ x>a。此外，閘 極208則配置於氮化錄基礎閘極絕緣層21〇上，而源極204 與汲極206係位於閘極208兩側之氮化鎵基礎半導體層202 上。 本實施例中’氮化鎵基礎閘極絕緣層210中例如具有 一摻質，以增進氮化鎵基礎閘極絕緣層210的電阻値，且 此摻質例如爲碳、鎂、鐵等金屬或是這些材質之組合，而 這些摻質（碳、鐵及鎂等金屬）例如係於磊晶過程中進行 摻雜。此外’上述之氮化鎵基礎閘極絕緣層210的電阻値 例如係介於1〇9至1012歐姆/□之間。 本實施例中，由於氮化鎵基礎閘極絕緣層210係配置 於氮化鎵基礎半導體層202上，二者爲相似之材料，故晶 格匹配特性十分良好。換言之，氮化鎵基礎閘極絕緣層210 與氮化鎵基礎半導體層202之間的介面特性良好，所以不 會因二者之間的材料特性差異太大而導致元件特性低落。 此外，本實施例之氮化鎵基礎閘極絕緣層210在製作上例 如係採用低溫製程，氮化鎵基礎閘極絕緣層210可於低溫 狀態（攝氏300至900度）生成’且毋需再經由磊晶後之 高溫熱處理(post annealing)製程即可獲得絕佳的絕緣效果。 由上述可知，氮化鎵基礎閘極絕緣層210在低溫磊晶 成長之後便具有良好的絕緣特性’在製作上相當簡單，且 氮化鎵基礎閘極絕緣層210的高電阻特性將使得場效電晶 體結構具有耐溫與高功率之操作特性。 上述之氮化鎵基礎閘極絕緣層210在製作上雖以低溫 0未劃線版 !314m4 磊晶製程爲例進行說明，但並非限定本發明必須採用低溫磊 晶製程才能夠達成’本發明亦可於其他溫度狀態下進行氮化 鎵基礎閘極絕緣層210的磊晶成長，以直接生成具有良好絕 緣特性之氮化録基礎閘極絕緣層210。 第4圖繪示爲第1圖與第3圖之場效電晶體結構中， 反向偏(reverse bias)壓與閘極漏電流之間的關係圖。請參照 第4圖，曲線A爲習知不具閘極絕緣層之氮化鎵場效電晶 體結構，其反向偏(reverse bias)壓（reverse voltage)與閘極漏 電流之間的關係，而曲線B則爲本實施例中具有高阻値之 氮化鎵基礎閘極絕緣層之氮化鎵場效電晶體結構，其反向 偏壓與閘極漏電流之間的關係。由第4圖可清楚得知，習 知之氮化鎵場效電晶體結構的閘極漏電流與本實施例之氮 化鎵場效電晶體結構的閘極漏電流相較，二者之間的閘極 漏電流差値超過1〇〇〇倍。以習知製作場效電晶體結構之經 驗可以預測，如此優異之絕緣特性必然可以滿足元件高溫 與高功率操作之需求。 本發明之氮化鎵基礎閘極絕緣層除了應用於第3圖所 繪示的結構之外，亦可應用於其他應用氮化鎵基礎磊晶材 料層的元件上，例如調製摻雜場效電晶體結構(MODFET) 或其他架構之高電子移動率電晶體(High Electron Mobility Transistor，HEMT)等元件，以下僅針對調製摻雜場效電晶 體結構(MODFET)的應用層面進行說明。 第5圖繪示爲依照本發明第二較佳實施例場效電晶體 結構之示意圖。請參照第5圖，調製摻雜場效電晶體結構 (MODFET)主要係由氮化鎵基材300、氮化鎵基礎半導體層 302、氮化鎵基礎閘極絕緣層318、源極312、汲極314以 及閘極316所構成。其中，氮化鎵基礎半導體層302係位 1314360 92 101 440未劃線版 於氮化鎵基材300上。氮化鎵基礎閘極絕緣層318係配置 於氮化鎵基礎半導體層302上，且氮化鎵基礎閘極絕緣層 318 之材質 AlxInyGai_x.yN，其中 xg 0，yg 0，1 2 x+y，x>a。 此外，閘極316則配置於氮化鎵基礎閘極絕緣層318上， 而源極312與汲極314係位於閘極318兩側之氮化鎵基礎 半導體層302上。 同樣請參照第5圖，在調製摻雜場效電晶體結構的架 構中，氮化鎵基礎半導體層302例如是由緩衝層304、通道 層306、間隙層308以及阻障層310所構成。其中，緩衝層 304與通道層306例如爲一未摻雜之AlJiibGau-bN層，且 a g 0，b 2 0，1 2 a+b，x>a ;間隙層308例如爲一未摻雜之 AlxIiiyGa^-yN 層，且 x20，y20，12 x+y ;而阻障層 3 10 例如爲一矽摻雜的AlxInyGamN層，且x2 0，ygO， x+y 〇 與前一實施例相似，本實施例之氮化鎵基礎閘極絕緣 層318中亦可具有一摻質，以增進氮化鎵基礎閘極絕緣層 318的電阻値（約爲109至1012歐姆/□之間），此摻質例 如爲碳、鎂、鐵等金屬或是這些材質之組合，而這些摻質 (碳、鐵及鎂等金屬）例如係於磊晶過程中進行摻雜。 第6圖繪示爲依照本發明第三較佳實施例場效電晶體 結構之示意圖。請同時參照第5圖第6圖，本實施例與第5 圖相似，惟其差異之處在於本實施例在緩衝層304與通道 層306之間配置有一隔絕層305,而此隔絕層305之材質例 如與閘極絕緣層318同爲AlxIHyGa^N，且x2 0，y2 0， 1 ^ χ+y。 上述所揭露之場效電晶體結構，主要在於加強元件本 身的閘極崩潰特性，進而達到高功率操作之目的。另外， ηΐ4·4。未劃線版 吾人更可利用上述之氮化鎵基礎絕緣層（GaN-based insulating layer)作爲半導體晶晶層與基材間的絕緣緩衝 層，這將可有效地消除邊閘極效應（side-gating effect)或背 閘極效應（back-gating effect)，且實質地降低輸出電導 (output conductance) ’進而更有利於高頻操作。 雖然本發明已以多個較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 圖式簡單說明 第1圖繪示爲習知採用氮化鎵基材之場效電晶體結構 的示意圖； 第2圖繪示爲習知高功率操作之場效電晶體結構的示 意圖； 第3圖繪示爲依照本發明第一較佳實施例場效電晶體 結構之示意圖； 第4圖繪示爲第1圖與第3圖之場效電晶體結構中， 反向偏壓與閘極漏電流之間的關係圖； 第5圖繪示爲依照本發明第二較佳實施例場效電晶體 結構之示意圖；以及 第6圖繪示爲依照本發明第三較佳實施例場效電晶體 結構之示意圖。 圖式標示說明 100 :氮化鎵基材 102 :氮化鎵基礎半導體層 1314· 4 4 0未劃線版 104 :源極 106 :汲極 108 :閘極 110 :閘極絕緣層 200 :氮化鎵基材 202 :氮化鎵基礎半導體層 204 :源極 206 :汲極 2 0 8 :聞極 210 :氮化鎵基礎閘極絕緣層 300 :氮化鎵基材 302 :氮化鎵基礎半導體層 304 :緩衝層 305 :隔絕層 306 :通道層 308 :間隙層 310 :阻障層 312 :源極 314 :汲極 3 16 :鬧極 318 :氮化鎵基礎閘極絕緣層AlxGh—χΝ, where 1 2 xg 0. Further, the source 104, the drain 106, and the gate 108 are disposed on the gallium nitride base semiconductor layer 102, and the source 104 and the drain 106 are respectively located on both sides of the gate 108. Figure 2 is a schematic illustration of a field effect transistor structure of conventional high power operation. Please refer to FIG. 1 and FIG. 2 simultaneously. In the field effect transistor structure shown in FIG. 1 , since the gate 108 is directly on the gallium nitride base semiconductor layer 102, it is operated at high temperature and high power. Under the condition, the gate leakage current of the component cannot be effectively suppressed, thereby affecting its characteristics. For the requirement of high temperature resistance and high operating power of the device, if a gate insulating layer 110 is disposed between the gate 108 and the gallium nitride base semiconductor layer 102 (shown in FIG. 2), it is expected to be greatly improved. The breakdown voltage of the component, which in turn reduces the gate leakage current. However, in the conventional field effect transistor structure, the gate insulating layer no directly uses cerium oxide (si〇2), tantalum nitride (smx), and oxidation. Insulating material such as gallium (Ga2〇3), the gate insulating layer 110 of these insulating materials is found to have poor lattice matching with the gallium nitride base semiconductor layer 102 after actual production, so the operational characteristics of the device cannot be Accurate evaluation. Due to the lack of a good quality insulating layer in the III-V material, it is quite difficult to produce a metal-insulating layer-semiconductor field effect transistor structure (MISFET) with stable electrical characteristics. A suitable problem, a method of replacing a insulating layer with a semi-insulating homogenous material on a GaAs substrate has been proposed to attempt to improve the lattice matching characteristics between the gate insulating layer and the substrate. Therefore, the metal-insulator-semiconductor field effect transistor structure (MISFET) has good electrical characteristics. Since the gallium arsenide is formed by a low temperature growth process, an insulating layer formed between the gate and the substrate by a low temperature process is formed. It still has to undergo post annealing to have good insulation properties of 5 1314360 92 10 1440 unlined version, but it will still cause partial damage to the gallium arsenide substrate due to high temperature process, and the high temperature process The steps are cumbersome, not only time consuming but also costly. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a field effect transistor structure that can improve the lattice between a gate insulating layer and a gallium nitride based semiconductor layer. The degree of matching is to reduce the gate leakage current of the component. Another object of the present invention is to provide a field effect transistor structure which is inexpensive to manufacture and simple in process steps. Another object of the present invention is to provide a high temperature resistance And suitable for high power operation field effect transistor structure. To achieve the above object, the present invention provides a field effect transistor structure, mainly by gallium nitride a substrate, a gallium nitride base semiconductor layer, a gallium nitride base gate insulating layer, a source/drain, and a gate, wherein the gallium nitride base semiconductor layer is on the gallium nitride substrate; gallium nitride The basic gate insulating layer is disposed on the gallium nitride base semiconductor layer, and the gallium nitride base gate insulating layer is an AlxInyGarx.yN layer, wherein x20, y20, 12 x+y; the source/drain system is disposed on The gallium nitride base semiconductor layer is located beside the gallium nitride base gate insulating layer; and the gate is disposed on the gallium nitride base gate insulating layer. According to a preferred embodiment of the present invention, gallium nitride The base gate insulating layer has, for example, a dopant to enhance the resistance 値 of the GaN base gate insulating layer, and the dopant is, for example, a metal such as carbon, magnesium, or iron, or a combination of these materials or grows at a low temperature ( 300 to 900 degrees Celsius). In accordance with a preferred embodiment of the present invention, the gallium nitride based semiconductor layer is, for example, an AlalribGak-bN layer, wherein a20, b20, 12a+b, a<x. In accordance with a preferred embodiment of the present invention, a field effect transistor structure is, for example, 6 131431. The unlined version is a g-doped field effect transistor structure (Modulation Doped FET, MODFET). Therefore, the gallium nitride based semiconductor layer in this embodiment is, for example, a buffer layer, a channel layer, a gap layer, and a barrier layer. Composition. Wherein, the buffer layer and the channel layer are, for example, an undoped AlalribGa^-bN layer, and 0 'b 2 0,1 2 a+b, x>a; the gap layer is, for example, an undoped AlxInyGarx-yN layer And x2 〇, yg 〇, ig x+y; the barrier layer is, for example, a radix-doped AlxIiiyGa^x-yN layer, and xg 〇, yg 〇, x+y. In the field effect transistor structure of the above-mentioned embodiment, for example, an insulating layer is disposed between the buffer layer and the channel layer, and the material of the insulating layer is, for example, carbon, magnesium, iron-doped or low-temperature grown ( AlzInyGaux.yN layer, 300 to 900 degrees Celsius, and xgO, yg〇, I; x+y. The invention adopts a GaN-based material as a gate insulating layer, which has good lattice matching characteristics with a gallium nitride base semiconductor layer, and is doped with an appropriate dopant (carbon, Metals such as magnesium and iron) have good insulating properties after that. Therefore, the field effect transistor structure of the present invention has superior electrical properties. The above and other objects, features, and advantages of the present invention will become more apparent and understood. A schematic diagram of a field effect transistor structure in accordance with a first preferred embodiment of the present invention. Referring to FIG. 3, the field effect transistor structure of the present embodiment is mainly composed of a gallium nitride substrate 200, a gallium nitride base semiconductor layer 202, a gallium nitride base gate insulating layer 210, a source 204, and a drain 206. And the gate 208 is composed of. The gallium nitride base semiconductor layer 202 is located on the gallium nitride substrate 200, and its material is, for example, AlaInbGai_a.bN, wherein agO, b2 0, 7 434Q 440 is not scribed. The gallium nitride base gate insulating layer 210 is disposed on the gallium nitride base semiconductor layer 202 and the material of the gallium nitride base gate insulating layer 21 is AlxInyGai.x-yN ' where xg 0 ' yg 〇' 1 g x +y ' x>a. In addition, the gate 208 is disposed on the nitride-based base insulating layer 21A, and the source 204 and the drain 206 are disposed on the gallium nitride-based semiconductor layer 202 on both sides of the gate 208. In the present embodiment, the GaN base gate insulating layer 210 has, for example, a dopant to improve the resistance 値 of the GaN base gate insulating layer 210, and the dopant is, for example, a metal such as carbon, magnesium, or iron. It is a combination of these materials, and these dopants (metals such as carbon, iron, and magnesium) are doped, for example, in an epitaxial process. Further, the resistance 値 of the above-described gallium nitride base gate insulating layer 210 is, for example, between 1 〇 9 and 10 12 Ω / □. In this embodiment, since the gallium nitride base gate insulating layer 210 is disposed on the gallium nitride base semiconductor layer 202, the two are similar materials, so the lattice matching characteristics are very good. In other words, the interface characteristics between the gallium nitride base gate insulating layer 210 and the gallium nitride base semiconductor layer 202 are good, so that the difference in material properties between the two is not too large, resulting in a drop in device characteristics. In addition, the gallium nitride base gate insulating layer 210 of the embodiment is fabricated by, for example, a low temperature process, and the gallium nitride base gate insulating layer 210 can be generated in a low temperature state (300 to 900 degrees Celsius). Excellent insulation is achieved by a post annealing process after epitaxy. It can be seen from the above that the gallium nitride base gate insulating layer 210 has good insulating properties after low temperature epitaxial growth, which is relatively simple in fabrication, and the high resistance characteristic of the gallium nitride base gate insulating layer 210 will make field effect. The transistor structure has temperature and high power operating characteristics. The above-described gallium nitride base gate insulating layer 210 is described by taking the low temperature 0 unlined version! 314m4 epitaxial process as an example, but the invention is not limited to the low temperature epitaxial process. The epitaxial growth of the gallium nitride base gate insulating layer 210 can be performed in other temperature states to directly generate the nitride-based gate insulating layer 210 having good insulating properties. Figure 4 is a graph showing the relationship between the reverse bias voltage and the gate leakage current in the field effect transistor structure of Figs. 1 and 3. Referring to FIG. 4, curve A is a conventional GaN field effect transistor structure having no gate insulating layer, and the relationship between the reverse bias voltage and the gate leakage current. Curve B is the relationship between the reverse bias voltage and the gate leakage current of the gallium nitride field effect transistor structure of the gallium nitride base gate insulating layer having high resistance in the present embodiment. As is clear from FIG. 4, the gate leakage current of the conventional GaN field effect transistor structure is compared with the gate leakage current of the GaN field effect transistor structure of the present embodiment. The gate leakage current difference 値 exceeds 1〇〇〇. The experience of conventional field-effect transistor structures can be predicted to ensure that such excellent insulating properties are inevitably required for high-temperature and high-power operation of components. The gallium nitride base gate insulating layer of the present invention can be applied to other components of the GaN-based epitaxial material layer in addition to the structure illustrated in FIG. 3, for example, modulation doping field effect electricity. Elements such as a crystal structure (MODFET) or other high-electron mobility transistor (HEMT) are described below only for the application level of a modulated doped field effect transistor structure (MODFET). Figure 5 is a schematic view showing the structure of a field effect transistor in accordance with a second preferred embodiment of the present invention. Referring to FIG. 5, the modulated doped field effect transistor structure (MODFET) is mainly composed of a gallium nitride substrate 300, a gallium nitride base semiconductor layer 302, a gallium nitride base gate insulating layer 318, a source 312, and a germanium. The pole 314 and the gate 316 are formed. Wherein, the gallium nitride base semiconductor layer 302 is not scribed on the gallium nitride substrate 300 at 1314360 92 101 440. The gallium nitride base gate insulating layer 318 is disposed on the gallium nitride base semiconductor layer 302, and the material of the gallium nitride base gate insulating layer 318 is AlxInyGai_x.yN, where xg 0, yg 0, 1 2 x+y, x>a. In addition, the gate 316 is disposed on the gallium nitride base gate insulating layer 318, and the source 312 and the drain 314 are disposed on the gallium nitride based semiconductor layer 302 on both sides of the gate 318. Referring also to Fig. 5, in the architecture for modulating the doped field effect transistor structure, the gallium nitride based semiconductor layer 302 is composed of, for example, a buffer layer 304, a channel layer 306, a gap layer 308, and a barrier layer 310. The buffer layer 304 and the channel layer 306 are, for example, an undoped AlJiibGau-bN layer, and ag 0, b 2 0, 1 2 a+b, x>a; the gap layer 308 is, for example, an undoped AlxIiiyGa. a ^-yN layer, and x20, y20, 12 x+y; and the barrier layer 3 10 is, for example, a germanium-doped AlxInyGamN layer, and x2 0, ygO, x+y 〇 is similar to the previous embodiment, this embodiment The gallium nitride base gate insulating layer 318 may also have a dopant to enhance the resistance 値 (between 109 and 1012 ohms/□) of the gallium nitride base gate insulating layer 318, such as It is a metal such as carbon, magnesium or iron or a combination of these materials, and these dopants (metals such as carbon, iron and magnesium) are doped, for example, in an epitaxial process. Figure 6 is a schematic view showing the structure of a field effect transistor in accordance with a third preferred embodiment of the present invention. Referring to FIG. 5 and FIG. 6 simultaneously, this embodiment is similar to FIG. 5 except that the difference is that an isolation layer 305 is disposed between the buffer layer 304 and the channel layer 306, and the material of the isolation layer 305 is disposed. For example, the same as the gate insulating layer 318 is AlxIHyGa^N, and x2 0, y2 0, 1 ^ χ + y. The field-effect transistor structure disclosed above mainly focuses on strengthening the gate breakdown characteristics of the component itself, thereby achieving high power operation. In addition, ηΐ4·4. The unlined version of the GaN-based insulating layer can be used as an insulating buffer layer between the semiconductor crystal layer and the substrate, which can effectively eliminate the side gate effect (side- The gating effect or back-gating effect, and substantially lowering the output conductance', is more conducive to high frequency operation. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a field effect transistor structure using a gallium nitride substrate; Fig. 2 is a schematic view showing a structure of a field effect transistor of a conventional high power operation; Illustrated as a schematic diagram of a field effect transistor structure according to a first preferred embodiment of the present invention; FIG. 4 is a diagram showing reverse bias voltage and gate leakage current in the field effect transistor structure of FIGS. 1 and 3. FIG. 5 is a schematic view showing a structure of a field effect transistor according to a second preferred embodiment of the present invention; and FIG. 6 is a view showing a field effect transistor structure according to a third preferred embodiment of the present invention. Schematic diagram. Schematic indication 100: gallium nitride substrate 102: gallium nitride base semiconductor layer 1314 · 4 4 0 unlined version 104: source 106: drain 108: gate 110: gate insulating layer 200: nitride Gallium substrate 202: gallium nitride base semiconductor layer 204: source 206: drain 2 0 8 : smell pole 210: gallium nitride base gate insulating layer 300: gallium nitride substrate 302: gallium nitride base semiconductor layer 304: buffer layer 305: isolation layer 306: channel layer 308: gap layer 310: barrier layer 312: source 314: drain 3 16: noisy 318: gallium nitride base gate insulating layer