1314228 九、發明說明： 【發明所屬之技術領域】 本發明s有關於-種晶片和應用其之電性接合裝置及顯 示面板，且特別是有關於一種具有緩衝層之晶片和應用其之電 性接合裝置及顯示面板。 . 【先前技術】 . —些現有之電子裝置中，元件及主體電路間的連接是透過 異方性導電膜（油你响_duetive fiim，ACF )來進行，例 如晶片就是利用異方性導電膜與液晶顯示面板電性連接。其 中’異方性導電膜是以料電性的合成樹脂及導電顆粒 ' (Particle)混合而成，而導電顆粒之中央部分為聚合物，且聚 - 合物之外表包覆一層金屬導體，如金、鎳、錫等。異方性導電 膜常被歸液晶顯示器的製程中，晶片與液晶顯示面板的接 合，且晶片之導電凸塊透過異方性導電膜之導電顆粒與液晶顯 示面板之接墊電性連接。其中玻璃黏晶技術（chip 〇n glass， COG )為最常使用到的技術之一，玻璃黏晶技術係將晶片藉由 • 異方性導電膜以熱壓合步驟直接與液晶顯示面板之薄膜電晶體 基板接合。 在將晶片透過玻璃黏晶技術與顯示面板接合之流程中，需 要先進行晶片及顯示面板的預壓著（pre_B〇nding)步驟。在預壓 ' 著步驟中，將晶片與顯示面板進行對位（Alignment)，其目的為 確定晶片位置正確與否。其中’晶片具有相對之一主動表面及 一非主動表面，主動表面具有接墊。接墊上具有導電凸塊，導 電凸塊係對位於顯示面板上之接墊。待確定晶片在顯示面板上 位置正確後’再進行主壓著（Main-Bonding)的熱壓合步驟。在主 5 1314228 壓著之熱壓合步驟中，顯示面板在平台上，晶片已經對位在顯 不面板上，Μ頭在晶片之非线表㈣上方。異方性導電膜 在晶片及顯示面板之間，但還未將晶片及顯示面板接合。當熱 壓頭下壓晶片肖’晶片與薄膜電晶體基板透過溶融態之異方性 導電膜而接合’且晶片之導電㈣透過異方性導電膜之導電顆 粒與液晶顯示面板之接墊電性連接。然後，升起熱壓頭，以固 化異方性導電膜，晶 >;透過玻璃黏晶技術與顯示面板接合之流 程在此完成。 然而，在預壓著步驟至主壓著之熱壓合步驟的過程當中， 由於晶片之非主動表面或熱壓頭上經常附著有異物（伪⑷卯 material)，導致晶片及顯示面板之間對應於異物之部分 面於熱壓合步驟後產生壓痕不良的現象。嚴重的話，將會造成 晶片破裂，後果不堪設想。 至於其他透過異方性導電膜在熱壓頭及平台之間進行熱 壓口步驟而接合之二電性元件，其所構成之電性接合裝置於熱 壓合步驟後亦會面臨上述問題。 【發明内容】 有L於此，本發明的目的就是在提供一種具有緩衝層之晶 片和應用其之電性接合裝置及顯示面板，其在晶片之非主動表 面《^置緩衝層之設汁，可以在晶片與基板進行熱壓合步驟 中，用以容納殘留於緩衝層表面及/或熱壓頭表面之異物。因 此’可以防止在熱壓合過程中造成晶片及基板之間的壓痕不良 或是晶片破裂等缺陷。 根據本發明的目的，提出一種晶片，包括本體、第一接墊' 導電凸塊以及緩衝層。本體具有主動表面及非主動表面，第一 1314228 接墊係設置於主動表面上。導電凸塊則設置於第一接塾上 衝層係形成於非主動表面上。當晶片透過一異方性導電膜與具 有第二接塾之基板進行熱壓合步驟時，晶片係與基板黏合了導 電凸塊係透過異方性導電膜之導電顆粒與第二接塾電性連接。 此外，緩衝層係可容納緩衝層之表面上於熱壓合步驟前及 間所殘留之異物。 根據本發明的再-目的，提出一種電性接合裝置，包括第 -電性元件、第二電性元件及異方性導電膜^第—電性元件具 有第-接墊，第二電性元件包括本體、第二接塾、導電凸塊及 緩衝層。本體具有第一表面及第二表面，第二接塾係設置於第 :表面上。導電凸塊係設置於第二接墊上，緩衝層㈣成於第 一表面上。異方性導電臈係設置於第一電性元件及第二電性元 件之間，並具有數個導電顆粒。異方性導電膜用以黏合第—電 性凡件及第二電性元件，使得導電凸塊透過導電顆粒與第—接 墊電性連接。當第-電性元件及第二電性元件透過熱壓頭及平 台進行熱麼合步驟時，第一電性元件係與第二電性元件黏合， 導電凸塊係與第-接墊電性連接。此外，緩衝層係可容納緩衝 層之表面上及/或熱壓頭之表面上於熱壓合㈣前及/或期 殘留之異物。 根據本發明的另一目的，提出一種顯示面板，包括薄膜電 晶體基板、晶片以及異方性導電膜。薄膜電晶體基板具有第— 接墊曰曰片包括本體、第二接墊、導電凸塊及緩衝層。本體具 有主動表面及非主動表面，第二接塾係設置於主動表面上。導 電凸塊係設置於第二接塾上，緩衝層係形成於非主動表面上。 異方性導電膜係設置於晶片及薄膜電晶體基板之間並具有數 個導電顆粒。異方性導電膜用以黏合晶片及薄膜電晶體基板， 7 1314228 使得導電凸塊透過導電顆粒與第一接塾電性連接。當晶片及薄 膜電晶體基板透過熱壓頭及平台進行熱壓合步驟時w㈣ 薄膜電晶體基板黏合’導電凸塊係與第—接墊電性連接。此外 緩衝層係可容納緩衝層之表面上及/或熱壓頭之表面上於熱壓 合步驟前及/或期間所殘留之異物。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉一較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明提出-種晶片，其在非主動表面上形成一緩衝層。 當晶片透過異方性導電膜（anis〇tr〇pic c〇nducdve出爪，) 在熱壓頭及平台之間與基板進行熱壓合步驟時，緩衝層可以容 納晶片之表面上及/或熱壓頭之表面上於熱壓合步驟前及/或期 間所殘留之異物。因此，可以避免異物造成壓痕不良，甚至造 成晶片破裂。 請參照第1圖，其繪示乃依照本發明之較佳實施例之晶片 的剖面圖。在第1圖中，晶片100包括一本體12〇、一第一接 墊130、一導電凸塊140以及一緩衝層110。本體120具有相對 之一主動表面124及一非主動表面122，第一接墊130係設置 於主動表面124上，導電凸塊（bump) 140則設置於第一接塾130 上。其中’第一接墊130例如是鋁，導電凸塊14〇例如是金、 鉛或錫，導電凸塊140及第一接墊13〇之間更可設置一凸塊底 金屬層（under bump metallurgy，UBM)。在本實施例中，以三個 導電凸塊140對應地設置於三個第一接墊130為例作說明。此 外’緩衝層110係形成於非主動表面122上。其中，緩衝層110 係於晶圓切割製程前或後，以化學氣相沉積法（chemical vapor 1314228 deposition，CVD)、物理氣相沉積法（physical vapor deposition， PVD)、貼附方式或塗佈方式形成於非主動表面122上。 請參照第2圖，其繪示乃依照第1圖之晶片與基板進行熱 壓合步驟前之狀態的剖面圖。如第2圖所示，當晶片100及一 具有第二接墊235之基板230透過一異方性導電膜260在一熱 壓頭240及一平台270之間進行熱壓合步驟前，晶片100先與 基板230進行對位，使得晶片100之導電凸塊140對位於基板 »1 230之第二接墊235，且異方性導電膜260在晶片100及基板 * 230之間。基板230在平台270上，熱壓頭240在緩衝層110 • 之上方。異方性導電膜260具有許多導電顆粒265，但導電顆 粒265並未電性導通導電凸塊140及第二接墊235。其中，緩 衝層110之表面上及熱壓頭240上具有異物250,而緩衝層110 及熱壓頭240之間亦會在晶片100與基板230進行熱壓合步驟 中具有其他異物。在本實施例中，基板230可以是一薄膜電晶 體（thin film transistor，TFT )基板或一電路板，在此以薄膜電 晶體基板為例作說明。其中，第二接墊235例如是銦錫氧化物 (indium tin oxide，IT0)。 φ 請參照第3圖，其繪示乃第2圖之晶片與基板進行熱壓合 步驟後之狀態的剖面圖。如第3圖所示，當晶片100及基板230 透過熱壓頭240及平台270進行熱壓合步驟時，晶片100係透 ' 過異方性導電膜260與基板230黏合，導電凸塊140係透過部 - 分之導電顆粒265與第二接墊235電性連接。因此，包含晶片 100、基板230及異方性導電膜260之顯示面板280終告完成。 由於緩衝層110形成於非主動表面122上，其硬度較晶片100 之本體120之硬度小，因此在熱壓合步驟時可以將第2圖中殘 留於熱壓頭240之表面上及/或缓衝層110表面上之異物250納 1314228 入緩衝層110内。如此一來’可以避免晶片11〇及基板230之 間對應於異物250之處產生壓痕不良的現象，防止晶片11〇因 異物250在熱壓合步驟時破裂。 然本實施例所屬技術領域中具有通常知識者可以明瞭本 實施例之技術並不侷限在此，如緩衝層110係可較佳地採用靜 電消散材料（static dissipative material)。此外，顯示面板280 例如是液晶顯示面板（liquid crystal display panel，LCD panel)，有機發光二極體（organic light emitting diode，OLED ) 顯示面板或有機電激發光元件（organic electrolumineseent device，OELD)。 另外’至於其他透過異方性導電膜在熱壓頭及平台之間進 行熱麗合步驟而接合之二電性元件，如第一電性元件及第二電 性元件。第一電性元件具有一第一接墊’第二電性元件包括一 本體、一第二接墊、一導電凸塊及一緩衝層。本體具有一第— 表面及一第一表面’第二接墊係設置於第一表面上。導電凸塊 係設置於第二接墊上，緩衝層係形成於第二表面上。異方性導 電膜係設置於第一電性元件及第二電性元件之間，用以黏合第 一電性元件及第二電性元件，使得導電凸塊與第一接墊電性連 接。當第一電性元件及第二電性元件透過一熱壓頭及一平台進 行熱壓合步驟時，第一電性元件係與第二電性元件黏合而構成 電性接合裝置，導電凸塊係與第一接墊電性連接。此外，緩衝 層係可容納緩衝層之表面上或熱壓頭上於熱壓合步驟前及/或 期間所殘留之異物。其中，上述之較佳實施例之第一電性元件 及第二電性元件分別為一薄膜電晶體基板及一晶片。 本發明上述實施例所揭露之晶片和應用其之電性接合裝 置及顯示面板，係於晶片之非主動表面上形成—相對於晶片材 1314228 料硬度較小之緩衝層，可以在晶片與基板進行熱壓合步驟中容 納殘留於緩衝層之表面上及/或熱壓頭之表面上之異物。如此一 來，可以避免晶片及基板之間因受力不均產生壓痕不良，防止 晶片產生破裂的現象。 综上所述，雖然本發明已以一較佳實施例揭露如上，然其 並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示乃依照本發明之較佳實施例之晶片的剖面圖； 第2圖緣示乃第i圖之晶片與基板進行熱壓合步輝前之狀 態的剖面圖；以及 ▲第3圖繪不乃第2圖之晶片與基板進行熱壓合步驟後之狀 態的剖面圖。 【主要元件符號說明】 100 .晶片 110 :緩衝層 120 :本體 122 :非主動表面 124 :主動表面 130 :第一接墊 14〇 :導電凸塊 230 :薄膜電晶體基板 235 :第二接墊 1314228 240 :熱壓頭 250 :異物 260 :異方性導電膜 265 :導電顆粒 270 :平台 280 :液晶顯示面板1314228 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer and an electrical bonding device and display panel using the same, and more particularly to a wafer having a buffer layer and an electrical property thereof Bonding device and display panel. [Prior Art] - In some existing electronic devices, the connection between the component and the main circuit is performed by an anisotropic conductive film (ACF), for example, the wafer is made of an anisotropic conductive film. Electrically connected to the liquid crystal display panel. Wherein the anisotropic conductive film is a mixture of a chargeable synthetic resin and a conductive particle, and a central portion of the conductive particle is a polymer, and the polymer is coated with a metal conductor, such as Gold, nickel, tin, etc. The anisotropic conductive film is often incorporated into the liquid crystal display process, and the wafer is bonded to the liquid crystal display panel, and the conductive bumps of the wafer are electrically connected to the pads of the liquid crystal display panel through the conductive particles of the anisotropic conductive film. Among them, chip 〇n glass (COG) is one of the most commonly used technologies. The glass bonding technology is a film directly bonded to a liquid crystal display panel by a thermocompression bonding step by using an anisotropic conductive film. The transistor substrate is bonded. In the process of bonding the wafer through the glass die bonding technique to the display panel, it is necessary to perform a pre-pressing step of the wafer and the display panel. In the pre-pressing step, the wafer is aligned with the display panel for the purpose of determining whether the wafer position is correct or not. Wherein the wafer has a relatively active surface and an inactive surface, the active surface having pads. The pad has conductive bumps, and the conductive bumps are the pads on the display panel. After the wafer is determined to be in the correct position on the display panel, a main-Bonding thermal compression step is performed. In the thermal lamination step of the main 5 1314228 press, the display panel is on the platform, the wafer has been aligned on the display panel, and the boring head is above the non-line table (4) of the wafer. The anisotropic conductive film is between the wafer and the display panel, but the wafer and the display panel have not yet been joined. When the thermal head presses the wafer, the wafer and the thin film transistor substrate are bonded through the dissolving anisotropic conductive film, and the conductive of the wafer (4) the conductive particles of the anisotropic conductive film and the electrical properties of the liquid crystal display panel connection. Then, the thermal head is raised to cure the anisotropic conductive film, and the process of bonding to the display panel through the glass die bonding technique is completed here. However, during the pre-compression step to the hot pressing step of the main pressing, since the non-active surface of the wafer or the thermal head is often attached with foreign matter (pseudo-material), the wafer and the display panel correspond to each other. Part of the foreign matter is inferior to the indentation after the thermocompression bonding step. If it is serious, it will cause the wafer to rupture, and the consequences are unimaginable. As for the other two electrical components which are joined by the hot pressing step between the thermal head and the platform through the anisotropic conductive film, the electrical bonding device formed by the electrical bonding device faces the above problems after the thermal compression bonding step. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer having a buffer layer and an electrical bonding device and display panel using the same, which are disposed on the inactive surface of the wafer. The foreign matter may remain in the thermal compression bonding step between the wafer and the substrate to accommodate foreign matter remaining on the surface of the buffer layer and/or the surface of the thermal head. Therefore, it is possible to prevent defects such as poor indentation between the wafer and the substrate or cracking of the wafer during the thermocompression bonding process. In accordance with the purpose of the present invention, a wafer is provided that includes a body, a first pad 'conductive bump, and a buffer layer. The body has an active surface and an inactive surface, and the first 1314228 pad is disposed on the active surface. The conductive bumps are disposed on the first interface and the punch layer is formed on the inactive surface. When the wafer is thermally bonded to the substrate having the second interface through the anisotropic conductive film, the wafer is bonded to the substrate by the conductive bumps and the conductive particles of the anisotropic conductive film and the second interface are electrically connected. connection. Further, the buffer layer can accommodate foreign matter remaining on the surface of the buffer layer before and during the thermocompression bonding step. According to a second aspect of the present invention, an electrical bonding apparatus is provided, including a first electrical component, a second electrical component, and an anisotropic conductive film. The first electrical component has a first pad, and the second electrical component. The body includes a body, a second contact, a conductive bump, and a buffer layer. The body has a first surface and a second surface, and the second interface is disposed on the surface. The conductive bumps are disposed on the second pad, and the buffer layer (4) is formed on the first surface. The anisotropic conductive lanthanide is disposed between the first electrical component and the second electrical component and has a plurality of conductive particles. The anisotropic conductive film is used for bonding the first electrical component and the second electrical component, so that the conductive bump is electrically connected to the first pad through the conductive particle. When the first electrical component and the second electrical component are thermally coupled through the thermal head and the platform, the first electrical component is bonded to the second electrical component, and the conductive bump and the first pad are electrically connected. connection. Further, the buffer layer can accommodate foreign matter remaining on the surface of the buffer layer and/or on the surface of the thermal head before and/or during the thermal compression (4). According to another object of the present invention, a display panel comprising a thin film transistor substrate, a wafer, and an anisotropic conductive film is provided. The thin film transistor substrate has a first pad comprising a body, a second pad, a conductive bump and a buffer layer. The body has an active surface and an inactive surface, and the second interface is disposed on the active surface. The conductive bumps are disposed on the second interface, and the buffer layer is formed on the inactive surface. The anisotropic conductive film is disposed between the wafer and the thin film transistor substrate and has a plurality of conductive particles. The anisotropic conductive film is used for bonding the wafer and the thin film transistor substrate, and the 7 1314228 is electrically connected to the first contact through the conductive particles. When the wafer and the thin film transistor substrate are subjected to a thermocompression bonding step through the thermal head and the substrate, the w (four) thin film transistor substrate is bonded to the conductive bump and electrically connected to the first pad. Further, the buffer layer can accommodate foreign matter remaining on the surface of the buffer layer and/or on the surface of the thermal head before and/or during the thermal compression step. The above-mentioned objects, features, and advantages of the present invention will become more apparent from the following description. It forms a buffer layer on the inactive surface. The buffer layer can accommodate the surface of the wafer and/or heat when the wafer is thermally bonded to the substrate between the thermal head and the platform through the anisotropic conductive film (anis〇tr〇pic c〇nducdve). Foreign matter remaining on the surface of the indenter before and/or during the thermocompression step. Therefore, it is possible to prevent foreign matter from causing indentation defects and even causing wafer cracking. Referring to Figure 1, there is shown a cross-sectional view of a wafer in accordance with a preferred embodiment of the present invention. In FIG. 1, the wafer 100 includes a body 12A, a first pad 130, a conductive bump 140, and a buffer layer 110. The body 120 has an opposite active surface 124 and an inactive surface 122. The first pad 130 is disposed on the active surface 124, and the conductive bump 140 is disposed on the first interface 130. Wherein the first pad 130 is, for example, aluminum, the conductive bump 14 is, for example, gold, lead or tin, and the bump bump metal layer is further disposed between the conductive bump 140 and the first pad 13〇 (under bump metallurgy) , UBM). In this embodiment, the three conductive bumps 140 are correspondingly disposed on the three first pads 130 as an example for description. Further, the buffer layer 110 is formed on the inactive surface 122. The buffer layer 110 is applied before or after the wafer dicing process, by chemical vapor deposition (CVD), physical vapor deposition (PVD), adhesion or coating. Formed on the inactive surface 122. Referring to Fig. 2, there is shown a cross-sectional view showing a state before the step of thermocompression bonding between the wafer and the substrate in accordance with Fig. 1. As shown in FIG. 2, before the wafer 100 and the substrate 230 having the second pads 235 are passed through an anisotropic conductive film 260 for thermal compression bonding between a thermal head 240 and a stage 270, the wafer 100 is processed. The substrate 230 is first aligned such that the conductive bumps 140 of the wafer 100 are opposite to the second pads 235 of the substrate »1 230, and the anisotropic conductive film 260 is between the wafer 100 and the substrate *230. The substrate 230 is on the platform 270 and the thermal head 240 is above the buffer layer 110. The anisotropic conductive film 260 has a plurality of conductive particles 265, but the conductive particles 265 do not electrically conduct the conductive bumps 140 and the second pads 235. The surface of the buffer layer 110 and the thermal head 240 have foreign matter 250, and the buffer layer 110 and the thermal head 240 also have other foreign matter during the thermal compression bonding process between the wafer 100 and the substrate 230. In this embodiment, the substrate 230 may be a thin film transistor (TFT) substrate or a circuit board. The thin film transistor substrate is taken as an example for illustration. The second pad 235 is, for example, indium tin oxide (IT0). φ Please refer to Fig. 3, which is a cross-sectional view showing a state in which the wafer and the substrate are thermocompression-bonded in the second drawing. As shown in FIG. 3, when the wafer 100 and the substrate 230 are subjected to a thermal compression step through the thermal head 240 and the stage 270, the wafer 100 is adhered to the substrate 230 by the anisotropic conductive film 260, and the conductive bumps 140 are bonded. The conductive particles 265 are electrically connected to the second pads 235. Therefore, the display panel 280 including the wafer 100, the substrate 230, and the anisotropic conductive film 260 is completed. Since the buffer layer 110 is formed on the inactive surface 122 and has a hardness lower than that of the body 120 of the wafer 100, the surface of the thermal head 240 may remain on the surface of the thermal head 240 and/or slow in the thermocompression bonding step. The foreign matter 250 nano 1314228 on the surface of the layer 110 is introduced into the buffer layer 110. In this way, it is possible to prevent the occurrence of indentation defects between the wafer 11 and the substrate 230 corresponding to the foreign matter 250, and to prevent the wafer 11 from being broken by the foreign matter 250 during the thermocompression bonding step. However, those skilled in the art to which the present invention pertains may clarify that the technology of the embodiment is not limited thereto. For example, the buffer layer 110 may preferably employ a static dissipative material. In addition, the display panel 280 is, for example, a liquid crystal display panel (LCD panel), an organic light emitting diode (OLED) display panel, or an organic electroluminescence device (OELD). Further, as for the other two electrical components, such as the first electrical component and the second electrical component, which are joined by a heat bonding step between the thermal head and the platform through the anisotropic conductive film. The first electrical component has a first pad. The second electrical component includes a body, a second pad, a conductive bump, and a buffer layer. The body has a first surface and a first surface. The second pad is disposed on the first surface. The conductive bump is disposed on the second pad, and the buffer layer is formed on the second surface. The anisotropic conductive film is disposed between the first electrical component and the second electrical component for bonding the first electrical component and the second electrical component such that the conductive bump is electrically connected to the first pad. When the first electrical component and the second electrical component are thermally pressed through a thermal head and a platform, the first electrical component is bonded to the second electrical component to form an electrical bonding device, and the conductive bump It is electrically connected to the first pad. Further, the buffer layer can accommodate foreign matter remaining on the surface of the buffer layer or on the thermal head before and/or during the thermocompression step. The first electrical component and the second electrical component of the preferred embodiment are respectively a thin film transistor substrate and a wafer. The wafer disclosed in the above embodiments of the present invention and the electrical bonding device and the display panel using the same are formed on the inactive surface of the wafer - a buffer layer having a small hardness relative to the wafer 1314228, which can be performed on the wafer and the substrate The thermal compression step accommodates foreign matter remaining on the surface of the buffer layer and/or on the surface of the thermal head. In this way, it is possible to prevent the occurrence of indentation defects between the wafer and the substrate due to uneven force, and to prevent cracking of the wafer. In view of the above, the present invention has been described above in terms of a preferred embodiment, and is not intended to limit the invention, and various modifications may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a wafer in accordance with a preferred embodiment of the present invention; and FIG. 2 is a cross-sectional view showing the state of the wafer and the substrate before thermoforming. Fig. 3 and Fig. 3 are cross-sectional views showing a state in which the wafer and the substrate of Fig. 2 are subjected to a thermocompression bonding step. [Main component symbol description] 100. Wafer 110: Buffer layer 120: Body 122: Inactive surface 124: Active surface 130: First pad 14〇: Conductive bump 230: Thin film transistor substrate 235: Second pad 1314228 240: thermal head 250: foreign matter 260: anisotropic conductive film 265: conductive particles 270: platform 280: liquid crystal display panel