TWI312570B - - Google Patents

Description

1312570 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit device and an electronic device. [Prior Art] The integrated circuit device for driving a display panel such as a liquid crystal panel has a display driver (LCD driver). This display driver is required to reduce the size of the wafer in order to reduce the cost. However, the size of the display panel incorporated in a mobile phone or the like is approximately constant. • Therefore, when the wafer size is reduced by simply reducing the size of the wafer by simply reducing the integrated circuit device of the display driver, it is difficult to mount. In addition, there are several types of display panels (amorphous TFT, low temperature polysilicon TFT) and the number of pixels (QCIF, QVGA, VGA). Therefore, it is necessary to provide a model in which the user corresponds to various types of display panels such as these. Further, when the layout of the circuit blocks of the integrated circuit device is changed, the influence of the circuit block on the integrated circuit device and other circuit blocks causes problems such as inefficient design and long-term development period. [Patent Document 1] JP-A-2002-222249 SUMMARY OF INVENTION [Problems to be Solved by the Invention] In view of the above technical problems, an object of the present invention is to provide a circuit area reduction and design. An efficient integrated circuit device and an electronic device including the same. (Means for Solving the Problem) The integrated circuit device of the present invention has the first 112460.doc 1312570 side of the short side of the integrated circuit device as the first direction from the side opposite to the third side, and the self-integrated circuit device is long. The second side of the edge; I: the target 4 @ The direction of the fourth side of the pair is the second direction, including the first to the Nth circuit blocks arranged along the first _, the first direction of the edge ^ For the integer of 2 or more, the first to the Nth circuit blocks include at least one memory block of the memory image data, and at least one of the driving data lines is used! The data drive area I, the memory block and the data driver block are arranged adjacent to each other in the first direction. In the present invention, the first to Nth circuit blocks are arranged along the first direction, and the first to Nth circuit blocks include: a memory block and a data driver block. The memory block and the data drive block are adjacent to each other along the first direction. Therefore, compared with the method of arranging the memory block and the data driver block along the second direction, the width of the integrated circuit device in the second direction can be reduced, and the narrow and slender integrated thunder can be provided. Road device. Further, when the structure of the memory block or the data driver block is changed, the influence on other circuit blocks can be suppressed to a minimum, and the design efficiency can be improved. In addition, the foregoing first-Nth circuit block of the present invention may further include: first to third memory blocks (1 is an integer of 2 or more); and each of the first to the first memory regions Block, along the former Cheng policy _ Gu Yu: Court.b has the direction of the Xundi and the first adjacent configuration of the first ~ I data drive block. In this way, the first "complex" block corresponding to the optimal number of blocks of image data bits to be memorized, and the first to the .th data drive block corresponding thereto can be arranged. Further, it is also possible to adjust the width of the integrated circuit device in the direction of the second direction and the length in the first direction by the number of blocks, in particular, the width in the first direction can be reduced. U2460.doc 1312570

In addition, the present invention uses the opposite direction of the first direction as the second direction n, which may be the third direction side of the first memory block (= <) in the first to the mth memory block. Adjacent to the first data drive block in the first-to-first data-driven profit block, 'the first J-side = the first-direction side' is adjacent to the aforementioned first-~^ memory machine. 1 memory block is arranged, placed in front of the J+1 memory block just before the first side of the block, adjacent to the first to the first material drive block in the J+1 data drive block configuration . Further, the present invention may also share a row address decoder between the memory block and the aforementioned J+ memory block. In this way, the circuit can be further reduced in size. In the present invention, the opposite direction of the first direction is taken as the third direction side of the third direction (1 S J < I), and the J-th data driver in the first to the first data driver blocks is spoofed. Before the move m "seven 15 [blocks are configured" in the first direction side of the aforementioned J memory block, the mth data drive block 7 in the block - the first data drive area A 勖 thief & The block 'is arranged adjacent to the TM body block on the first direction side of the aforementioned J+1 data driver block. The first to the first memory block may be from ^ τ

~ The data of each data driver block 俨 均 The distance between the output lines is uniform. Further, in the case where the present invention is accessed from the host side, only the first to the hth memory blocks may be selected to correspond to the storage line. The character of the memory block of the & field is ll2460.doc 1312570. When accessing from the host side, the characters of all the memory blocks of the helmet are selected from the first to the first memory block. It is possible to achieve low power consumption. Furthermore, the invention may also be packaged. A repeater block, each of which is adjacent to the previous > attacking each of the first ~ 苐I ‧ billion body blocks, and arranging a number of repeater blocks

Do not include the current level of the read data signal from each of the above-mentioned -1st to the first memory block, the memory selection signal is activated (initial), before the selection of the first 第 唆 唆 丄 丄 引 第一 第一 第一1 When the Jth memory block (1 S J<I) in the memory block, white A, +, 咕τ4 ^ Read the data from the J § memory block

The ##' is buffered by the buffer corresponding to the transponder block of the aforementioned J., but the memory bank selection signal is turned on/off. When the active J-memory block formation non-selection is actively described, the output state of the buffer corresponding to the repeater block of the aforementioned "remembered block is set to the impedance state. Thus, the memory selection signal of the J memory block becomes inactive (inactive), and when the memory block other than the J memory block is selected, the read data from the selected S memory block is selected. The signal is correctly transmitted by reading the data line. In addition, the present invention may also be arranged in the memory block along the second direction to be connected to the word line of the memory cell of the memory block, and in the memory block along the foregoing In the first direction, the wiring outputs the bit line of the image data stored in the memory block to the data driver block. Thus, the length of the word line can be shortened to correct the signal delay on the word line. 112460.doc •10- 1312570 In addition, the present invention can also be lifted from the arrow F, ...] 4 § the memory block for the aforementioned data drive test & block, dynamic block image data during a horizontal sweep .胄-"Recall that the memory area is so" because the number of memory cells in the second direction of the memory block is reduced, therefore, the width of the memory block in the direction of the second direction of the integrated circuit device can be reduced. 'It is also possible to reduce the product: 2. The invention can also be read and stored in the memory block by scanning a plurality of different word lines in the (10) horizontal scanning period memory block. Image data. In addition, the data driver block may also include a plurality of data drivers stacked in the first direction. (4) Thus, data drivers of various configurations and types can be effectively configured. The first one of the plurality of data drivers may dynamically latch the d/a conversion of the image data of the flash lock from the image data read by the memory block for the second time during the first horizontal scanning, and Outputting the data signal obtained by D/A conversion to the data signal output line, and the second data driver of the plurality of data drivers is locked from the memory block during the foregoing first-level scanning period The second read image data, the D/A conversion of the image data of the lock is performed, and the data signal obtained by the d/a conversion is output to the data signal output line. Thus, the first and second data drivers It is only necessary to latch the image data read for the first time and the second time, and perform D/A conversion. Therefore, the size of the first and second data drivers can be prevented, and the integrated circuit device is in the second. 112460.doc -11· 1312570 In addition, in the present invention, the first and the _th data drivers of the plurality of data drivers may respectively be configured to be configured to be powered by the first voltage level. a first circuit region of the circuit and a second circuit region of the circuit configured to operate at a second voltage level higher than the first voltage level: said first and second data drivers a first circuit region of a data driver is adjacent to the first memory block, and a first circuit region of the second data driver is disposed adjacent to the first memory block. Thus, the first voltage level is configured due to the abutment. It The source of the action

The first and second memory blocks and the first circuit area of the first and second data drivers can improve layout efficiency. In addition, the present invention can also use the number of pixels in the horizontal scanning direction of the display panel as the HPN 'the number of bits of the image data of one pixel portion as the PDB', and the number of blocks of the six-remembered block is regarded as MBN. The number of readings of image data read from the memory block during one horizontal scanning period is rn. 'The sense amplifier block of the memory block includes P sense amplifiers juxtaposed along the second direction, The number p of the aforementioned sense amplifiers is P = (HPNxPDB) / (MBNxRN). Thus, the width of the first to Nth circuit blocks in the second direction can be set to a recording width corresponding to the number of blocks MBN of the block and the number of readings of the image data. Further, the sense amplifier block of the memory block of the present invention may be stacked with a plurality of sense amplifiers in the foregoing first direction. Thus, since the output pitch of the image data supply line from the memory block in the second direction can be reduced, the width of the memory block in the second direction 112460.doc • 12- ϊ 31257 可 can be reduced. In addition, the present invention may also be in the first direction side of the stacking configuration, the first direction side of the second sense amplifier, and the memory cell row of the two columns juxtaposed along the first direction, and the upper side of the memory cell row The bit line is connected to the bit line of the memory cell line of the lower side of the aforementioned _ sense amplification n' to be connected to the aforementioned second sense amplifier. Thus, the memory cell can use a memory cell having a narrow width in the second direction, and it is possible to achieve a high integration of the memory block.

In addition, the output line of the present invention electrically connecting the data driver block and the data for the data line (4) may be disposed on the second direction side of the data driver block, and the aforementioned block The second direction side. In this way, the pad for the data driver can be configured by effectively utilizing the vacant area of the memory block on the second direction side. In addition, the data driver area of the present invention may also include a plurality of sub-pixel driver cells, each of which outputs a data signal corresponding to the image data of the sub-pixel portions, and rearranges the output signals of the sub-pixel driver cells. The rearrangement wiring area for the arrangement order of the lines is provided in the arrangement area of the sub-pixel driver cells. In this way, when the rearranged wiring area is provided in the arrangement area of the sub-pixel driver cell, the switching of the wiring layer of the wiring area between the pad and the data driver block can be minimized, and the cloth can be reduced. The width of the line area in the second direction. In addition, the present invention may also be in the first plurality of sub-pixel driver cells belonging to the first group of the output signal take-out lines of the sub-pixel driver cells of the 112460.doc • 13· 1312570 group. In the arrangement order, the second group of the output signal take-out lines belonging to the sub-pixel driver cells of the second group among the plurality of sub-pixel driver cells are rearranged in the second rearranged wiring region. Thus, the order of the fetch lines of the first group can be rearranged in the first rearranged wiring area. The order of the fetch lines of the second group can be rearranged in the second rearranged wiring area. Therefore, the arrangement order can be rearranged in a plurality of rearranged wiring areas, and thus the width of the wiring area between the pad and the data driver block in the second direction can be further reduced. In addition, the foregoing data driver block of the present invention may also include a plurality of sub-pixel driver cells, each of which outputs image data corresponding to the image of the i sub-pixel portions, and supplies image data from the memory block. The image data supply line to the sub-pixel driver cell is routed along the first direction across a plurality of sub-pixel driver cells. In this way, the image data from the memory block can be efficiently supplied to several sub-pixel driver cells using the image data supply line. In addition, the sub-pixel driver cell of the present invention may also include a D/A converter that uses D/A conversion of gray scale and voltage input image data, and supplies the gray scale voltage gray for the above-mentioned rotation. The order (four) supply line is routed along the aforementioned second direction across a plurality of the aforementioned sub-pixel driver cells. In this way, the gray scale voltage supply line of the plurality of sub-pixel driver cells arranged along the second direction can be effectively supplied with the gray scale voltage supply line along the second direction, thereby improving the layout. effectiveness. In addition, it can effectively be used 112460.doc • 14-1312570 to use the vacant cloth of the take-out line. In addition, the present invention can also be in the arrangement area of the aforementioned sub-replacer along the aforementioned image: the (10) domain of the driver cell and the P-type transistor. In the region, a circuit arrangement region other than the N-type transistor region changer is disposed in the first sub-portion, and the D/A-transfer crystal region and the P-type transistor region of the cell are arranged. Month - direction and configuration _

The second type of N-type supply edge of the N-type transistor region arranged along the second direction can improve the layout efficiency: the impurity: = the gray-scale power is connected and the power other than the D/A converter is configured. When the directional type circuit is in the form of a transistor region and a 电-type transistor region, it can be effectively arranged along the signal flow direction. In addition, the present invention can also be configured by using the N-type transistor and the P-type transistor disposed in the transistor region of the aforementioned arrangement region of the converter, the P-type transistor region, and the P-type transistor. The transfer gate 0 of the device can connect the gray-scale voltage supply line to the transfer-pole type and the p-type transistor, and the layout efficiency can be improved. Furthermore, the present invention may further include: a first interface region disposed along the fourth side of the first to the Nth circuit blocks, and a reverse direction of the second direction; In the fourth direction, a second interface region is provided along the second side on the fourth direction side of the first to Nth circuit blocks. Further, the electronic device of the present invention includes the integrated circuit device of any of the above items and a display panel driven by the integrated circuit device. 112460.doc • 15-1312570 [Embodiment] Hereinafter, an embodiment of the present invention will be described in detail. In addition, it is to be noted that the present invention is not intended to limit the scope of the invention described in the claims, and the configuration of the present invention is not limited thereto. 1. Comparative Example Fig. 1(A) shows an integrated circuit device 500 of a comparative example of the present embodiment. Figure UA) The integrated circuit device 5〇〇 includes: the hidden block block display data • RAM) and the data drive block DB 〇 and the memory block _ and data drive

The actuator block DB is arranged along the D2 direction. Further, the memory block MB and the data driver block DB form an ultra-flat block having a length along the 〇1 direction longer than the width in the 〇2 direction. The image data from the host side is written to the memory block. Then, the data driver block DB converts the digital image data written in the memory block MB into an analog data electric grind, and drives the data line of the display panel. Thus, in Figure UA), the signal flow of the image data is in the direction of the D2. Therefore, the comparison example of Fig. i(a) Lu is matched with the flow of the signal, and the memory block MB and the data driver block DB are arranged along the 〇2 direction. Thereby, a short path between the input and the output can be used to optimize the signal delay and effectively transmit the signal. However, the comparative example of Fig. 1 (A) has the following problems. The integrated circuit device such as a display driver or the like is required to reduce the size of the wafer in order to reduce the cost. However, with the fine processing, when the integrated circuit device 500 is simply reduced to reduce the size of the wafer, the long side 112460.doc -16 - 1312570 is also small in addition to the short side direction. Therefore, as shown in Fig. 2(a), the problem of difficulty in installation is caused. That is, the output pitch must be 22 μm or more, but the simple reduction of Fig. 2(a), such as forming a pitch of 17 Pm, is difficult to install due to the narrow pitch. In addition, the glass frame of the display panel is wide, and the number of glass is reduced, resulting in an increase in cost.

First, the display driver changes the structure of the S memory and the data driver in response to the type of display panel (amorphous TFT, low temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), and the specifications of the product. Therefore, in the comparative example of Fig. 1(A), a certain product is shown in Fig. 1(B), and the structure of the memory and the data drive is changed even if the solder (four) distance, the cell pitch of the memory, and the cell pitch of the data driver are the same. When, as shown in Figure UC), these distances are inconsistent. When the pitch is not uniform as shown in Fig. 1(C), an unnecessary wiring region where the absorption pitch is not used must be formed between the circuit blocks. In particular, in the comparative example of Fig. 1 (A) in which the D direction block is flat, the excess wiring area for which the absorption pitch is not uniform is large. Therefore, the width of the integrated circuit device 500 in the D2 direction becomes larger, and the wafer area increases, resulting in an increase in cost. In addition, in order to avoid this situation, the pad pitch is consistent with the cell pitch, and when the layout of the k-memory and data driver is used, the development period is extended, and V is cost & plus. That is, since the comparative example of Fig. (a) is to individually design the circuit structure and layout of each circuit block, and then perform the work of the matching pitch, etc., an unnecessary vacant area is generated, and design inefficiency occurs. 2. Structure of the integrated circuit device The figure shows a configuration example of the integrated circuit device 112460.doc -17- 1312570 ίο which can solve the above problems. In the present embodiment, the direction from the first side SIM of the short side of the integrated circuit device ι to the third side SD3 is referred to as the first direction ο, and the direction opposite to (1) is the second direction D3. Further, the direction from the second side SD2 of the long side of the integrated circuit device to the fourth side SD4 is the second direction D2, and the direction opposite to D2 is the fourth direction D4. In addition, in FIG. 3, the left side of the integrated circuit device 10 is the first side SD1, and the right side is formed with the third side SD3, but the left side is also the second side SD3, and the right side is the first side sdi. As shown in Fig. 3, the integrated circuit device 10 of the present embodiment includes the first to Nth circuit blocks CB1 to C101 arranged in the D1 direction. That is, in the comparative example of Fig. 1(A), the circuit blocks are arranged in the 〇2 direction and the circuit blocks CB1 to CBN of the present embodiment are arranged in the D1 direction. Further, each of the circuit blocks does not form an ultra-flat block as in the comparative example of Fig. (A), but forms a relatively square block.

Further, the 'integral circuit device 1' includes the output side i/f region 12 provided along the side SD4 in the D2 direction side of the first-Nth circuit block CB1 to CBN (generalized §, the first interface region) ). Further, the D4 direction side of the first to Nth circuit blocks CB1 to CBN includes an input side I/F area 14 (in a broad sense, a second interface area) provided along the side SD2. More specifically, the output side I/F area 12 (first I/O area) is disposed on the D2 direction side of the circuit blocks cbi to CBN without passing through other circuit blocks or the like, and further, the input side I/; The F region 14 (second I/O region) is disposed on the D4 direction side of the circuit block cb^cbn without passing through other circuit blocks or the like. That is, in the portion where at least the data driver block exists, there is only one circuit block (data drive block) in the D2 direction. In addition, the integrated circuit device 10 is used as the IP (Intellectual Property H2460.doc -18·1312570) When the core is assembled in another integrated circuit device, it may be configured not to provide at least one of the regions 12 and 14. The output side (display panel side) I/F area 12 is a region 117 which is an interface with the display panel, and includes various components such as a pad, an output transistor connected to the pad, and a protective member. Specifically, 'the output transistor for outputting a data signal to the data line and outputting a scan signal to the scanning line is included. In addition, when the display panel is a touch panel, the input transistor may be included. The input side (host side) I/F area 14 is an area that interfaces with the host (Mpu, image processing controller, baseband engine), and may include: a pad, and a connection to the Tan pad (input output) Various components such as a transistor, an output transistor, and a protection element. Specifically, it includes: an input transistor for inputting a signal (digital signal) from a host, and an output transistor for outputting a signal to a host. In addition, it is also possible to provide an output side or an input side I/F area along the side sm of the short side. Further, bumps or the like which become external connection terminals may be provided in the I/F (interface) region 12, 14, and may be provided in other regions (first to Nth circuit blocks CB1 to CBN). It is provided in the I/F region 12, and in the case of "outside regions", it is realized by using a small bump technique other than gold bumps (bumping technology using a resin as a core, etc.). Further, the first to the first circuit The blocks CB1 to CBN may include at least two (or three) different circuit blocks (circuit blocks having different functions). For example, when the integrated circuit device 10 displays the actuator, the circuit block can include : At least two of the blocks of H' memory, scan driver, logic circuit, gray-scale voltage generation circuit and power supply circuit. More specifically, 112460.doc •19- 1312570, circuit blocks CB1~CBN at least It may include: a block of data driver and logic circuit, and further may include a block of gray scale voltage generating circuit. In addition, in the case of memory internal storage type, a block of memory may further be included. Various types are shown in FIG. The display driver and the built-in circuit block thereof. The display driver for the amorphous TFT (thin film transistor) panel built in the memory (RAM), the circuit blocks CB 1 C CBN include: memory, data driver ( Source driver ), scan driver (gate driver), logic circuit (gate array circuit), gray scale voltage generation circuit (γ correction circuit), and power supply circuit block. In addition, built-in memory low temperature polysilicon (LTps) TFT panel With the display driver 'because the scan driver can be formed on the glass substrate, the block of the scan driver can be omitted. In addition, the amorphous TFT panel with no built-in memory can omit the block of memory, non-incorporated memory. The low-temperature polysilicon TFT panel can omit the block of the memory and the scan driver. In addition, the CSTN (color twisted nematic) panel and the TFD (thin film diode) panel can omit the block of the gray scale voltage generating circuit. 5(A) and (B) show an example of a planar portion of the integrated circuit of the display driver of the present embodiment. Fig. 5(A)(B) shows an example of an amorphous TFT panel with built-in memory. Figure 5 (A) shows the QCIF, 32 gray-scale display driver as the target, Figure 5 (B) uses the QVGA, 64 gray-scale display driver as the target. Figure 5 (A) (B), the first ~ Nth circuit block cm~CBN contains the first - ~ fourth Broadly speaking, memory and block MB based on the first ~ .I〗 memory block region of 2 or more integer). Further, for each of the first to fourth memory regions 112460.doc • 20.1312570 blocks MB1 to MB4, the fourth to fourth data driver blocks DB1 to DB4 are arranged adjacent to each other along the D1 direction (in a broad sense) Specifically, the first to the first data driver block p, specifically, the memory block MB丨 and the data driver block DB1 are adjacently arranged along the D1 direction, and the memory block MB2 and the data driver block DB2 are along the D1. The direction is adjacently arranged. Then, the image data (display data) used by the data driver block DB 1 for driving the data line is memorized by the adjacent memory block MB1, and the image driver block DB2 uses the image for driving the data line. The data is memorized by the adjacent memory block Μβ2. Furthermore, Fig. 5(A) is the D3 direction side of the MB1 (in the broadest sense, the J memory block. ISJd) in the memory blocks MB1 to MB4. DB1 (in a broad sense, the jth data driver block) in the data drive block DB1 to DB4 is arranged. Further, in the D1 direction side of the memory block MB1, the memory block MB2 is adjacently arranged (in a broad sense) For the j+i memory block). Then, in the D1 direction side of the MB memory block MB2, the adjacent data driver block DB2 (broadly speaking, the j+1th data driver block) ^ the memory block MB3, MB4 and the data driver block The configuration of DB3 and DB4 is also the same. Thus, Figure 5(A) is for the boundary line of MB 1, MB2, line-symmetrically configuring MB1, DB1 and MB2, DB2, and the boundary line between MB3 and MB4, and line-symmetrically configuring MB3. DB3 and MB4, DB4. In addition, in Fig. 5(A), DB2 and DB3 are arranged adjacent to each other, but other circuit blocks may be disposed between them without being adjacent thereto. In addition, Fig. 5(B) is in memory. In the MB3 (the Jth memory block) of the block MB1-MB4, the D3 direction side is adjacent to the configuration data driver block 112460.doc -21 · 1312570 DB1 in DB1 to DB4 (the Jth data drive block). In addition, DB2 (J+1th data driver block) is placed in the D1 direction side of MB1. In addition, MB2 (the memory block of J+1) is placed in the D1 direction side of DB2. DB3, MB3, DB4, MB4 In the same manner, in FIG. 5(B), MB1 and DB2, MB2 and DB3, MB3 and DB4 are arranged adjacent to each other, but these may not be adjacent to each other. Other circuit blocks are disposed between them. With the layout configuration of FIG. 5(A), it can be between the memory blocks MB1 and MB2, and between MB3 and MB4 (the Jth and J+1th memory blocks) The advantage of sharing the row address decoder. In addition, with the layout configuration of FIG. 5(B), there is a cloth signal output line that can output the data driver blocks DBi to DB4 to the output side I/F region 12. The line spacing is uniformed to improve the wiring efficiency. Further, the layout of the integrated circuit device 10 of the present embodiment is not limited to those shown in Figs. 5(A) and (B). If the number of blocks in the memory block or the data drive block is 2, 3 or more, the block may not be divided to form a memory block or a data drive block. In addition, it can be modified that the memory block and the data drive block are not adjacent to each other. Alternatively, the memory block, the scan driver block, the power supply circuit block, or the gray scale voltage generating circuit block may be omitted. Further, between the circuit blocks CB1 to CBN and the output side I/F area 12 or the wheel-in side i/F area 丨4, a circuit block having a very narrow width in the D2 direction (a slim circuit below WB) may be provided. Block). In addition, the circuit blocks CB1 C CBN may also include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. The scan driver circuit and the power supply circuit can also be constructed as one circuit block. 112460.doc • 22· 1312570 Fig. 6(A) shows an example of a cross-sectional view of the integrated circuit device 10 of the present embodiment taken along the direction D2. At this time, W1, WB, and W2 are widths of the output side I/F area 12, the circuit blocks CB1 to CBN, and the input side I/F area 14 in the D2 direction, respectively. Further, the width of the W-series circuit device 10 in the D2 direction. As shown in FIG. 6(A), this embodiment can be formed in the D2 direction between the circuit blocks CB1 to CBN (data driver block DB) and the output side and the input side I/F areas 12 and 14 without passing through other circuits. Block. Therefore, it can be

Wl+WB + W2SW<Wl+2xWB + W2, and an elongated integrated circuit device can be realized. Specifically, the width W in the D2 direction may be W < 2 mm, and more specifically ' may be W < 1 _ 5 mm. In addition, when considering wafer inspection and mounting, it must be W > 0.9 mm. Further, the length Ld in the longitudinal direction may be 15 mm < LD < 27 mm. Further, the wafer shape ratio SP = LD / W may be sp > io' and more specifically sp > 12. Further, the widths W1, WB, and W2 of FIG. 6(A) are the transistor formation regions (bulk regions) of the output side Ι/ρ region 12, the circuit blocks CB1 to CBN, and the input side I/F region 14, respectively. The width of the active area). That is, in the I/F regions 12, 14, an output transistor, an input transistor, an input/output transistor, and an electrostatic protection element transistor are formed. Further, a transistor constituting the circuit is formed in the 纟 circuit blocks CB1 to CBN. Wi, wb is determined by using a well region or a diffusion region forming such a transistor as a reference. In order to realize a narrower and slender integrated circuit device, bumps (active faces & blocks) must also be formed on the transistors of the circuit block CB1 CBN. Specifically, the core is formed of a resin, and a resin core bump or the like in which a metal layer is formed on the surface of the tree in the crystal (active region) is formed. Then, the bump 112460.doc -23· 1312570 (external connection terminal) is connected to the bumps arranging the MI/F regions 12, 14 by metal wiring. Wi, WB, and W2 of this embodiment are not the width of the formation region of such a bump, but the width of the transistor formation region formed under the bump.

Further, the widths of the respective circuit blocks CB1 to CBN in the D2 direction can be unified to the same width. At this time, the widths of the respective circuit blocks need only be substantially the same, and the difference between the extents of the number of μηι to 20 μιη (tens of μm) is within the allowable range. Further, in the case where there are circuit blocks having different widths in the circuit blocks CB1 to CBN, the width WB may be the maximum width among the widths of the circuit blocks CB1 to CBN. The maximum width at this time can be the width of the data drive block in the D2 direction. In the case of an integrated circuit device with built-in memory, it can be the width of the memory block in the D2 direction. Further, a vacant area having a width of about 20 to 30 μm may be provided between the circuit blocks CB1 to CBN and the I/F areas 12, 14. Further, in the present embodiment, in the output side I/F area 丨2, pads having a order of 1st order or several steps in the 〇2 direction can be arranged. Therefore, considering the width of the pad (such as 〇. i mm) or the pad pitch, the width W1 of the output side j/f region 丨2 in the D2 direction may be 0.13 mm SWlS 0.4 mm. Further, in the input side Ι/F region 14, a pad having a step of 1 order in the D2 direction can be disposed, so the width W2 of the input side I/F region 14 can be 0.1 minSW2S0.2 mm. In addition, in order to realize the elongated integrated circuit device, the logic signal from the logic circuit block and the gray from the gray scale voltage generating circuit block must be formed on the circuit blocks CB1 C CBN by global wiring. For the voltage signal or the power supply wiring, the total wiring can be as large as 0.8~0.9 mm. Therefore, considering these 112460.doc -24-1312570, the width WB of the circuit blocks CB1 to CBN can be 0.65 mmSWBS1.2 mm ° and then even Wl = 0.4 mm, W2 = 0.2 mm, due to 0.65 mmS WBS 1.2 Mm, so WesWl+Wa is established. In addition, in the case of the minimum value of Wl, WB, and W2, Wl = 0.13 mm, WB = 〇.65 mm, and W2 = 0.1 mm, and the width of the integrated circuit device forms W = 0.88 mm. Therefore, W = 0.88 mm < 2xWB = l_3 mm holds. In addition, in the case of the maximum value of Wl, WB, and W2, Wl = 0.4 mm, WB = 1.2 mm, and W2 = 0.2 mm, and the width of the integrated circuit device forms w = 1.8 mm. Therefore, W = 1.8 mm < 2xWB = 2_4 mm holds. Therefore, the relationship of W < 2xWB is established, and an elongated integrated circuit device can be realized. In the comparative example of Fig. 1(A), as shown in Fig. 6(B), two or more circuit blocks are arranged along the D2 direction. Further, in the D2 direction, a wiring area is formed between circuit blocks or between a circuit block and an I/F area. Therefore, the width w of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a narrow elongated wafer cannot be realized. Therefore, even if the wafer is reduced by the fine processing, as shown in Fig. 2(A), the length LD in the D1 direction (longitudinal direction) is shortened, and the output pitch is formed at a narrow pitch, which causes difficulty in mounting. On the other hand, in the present embodiment, as shown in Figs. 3 and 5(A) and (B), a plurality of circuit blocks CB1 to CBN are arranged along the D1 direction. Further, as shown in FIG. 6(A), a transistor (circuit element) (active surface bump) can be disposed under the pad (bump). In addition, circuit blocks or circuit blocks and "regions" may be formed by global routing formed above the local (1 〇cal) wiring of the wiring within the circuit block (below the underlying pad). Therefore, as shown in Fig. 2(B), at 112460.doc • 25· 1312570, the length LD of the integrated circuit device 10 in the D1 direction is maintained, and the width in the D2 direction can be reduced. Therefore, an ultra-narrow elongated wafer can be realized. Therefore, if the output pitch can be maintained at 22 μβ1 or more, the mounting can be facilitated. Further, since the present embodiment is configured by arranging a plurality of circuit blocks CB1 CBN along the D1 direction, It is easy to change the specification of the product, etc. That is, since the products of various specifications can be set using a common platform, the efficiency of the juice can be improved. As shown in Fig. 5(A), even the number of pixels and the number of gray scales of the display panel are displayed. In the case of subtraction, it is only necessary to increase or decrease the number of blocks in the memory block or the data drive block, or the number of times the image data is read during one horizontal scanning period, etc. Further, 'Fig. 5(A)(B) An example of an amorphous TFT panel with built-in memory, but In the case of developing a product for a low-temperature polysilicon TFT panel of a built-in memory, it is only necessary to remove the scan driver block, that is, η* from the circuit blocks CB1 to CBN. Further, in the case of developing a product other than the built-in memory, Therefore, it is only necessary to remove the memory block. Thus, even if the circuit block is removed in accordance with the specifications, the influence of the circuit block on other circuit blocks can be minimized in the present embodiment, thereby improving the design efficiency. In the form, the width (height) of each of the circuit blocks CB1 to cBn in the D2 direction can be unified into the width (height) of the data driver block or the memory block. Then, the number of transistors in each circuit block is increased or decreased. The adjustment can be made by increasing or decreasing the length of each circuit block in the D1 direction, thereby making the design more efficient. As shown in Fig. 5(A)(B), even the gray scale voltage generating circuit block or the power circuit area The structural change of the block, and the increase or decrease of the number of transistors can still be determined by increasing or decreasing the gray-scale voltage generation circuit block and the length of the power supply circuit block in the direction of D1. 112460.doc -26- 1312570 In addition, For example, a method of arranging a data driver block in the (1) direction and a plurality of other circuit blocks such as a memory block along the D1 direction on the D4 direction side of the data driver block is also considered. In the comparative example, a data driver block having a large width is interposed between other circuit blocks such as a memory block and an output side i/f area, so that the width W of the integrated circuit device in the D2 direction becomes large, and it is difficult to achieve narrowness. In addition to the slender wafer. 2, the extra wiring area between the data driver block and the memory block causes a larger width w. In addition, when the structure of the data driver block or the memory block is changed, In the figure KB) (C), the problem of inconsistent distance is explained, and the design efficiency cannot be improved. Further, the third comparison of the present embodiment also considers a method in which only the circuit blocks (e.g., data driver blocks) of the same function are divided by blocks, and the parallel arrangement is performed in the direction of 〇1. However, since the third comparative example can only have the same function (e.g., the function of the data driver) in the integrated circuit device, it is impossible to realize the introduction of various products. The circuit blocks CB1 to CBN of this embodiment include at least two circuit blocks of different functions. Therefore, as shown in Fig. 4 and Fig. 5(A), there are advantages of an integrated circuit device which can provide various types of display panels corresponding to various types of display panels. 3. Circuit configuration Fig. 7 shows an integrated circuit device The circuit configuration of the integrated circuit device 10 is not limited to that of Fig. 7, and can be implemented by various modifications. The memory 20 (display data RAM) memorizes image data. The memory cell array 22 includes several Memory cells' and memorize the image data (display data) of at least one frame (1 picture). At this time, '1 pixel is R, G, 3, 3 112460.doc -27- 1312570 sub-pixels ( 3 points), each sub-pixel is stored as image data of 6-bit (k-bit). The column address decoder 24 (MPU/LCD column address decoder) performs decoding processing of the column address and performs memory. The processing of the character line of the cell array is performed. The row address decoder 26 (MPU row address decoder) performs decoding processing of the row address, and performs selection processing of the bit line of the memory cell array 22. The read circuit 28 (MPU write/read circuit) performs the pair of memory cells 22 The process of inputting image data and reading the image data from the memory cell array 22. In addition, the access area of the memory cell array 22 is defined by using the start address and the end address as rectangles for the vertices. That is, the memory access is performed by defining the access area 'with the row address and the column address of the start address, the row address and the column address of the end address. Logic circuit 40 (such as automatic configuration wiring) The circuit generates a control signal for controlling the display time or a control signal for controlling the data processing time, etc. The logic circuit 40 can be formed by automatically configuring wiring by a gate array (G/A) or the like. The control circuit 42 generates Various control signals are used to control the entire apparatus. Specifically, the adjustment data (γ correction data) of the output gray scale characteristic (γ characteristic) is supplied to the gray scale voltage generating circuit 110 to control the voltage generation of the power supply circuit 9 . Controlling the write/read processing of the memory using the column address decoder 24, the row address decoder 26, and the write/read circuit 28. The display time control circuit 44 generates a control display time. The control signal is used to control the reading of the image data from the memory to the display panel side. The host (MPU) interface circuit 46 generates internal pulses for each access from the host to implement access to the host interface of the memory. RGB interface The circuit 48 realizes that the RGB data of the moving 写入 is written into the RGB interface of the memory by the dot clock. Alternatively, only the 112460.doc • 28-1312570 host interface circuit 46 and the fine interface circuit 48 may be configured. In the shot of the 'host interface interface and the interface circuit I phantom pixels access to the memory 20 in the early position. In addition, for the data driver 5, the dream is separated from the domain interface circuit 46 'RGB interface circuit 48 internal display In the inter-subsidiary, the bus cycle transmission is specified by the line address, and the image feed device 50, which is read in line units, drives the circuit for the data line of the display panel, and its configuration example is shown in FIG. 8(4). The data lock circuit 52卩-1 locks the digital image data from the memory. The D/A conversion circuit 54 (electrical (four) selection circuit) locks the D/A conversion of the digital image data in the data f_1 lock circuit 52 to generate a feed voltage. Specifically, a gray scale voltage (reference voltage) is received from the gray scale voltage generating circuit 110, and a voltage corresponding to the digital image data is selected from the plurality of gray scale electric power M. Output as a data voltage. The output circuit 56 (drive circuit, buffer circuit) buffers the data voltage from the D/A conversion circuit 54 and outputs it to the data line ' of the display panel to drive the data line. In addition, the data driver may not be included in a part of the output circuit 56 (such as the output section of the operational amplifier/, and is disposed in other areas. The scan driver 70 is a circuit for driving the scan line of the display panel, FIG. 8 (B) Let the configuration example be shown. The shift register 72 includes a plurality of flip-flops sequentially connected, and is synchronized with the shift clock signal SCK, and sequentially shifts the enable wheel-in output signal EIO. The level shifter % converts the voltage level from the shift register to the high voltage level for scan line selection. The output circuit 78 converts the output by the level shifter 76. The voltage is delayed by 112460.doc •29·!31257 and output to the scan line of the display panel to select the drive scan line. In addition, the scan driver 70 can also adopt the configuration shown in Fig. 8(C). c) =, 'Scan address generation circuit 73 generates a scan address and outputs, address decoding: performs a decoding process of the scan address. Then, by this decoding process, the scan line of the feature is passed through the level shifter. 76 and output circuit? 8 and output power. ^ Power supply 90 is a circuit for generating various power supply voltages, and its configuration example is shown in Fig. 9 (α). The boosting circuit 92 uses a boosting capacitor or a boosting transistor to charge an input power supply voltage or an internal power supply voltage by a charge pump method. Boosting, generating a circuit for boosting voltage, and may include a 〜4th boost circuit, etc. The boost circuit 92 can generate a high voltage used by the scan driver 7 or the gray scale voltage generating circuit 110. The regulator circuit 94 performs level adjustment of the boosted voltage generated by the booster circuit 92. The vc〇M generating circuit generates a voltage of vc〇M supplied to the opposite electrode of the display panel and outputs the voltage. The control circuit 98 performs the control. The controller of the power supply circuit 9 includes various control registers, etc. The gray scale voltage generating circuit (γ correction circuit) n〇 generates a gray scale voltage circuit. FIG. 9(B) shows a configuration example thereof. The circuit ιΐ2 (voltage dividing circuit) outputs the selection voltages vs VS 255 (in a broad sense, R selection voltages) according to the high-voltage power supply voltages VDDH and VSSH generated by the power supply circuit 9 。. Specifically, the power is selected. The voltage generating circuit 112 includes a step resistor circuit having a plurality of resistor elements connected in series, and then outputs a voltage of VDDH and VSSH by the step resistor circuit as the selected power VS0 to VS255. The gray scale voltage selecting circuit 114 By logic 112460.doc -30- 1312570 circuit 40, according to the adjustment data of the gray scale characteristic of the adjustment register IB according to 3, and the selection voltage VS0~VS255, such as 64 gray scale, select The voltage of 64 (broadly speaking, 8. R > s) and the output gray scale voltage VO V63. Thus, a gray scale voltage corresponding to the optimum gray scale characteristic (丫 correction characteristic) of the display panel can be generated. Further, in the case of the polarity inversion driving, the step resistor circuit for the positive polarity and the step resistor circuit for the negative polarity may be provided in the selection voltage generating circuit 112. Further, the resistance values of the respective resistance elements of the step resistance circuit may be changed in accordance with the adjustment data set in the adjustment register 116. Further, an impedance conversion circuit (an operational amplifier to which a voltage repeater is connected) may be provided in the selection voltage generating circuit 2 or the gray scale voltage selecting circuit 114. Fig. 10(A) shows a configuration example of each DAC (digital analog converter) included in the D/A conversion circuit 54 of Fig. 8(A). Each of the DACs of Fig. 1 (Α) can be set as each sub-pixel (or each pixel), and is constituted by a *R〇M decoder or the like. Then, according to the 6-bit digital image data D记忆~D5 from the memory 20 and its inverted data class~XD5,# is selected by any one of the gray-scale voltages V0-V63 from the gray-scale (4) generating circuit (10), and The image data D〇~D5 is converted into an analog voltage. Then, the analog voltage signals DAQ (DAQR, DAQG, DAQB) are output to the output circuit 56. In addition, when the display signal for R, G, and B is multiplexed and transmitted to the display driver by a display driver for a low-temperature polysilicon TFT or the like (in the case of FIG. 10(C)), i can also be used. D/A conversion is performed for the shared image data of R, g, and B. In this case, each of the DACs of Fig. 10(A) is set for each pixel. 112460.doc -31 - 1312570 Fig. 10(B) shows a configuration example of each of the output portions SQ included in the output circuit 56 of Fig. 8(A). Each of the output portions SQ of Fig. 10(B) can be set for each pixel. Each output unit SQ includes an impedance conversion circuit OPR, OPG, and OPB (an operational amplifier connected to a voltage repeater) for R (red), G (green), and b (blue), and performs 彳s number DAQR from the DAC. The impedance conversion of DAQG and DAQB, and output the data signals DATAR, DATAG, and DATAB to the data signal output lines for R, G, and B. In addition, in the case of a low-temperature polysilicon TFT panel, the switching elements (switching transistors) SWR, SWG, and SWB shown in Fig. 10(C) may be provided, and the impedance conversion circuit 0P outputs data for R, G, and b. The signal signal DATA to which the signal is multiplexed. In addition, several pixels can be included for data signal multiplexing (multiplexing). Further, an impedance conversion circuit of Fig. 10 (B) and (c) may be omitted in the output portion SQ, and only a switching element or the like may be provided. 4. Adjacent data driver block and memory block In the present embodiment, as shown in Fig. 11 (4), the data driver block DB and the memory block MB are arranged adjacent to each other in the m direction. In this regard, the comparison of Fig. 1(A) is as shown in Fig. 12(A), and the memory block MB and the data driver block are coupled to the flow direction of the signal, and are arranged in the D2 direction along the short side direction. Therefore, the width of the integrated circuit device in the (five) direction becomes large, and it is not easy to realize a narrow elongated wafer. In addition, due to the change of the number of pixels of the display panel, the specification of the display driver, and the structure of the memory cell, the width of the 6-fold memory block MB or the data driver block 〇8 in the D2 direction and the length in the D1 direction change. It also affects other circuit blocks, resulting in inefficient design. 112460.doc •32- 1312570 Conversely, in the present embodiment, since the data driver block DB and the memory block MB are arranged along the D1 direction, the width W of the integrated circuit device in the 〇2 direction can be reduced, and The ultra-narrow elongated wafer shown in Fig. 2(B) is realized. Further, even if the number of pixels of the display panel or the like changes, as shown in Fig. 1(B), by dividing the memory block or the like, it is possible to correspond thereto, and thus the design is made efficient. Further, in Fig. 12(A), since the word line WL is arranged along the 〇1 direction in the longitudinal direction, the signal delay on the word line WL becomes large, and the reading of the image data is sluggish. In particular, since the word line WL connected to the memory cell is formed by the polysilicon layer, the problem of the signal delay is severe. At this time, in order to reduce the signal delay, a method of setting the buffer circuits 520, 522 shown in Fig. 12 (B) is also employed. However, when this method is employed, the circuit scale of this portion becomes large, resulting in an increase in cost. On the other hand, in the present embodiment, as shown in FIG. 11(A), in the memory block MB, the word line is drawn along the D2 direction in the short-side direction, and the bit is arranged along the D1 direction in the longitudinal direction. Yuan line BL. Further, this embodiment is in the width of the D2 square • Xiao integrated circuit device. Therefore, the length of the word line WL in the memory block mb can be shortened, and the signal delay on the WL can be significantly reduced as compared with the comparison example of Fig. 12(A). In addition, since it is not necessary to provide the buffer circuits 520, 522 shown in the figure, the circuit area is also reduced. Further, in the comparative example of Fig. 12(A), even when the access area from a part of the memory is accessed from the host, the word line WL which is long in the 01 direction and has a large parasitic capacitance is selected, so that power consumption increases. On the other hand, as shown in FIG. 11(B), by means of dividing the memory in the direction block, when the host accesses (from the host side, I12460.doc • 33 _ 1312570 takes N*), only the selection corresponds to The word line WL of the memory block (the first memory block) of the access area is accessed, so that low power consumption can be achieved. Further, the WL of Fig. 11(A) is connected to the word line of the memory block MBi memory cell. That is, it is connected to the local word line of the gate of the transfer transistor of the memory cell. In addition, the figure u(A)tBL is used to output the bit line of the image data (the hidden data k number) of the memory block (memory cell array) to the data driver block DB. That is, the signal of the image data stored in the memory block MB is output from the memory block mb to the data drive block DB in the direction of the bit line muscle. As shown in the comparative example of Fig. 12(A), the method of arranging the memory block mb and the billet driver block DB along the D2 direction is reasonable in consideration of the direction in which the signal flows. In this regard, the present embodiment is shown in the DB as shown in Fig. 11(A)! The output line OQL of the data signal from the data driver block DB is wired in the 2 direction. In addition, in the output side I/F area 12 (first interface area), the data signal output line is routed along the D1 (D3) direction. barrier. Specifically, in the output side I/F area 12, the global wiring of the upper layer of the local wiring (transistor wiring) in the region is used, and the data signal is output along the (1) direction. Line DQL. In this way, even if the data driver block DB and the memory block are arranged in the 〇1 direction, the data signal from the Μ can be correctly input to the display panel via the pad. In addition, 'when the data signal output line is wired as shown in π(Α)', the output side ι/ρ area can be used to connect the data output line DQL to * 'js -3⁄4. ^ , soldering, etc. It is possible to prevent an increase in the width w of the integrated circuit device in the D2 direction. 112460.doc -34- 1312570 5. Details of memory block and data driver block 5.1 Block division As shown in Fig. 13(A), the number of pixels of the display panel in the vertical scanning direction (data line direction) is VPN=320, the number of pixels in the horizontal scanning direction (scanning line direction) is the panel of QVGA with HPN=240. Further, the number of bits of the image (display) data of one pixel portion, PDB, R, G, and B, is 6 bits, and is PDB = 18 bits. In this case, the number of bits of image data required for display of one frame portion of the display panel is VPNxHPNxPDB = 320x240x1 8 bits. Therefore, the memory of the integrated circuit device memorizes at least the image data of the 320x240x1 8-bit portion. In addition, the data driver outputs a data signal of HPN=240 portions (corresponding to 240><18-bit portion of the image data to the display panel during every horizontal scanning period (during each scanning of one scanning line) Data signal). In Fig. 13(B), the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. Further, the memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. Therefore, each of the data driver blocks DB1 to DB4 outputs a data signal of HPN/DBN = 240 / 4 = 60 portions to the display panel every one horizontal scanning period. Further, each of the memory blocks MB 1 to MB4 memorizes (VPNxHPNxPDB) / MBN = (3 2 〇 x 24 〇 x 18) / 4-bit portion of the image data. Further, as shown in Fig. 13 (B), the memory block mb 1 and MB 2 of the present embodiment share the row address decoder CD12. Further, the memory blocks MB3 and MB4 share the row address decoder CD34. As shown in the comparison example of FIG. 12(A), since the row address decoder is disposed on the D4 direction side of the memory cell array, the row address decoder cannot be shared as shown in FIG. 13(B) of 112460.doc • 35· 1312570 FIG. 13(B). . On the other hand, in the present embodiment, since the row address decoders CD 12 and CD 34 can be shared, it is possible to reduce the area and cost of the circuit. Further, when the data driver blocks DB1 to DB4 and the memory blocks MB1 to MB4 are arranged as shown in Fig. 5(B), the sharing of such row address decoders cannot be performed. However, Fig. 5(B) has the advantage of being able to uniformize the distance between the data signal lines from the data driver block and to facilitate the wiring pullback. 5.2 Reading a number of times during one horizontal scanning In Fig. 13(B), each data driver block 〇] 31 to 〇 34 outputs 60 pieces of data signals during one horizontal scanning period. Therefore, it is necessary to read 240 pieces of image data corresponding to the data signal during each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4. However, when the number of bits of image data read during each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) juxtaposed in the D2 direction. Therefore, the width of the integrated circuit device in the D2 direction w is narrowed. In addition, the length of the word line is also a problem of delay = delay. ° I, this embodiment is (4) from each memory block to 4 pairs of data driver blocks ~ DB4, 纟i horizontal scanning period: owe (RN times) read memory in each memory block MB1 ~ MB4 method of shadow. This 'Beca' shows A1, A2 in Figure 14. During the Hgj horizontal scan, only the (10)4 body access signal MACS (character selection signal) forms active (high/bad, from each memory block to each data) The driver block, in i 112460.doc -36 - 1312570, is set in the data drive horizontal scanning period to read the RN = 2 times image data in the block of Figure 15 of the first, the first - 资. Driver DRa, DRb package data latch circuit 'according to A3, A4 _ 八 八 不 不 latch signal LATa LATb 'latch read image data. ' After sentence, first and second data listener DRa, DRb contains D/A conversion mine said ^ ~ (four) circuit 'into (four) image data D / A conversion, DRa, DRb contains the wheel of snow as shown in the circuit such as A5, A6, will be D The data signal obtained by /A conversion is DATAa, DATAb is output to the data nickname output line. Then, as shown in A7, the pixels of the panel are displayed.

The scanning signal SCSEL of the gate of the TFT _ is actively generated, and the data signal is held in each pixel of the display panel. The other image 14 reads the image data twice during the first horizontal scanning period and outputs the data signal (four) heart DATAb to the data signal output line during the same first-level scanning period. However, it is also possible to read the image data twice during the first horizontal sweep (4), and to output the data signal ATAb corresponding to the image data of (10) to the output of the bedding material during the second horizontal sweep. ,line. Further, Fig. (10) shows the case where the number of readings RN = 2, but it is also RN ^ 3. According to the method of Fig. 14, as shown in Fig. 15, the image data corresponding to the greedy signals of 30 σρ points are read from the respective memory blocks, and the data drivers DRa, DRb rotate the data signals of 30 parts. Thereby, 60 pieces of data signals are outputted from each data driver block. Thus, in the figure "from the memory block, the image data corresponding to the data signal of the 3 〇 section is read in one reading. Therefore, the method of reading only once during the horizontal scanning period Comparing, the number of memory cells and sense amplifiers in the D2 direction of Fig. 15 can be reduced. 112460.doc -37- 1312570 Thus, the width of the integrated circuit device in the D2 direction can be reduced, and the figure shown in Fig. 2(B) can be realized. The ultra-narrow slender wafer, especially the length of one horizontal sweep period is 52 psec in the case of QVGA. In addition, the read time of the memory is 40 nsec, which is much shorter than 52 psec. Therefore, even if it will The number of readings during the i horizontal scanning period has been increased from the number of times to several times, and the image of the display characteristics is not large.

In addition, FIG. 13(A) is a display panel of QVGA (32〇x240). However, when the number of readings in one horizontal scanning period is a ruler, it may correspond to a display panel of VGA (640×480). Can increase the freedom of design. In addition, in a single reading during one horizontal scanning period, the column address decoder (word line selection circuit) may select the number of different word lines in each memory block during one horizontal scanning period. Alternatively, the address decoder (word line selection circuit) can implement the second method of selecting the same word line in each memory block several times during horizontal scanning. Alternatively, it may be implemented by combining both the first and second methods.乂3 Feeder Driver and Driver Cell Figure 15 shows an example of the configuration of the driver cell included in the data driver and data driver. As shown in Fig. 15, the data driver block includes a plurality of data drivers DRa, which are arranged along the D1 direction, and are configured (first to first claw data driving states). Further, each data drive 1DRa, and DRb includes a plurality of (in other words, Q) drive cells DRC1 to DRC30. The first material feeder DRa selects the word line WLla of the memory block, as shown in A1 of FIG. 14 , when the white seven, 5 memory block reads the first image data, according to FIG. 3 (4) Signal _, the image data read by the flash lock. In the 112460.doc -38- 1312570, the d/a conversion of the image data of the flash lock is performed, and the data signal DATAa corresponding to the first image data is output to the data signal output line as indicated by A5. In addition, the second data driver DRb selects the word line WL~lb of the memory block as shown in FIG. 14 VIII, and reads the second image data from the memory block according to A4. The latch k唬LATb latches the image data read. Then, the input image of the +# + & 1 lock image-D/A conversion of the bedding material, and the material signal corresponding to the second reading of the image data is outputted to the data signal as shown in FIG. Output line. Thus, each of the data drivers DRa, DRb outputs a data signal corresponding to a strip portion corresponding to 6 pixels by outputting a data signal corresponding to 3 部分 pixels of 3 像素 pixels. As shown in Fig. 15, when a plurality of data drivers DRa and DRb are arranged (stacked) in the DI direction, it is possible to prevent the width w of the integrated circuit device from being increased in the D2 direction due to the size of the data driver. In addition, the data driver adopts the (4) configuration in accordance with the type of display panel. By then along

When a plurality of data drivers are arranged in the Di direction, data drives of various configurations can be effectively arranged. In addition, Fig. 15 shows that the number of data drive configurations in the (1) direction is two, but the number of configurations may be four or more. Further, in Fig. 15, each of the data gram leaves drive DRa, and DRb includes 30 (Q) driver cells drci~drc3〇 arranged in parallel along the D2 direction. At this time, each of the driver cells DRC丨DRC3〇 receives the image data of the i pixel portion. Then, the d/a conversion of the image data of the i pixel portions is performed, and the data signals corresponding to the image data of the i pixel portions are rotated. Each drive 112460.doc -39- 1312570 actuator DRC 32 can include: data latch circuit, DAC of Figure 10 (A) (DAC of 1 pixel part) and output of Figure 10 (B) (C) SQ. Then, in FIG. 15, the number of pixels in the horizontal scanning direction of the panel is displayed (the letter of the horizontal scanning direction received by each integrated circuit device in the case where the data lines of the display panel are driven by the plurality of integrated circuit devices) Prime number) Set to HPN, set the number of blocks in the data drive block (number of block divisions) to DBN, and set the number of input of image data input by the driver cell during one horizontal scan to IN. Further, IN is equal to the number of readings RN of the image data during one horizontal scanning as explained in Fig. 14 . In this case, the number Q of driver cells DRC1 to DRC30 juxtaposed in the D2 direction can be expressed as Q = HPN / (DBNxIN). In the case of Fig. 15, since HPN=240, DBN=4, IN=2, it is Q=240/(4x2)=30. Further, when the width (pitch) of the driver cells DRC1 to DRC30 in the D2 direction is WD, and the width of the peripheral circuit portion (buffer circuit, wiring region, etc.) included in the data driver block in the D2 direction is WPCB, The width WB (maximum width) of the first to Nth circuit blocks CB1 to CBN in the D2 direction can be expressed as QxWDSWB<(Q+l)xWD + WPCB. Further, when the width of the peripheral circuit portion (the column address decoder RD, the wiring region, and the like) included in the memory block is WPC in the D2 direction, it can be expressed as QxWDSWB<(Q+l)xWD+WPC. In addition, the number of pixels of the display panel in the horizontal scanning direction is set to HPN, the number of bits of the image data of one pixel portion is set to PDB, and the number of blocks of the memory block is set to MBN (=DBN). During one horizontal scanning period, the number of readings of image data read from the memory block is set to RN. At this time, li2460.doc -40- 1312570 In the sense amplifier block SAB, the number P of the sense amplifiers (the sense amplifiers that output the image data of one bit portion) juxtaposed along the D2 direction can be expressed as P = (HPNxPDB)/(MBNxRN). In the case of Fig. 15, since HPN = 240, PDB = 18, MBN = 4, and RN = 2, therefore, P = (24 〇 x 18) / (4x2) = 540. In addition, the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of sense amplifiers that are not effective for a sense amplifier or the like for a virtual memory cell. In addition, when the width (pitch) of each sense amplifier included in the sense amplifier block SAB is set to WS in the D2 direction, the width WSAB of the sense amplifier block SAB (memory block) in the D2 direction can be expressed as WSAB. =PxWS. Then, the width WB (maximum width) of the circuit blocks CB1 to CBN in the D2 direction is also expressed as PxWSSWB<(P+PDB) when the width of the peripheral circuit portion included in the memory block is set to WPC in the D2 direction. )x WS+WPC. 5.4 Memory Cell Figure 16(A) shows an example of the structure of a memory cell (SRAM) included in a memory block. The memory cell comprises: transfer transistor TRA1, TRA2, load transistor TRA3, TRA4 and drive transistor TRA5, TRA6. When the word line WL is formed, the transfer transistors TRA1 and TRA2 are turned on, and the image data can be written to the nodes NA1 and NA2, and the image data can be read from the nodes NA1 and NA2. Further, the written image data is held at the node ΝΑΙ, NA2 by the positive and negative circuits formed by the transistors TRA3 to TRA6. Further, the memory cell of the present embodiment is not limited to the structure of FIG. 16(A), and may be modified to use a resistive element as the load transistor TRA3, TRA4, and other transistors such as 112460.doc -41 - 1312570 Implementation. Fig. 16 (B) (C) shows an example of the layout of memory cells. Fig. 16(B) is a layout example of a horizontal cell, and Fig. 16(C) is a layout example of a vertical cell. At this time, as shown in Fig. 16(B), the horizontal cell is a cell having a word line WL longer than the bit line BL and XBL in each memory cell. Further, as shown in Fig. 16(C), the vertical cells are cells which are longer in the bit line BL and XBL than the word line WL in each memory cell. Further, the WL of FIG. 16(C) is formed of a polysilicon layer and is connected to a local word line of the transfer transistors TRA1 and TRA2. However, a metal for preventing signal delay and potential stabilization of WL may be further provided. The character line of the layer. Fig. 17 shows an arrangement example of a memory block and a driver cell when the memory cell system uses the horizontal cell shown in Fig. 16(B). In addition, FIG. 17 shows in detail the one pixel portion corresponding to the driver cell and the memory block. As shown in Fig. 17, the driver cell DRC that receives the image data of one pixel portion includes data latch circuits DLATR, DLATG, DLATB for R (red), G (green), and B (blue). Each of the data latch circuits DLATR, DLATG, and DLAB latches the image data when the latch signal LAT (LATa, LATb) is active. Further, the driver cell DRC includes the RCR, DACG, and DACB for R, G, and B described in FIG. 10(A). Further, the output portion SQ explained in Fig. 10 (B) (C) is included. The portion of the sense amplifier block SAB corresponding to one pixel includes: sense amplifiers SAR0 to SAR5 for R, sense amplifiers SAG0 to SAG5 for G, and sense amplifiers SAB0-SAB5 for B. Then, on the D1 direction side of the sense amplifier SAR0, the bit line BL of the memory cell MC which is juxtaposed along the D1 direction, XBL is connected to S AR0. Further, on the D1 direction side of the sense amplifier 112460.doc - 42 · 1312570 SARI, the bit lines BL, XBL of the memory cells MC juxtaposed along the D1 direction are connected to SAR1. The relationship between other sense amplifiers and memory cells is also the same. When the word line WLla is selected, the memory cell MC of the gate of the transfer transistor is connected from WLla, the image data is read to the bit line BL, XBL, and the signals are sensed by the sense amplifiers SAR0 to SAR5, SAG0~SAG5, SAB0~SAB5. Zoom in action. Then, the DLATR latches the image data D0R to D5R from the 6-bit R of SAR0 to SAR5, the DACR performs the φ D/A conversion of the latched image data, and the output unit SQ outputs the data signal DATAR. In addition, the DLATG latches the image data D0G to D5G for the 6-bit G of the SAG0 to SAG5, the D/A conversion of the latched image data by the DACG, and the output signal SDATA of the output portion SQ. In addition, the DLATB latches the image data D0B to D5B from the 6-bit B of SAB0~SAB5, the DACB performs D/A conversion of the latched image data, and the output unit SQ outputs the data signal DATAB. Then, in the case of the configuration of Fig. 17, the reading of the image data during one horizontal scanning # shown in Fig. 14 can be realized as follows. That is, during the first horizontal scanning period (selection period of the first scanning line), the character line WLla' is first selected to perform the first reading of the image data, as shown in A5 of FIG. 14, and the first data is output. Signal DATAa. Next, the word line WLlb is selected during the same first horizontal scanning period, and the second reading of the image data is performed, as shown in A6 of Fig. 14, and the second data signal DATAb is output. In addition, during the second horizontal scanning period (the selection period of the second scanning line), the character line WL2a is first selected, and the 112460.doc-43 · 1312570 image data is extracted to output the first data signal DATAa. . Next, the word line WL2b is selected in the same second horizontal scanning period, the first reading of the image data is performed, and the second data signal DATAb is output. Thus, in the case of using the test cell, it is possible to select a different number of word lines (WLla, WLlb) in the memory block during the HiI horizontal scan. Several readings during the horizontal scan. Fig. 18 shows an arrangement example of the memory block and the driver cell when the memory cell system uses the vertical cell shown in Fig. 16 (c). The vertical cell can make the width in the 〇2 direction shorter than the transverse cell. Therefore, the number of memory cells in the 〇2 direction can be made twice as large as that of the horizontal cells. The vertical cells then use the row select signals c 〇 La, c 〇 Lb to switch the rows of memory cells connected to the respective sense amplifiers. As shown in Fig. 18, when the row selection signal C0La is active, the memory cell MC' on the side of the D1 direction of the sense amplifiers SAR0 to SAR5 is selected to be connected to the sense amplifiers SAR0 to SAR5. Then, the signal of the image data in the selected memory cell MC is enlarged and recorded, and D0R to D5R are output. Further, when the row selection signal C0Lb is active, the memory cells MC' on the Cb side are connected to the memory cells MC' on the D1 direction side of the sense amplifiers SAR0 to SAR5, and are connected to the sense amplifiers SAr〇 to SAR5. Then, the signal of the image data in the specially selected memory cell MC is reproduced, and the DOR~D5R is output. The reading of the image data of the memory cells connected to other sense amplifiers is also the same. Then, the reading of the image data during one horizontal scanning period shown in Fig. 14 in the case of the configuration of Fig. 18 can be realized as follows. That is, during the first horizontal scanning, the word line WL1 is first selected, so that the row selection signal U2460.doc - 44 - 1312570 C 〇 La is actively formed, as shown by A5, and the first time of the round-out room __ ordering image data Read the data signal DATAa as shown in Fig. U - Water & Secondly, during the same field, select the same character line WL1, and make the line selection as 主COL to form the main narration, history companion 15 'to perform the second reading of the image data' as shown in Fig. 14 ^ D, output The secondary data signal DATAb. In addition, during the second level scan, the word line WL2 is selected, so that the line selection 俨% C〇La forms the main stream % j j ^ ^ wind active, the first reading of the image data, the output first

People's bait material k number DATAa. Secondly, 'select the same word line WL2' during the same second horizontal sweeping period to make the row selection signal c〇Lb active, perform the second reading of the image data, and output the second data signal DATAb. In the case of a cell, by reading the same word line in the S-resonance block during one horizontal scanning period, several readings can be realized during one horizontal reading. Further, the configuration and arrangement of the driver cell DRC are not limited to those of Figs. 17 and 18 and can be implemented with various modifications. For example, as shown in Fig. 10(C), when a data signal for R, G, and B is multiplexed and transmitted to a display panel, a shared DAC can be used. 'D/A conversion of image data for R, G, and B (image data of 1 pixel portion). Therefore, in this case, the driver cell drc only needs to include one shared DAC of the configuration of Fig. 10(A). Further, in Figs. 17 and 18, the circuits for R (DLATR, DACR), the circuits for G (DLATG, DACG), and the circuits for B (DLATB, DACB) are arranged along the D2 (D4) direction. However, circuits for R, G, and B can also be arranged along the D1 (D3) direction. 112460.doc 45· 1312570 i: Thousands of Machines • W19(A) (Β) shows an example of a sub-machine (optoelectronic device) including the integrated circuit device 10 of the present embodiment. In addition, the electronic device may also include components other than those other than the figure (such as a camera, an operation unit, or a power source). Further, the electronic device of the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, or a portable information terminal. In the figure (4) (8), the host device 410 is an MPU (Microprocessor Unit), a baseband engine (baseband processor), or the like. The host device performs the control of the display == body circuit device 1〇. Alternatively, it can be handled as a type of engine and baseband material, or as a (four), elongation, and calibration engine. In addition, the image processing controller of FIG. 19(B), the graphics engine such as calibration, and the like (4) shrink and stretch panel 400 include: a plurality of data lines (source lines), a plurality of scan lines, and A specific number of pixels for the data line and the scan line. The second one is: the photoelectric element in each pixel area is changed by two (in the narrow sense, the liquid crystal element uses TFT to realize the display operation. The display panel can be used by the active matrix method of switching elements such as F/TFD. The panel and the display panel 400 can also be other than the active matrix method. The panel can be a panel other than the liquid crystal panel. Figure: A) The T' integrated circuit device 10 can use the built-in memory m. In this case, the integrated circuit device_shirt image data from the host device is temporarily written into the built-in memory, and the captured image data is read from the built-in memory read 112460.doc • 46, 1312570 to drive the display panel. . Further, in the case of Fig. 19(B), the integrated circuit device ίο can use a non-incorporated memory. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. Then, the integrated circuit device drives the display panel 4 under the control of the image processing controller 420. 7. Modification 7.1 Macroblocking In this embodiment, as shown in FIG. 20(A), the driver block db, the memory block MB, and the solder-plastic* block PDB may be subjected to macrocellization (macro-collection). , macro block lumping). In Fig. 20(A), the data driver block DB and the memory block MB are arranged along the D1 direction, and the pad block pdb is disposed on the D2 direction side of the data driver block DB and the δ memory block MB. At this time, a plurality of pads for electrically connecting the output line of the data driver block Ββ with the data line of the display panel are disposed in the solder bump block PDB. Specifically, the pad block PDB includes pad rows of two columns (in a broad sense, a series) which are alternately arranged in the D2 direction, and each pad row is arranged with pads (pad metal) in the direction of D1. In addition, the driver macro cell (driver macroblock) of Fig. 2(a) is a hard macro that is fixed for its wiring and circuit cell configuration. Specifically, wiring and circuit cell configuration are performed by a manual work layout. In addition, you can automate one of the wiring and configuration. In addition, it may be modified to implement other additional circuits between the data drive block DB and the memory block MB, or modified to be implemented in the drive macro cell without memory blocks. According to the method of FIG. 20(A), the output of the data driver can be successfully routed to the pad by the manual work layout 112460.doc -47 . 1312570, and the driver is used as the driver macro cell. . Therefore, compared with the method of wiring the data output by the automatic wiring tool, the wiring area of the output line can be reduced, so that a narrow elongated wafer can be realized. Further, the integrated circuit device of the layout shown in Fig. 5 (Α) (Β) can be realized by arranging the driver macro cells in parallel along the (1) direction, so that the circuit design and the layout work are made efficient. If the specification of the number of pixels of the display panel is changed, the number of the driver macro cells can be changed only by changing the configuration, and the output line of the data driver is not required to be re-routed, thereby improving the work efficiency. Further, in Fig. 2 (〇), in addition to the region on the D2 direction side of the data driver block DB, the region on the D2 direction side of the XX memory block MB can be effectively utilized as the pad arrangement region. Therefore, it is possible to configure the soldering of the soldering block pdb of the WPB WPB without waste, and to improve the layout efficiency. In addition, in FIG. 20(A) and (B), when the widths of the data driver block db, the memory block MB, and the pad block PDB in the D1 direction are respectively WDB, WMB, and WPB, WDB can also be used. The relationship between +WMB g wpB was established. That is, in FIG. 20(A), the width WPB of the pad block pdb in the D1 direction is substantially equal to the sum of the width WDB of the data driver block DB and the visibility WMB of the memory block mb, such as WDB + WMB = WPB. Further, in Fig. 20(B), a repeater block rP of an additional circuit is arranged. The transponder block RP includes a circuit block for buffering at least a memory data signal (or an address signal, a memory control signal) to the memory block MB and a buffer for the memory block MB. Then, in the case of FIG. 20(B), when WDB + WMB <WPB 〇 112460.doc -48 - 1312570 WDB+WMB=WPB is established, when a plurality of driver macro cells are arranged in parallel in the D1 direction, phase No excess vacant area is created between the adjacent pad pads, and several pad blocks can be juxtaposed along the D1 direction. Therefore, the knowledge of the data drive is also arranged in the D1 direction without waste, and the width of the integrated circuit device in the D1 direction can be reduced. In addition, when the relationship of WDB + WMB < WPB is established, the repeater block RP of the additional circuit shown in Fig. 2 (B) can be configured, and the layout efficiency can be improved. That is, when the width WpB of the pad block PDB becomes larger due to the limitation of the pad pitch, and the vacant area is generated next to the memory block MB or the data driver block DB, additionality can be configured in the vacant area. Circuit. Further, the additional circuit disposed in the vacant area is not limited to the repeater block Rp. For example, a part of the gray scale voltage generating circuit may be configured, or the output line of the data driver may be set to a circuit of a specified potential or an additional circuit of an electrostatic protection circuit, etc. In addition, the repeater block Rp of the additional circuit block is called. The width of the direction is set to WAB, and the number of pads of the pad block pDB is set to 1^1>. Thus, the relationship of (NP-l)xPP<WDB+WMB+WAB<(Np+1)xpp is established. When such a relationship is established, when a plurality of driver macro cells are arranged side by side in the D1 direction, no excess vacant area is generated, and a plurality of pad blocks are juxtaposed in the D1 direction, and uniform pad pitches can be arranged along the m direction. Solder pad. Then, when the pads are arranged at a uniform pad pitch, when the integrated circuit device is mounted on the glass substrate by bumps or the like, stress is uniformly applied to the pad arrangement region, thereby preventing contact failure. In addition, when a vacant area is generated between the pads, the vacant area may cause the flow of the anisotropic conductive material of the ACF or the like to change the flow of the material 112460.doc -49 - 1312570, and the joint failure occurs, etc. π W / Λ*, however, this can be prevented by arranging the mats at a uniform pad spacing. Furthermore, the relationship of WDB + WMB + WABSNPxPP can also be established. In this way, the pitch of the pads in the D1 direction can be made more uniform, and the stress can be more uniform. In addition, in the case of an additional circuit in which the repeater block RP is not configured, it may be WAB=0. In addition, a dummy pad other than the pad for the data driver can be disposed in the soldering pad pDB (the bump or the bonding pad is not connected), and the pad and dummy of the data driver can also be used. The sum of the number of pads is used as the number of pads NP. 7 · 2 repeater block Figure 21 shows an example of the construction of a repeater block. The repeater block can be configured as if it can be adjacent to each of its own body blocks (jth memory block). As shown in FIG. 5(b), the memory for transmitting the data signal from the logic circuit block LB, the address signal, and the memory for the k-number are globally and lined, and are routed to the circuit along the direction D1. On the block, these signals are supplied from the logic circuit block 1^ to the respective memory blocks MB1~MB4°. At this time, when the signals are not buffered, the rising or falling waveform of the signal is sluggish, and the memory area is The time during which the block writes data is extended, and a write error may occur. In this case, if the repeater block of FIG. 21 is arranged adjacent to the side of the memory block such as the d 1 direction side, the address information can be written by the repeater block buffer. The signal and memory control signals are input to each memory block. Therefore, the delay of the rising or falling waveform of the signal can be reduced, and the data can be correctly written to the memory block. In Fig. 21, the write data signal from the logic circuit block Lb (WD0, U2460.doc -50. 1312570 WD1···) is buffered by the buffers BFA1, BFA2, which are composed of two inverters, and output. The repeater block to the next order. Specifically, in FIG. 5(B), the transponder block disposed on the D1 direction side of the memory block MB4 is placed on the D-direction side of the s-resonant block MB3. The transponder block outputs the buffered signal. Further, the write data signal from the logic circuit block LB is buffered by the buffers BFB1, BFB2, ... and output to the memory block. Specifically, in FIG. 5 (8), the transponder block disposed on the D1 direction side of the memory block MB4 outputs the buffered signal to the memory block mb4, so that the information is written. The signal is provided with buffers BFB1, BFB2, ... for each memory block in addition to the output buffers BFA1, BFA2, ... for the next-order memory block. Therefore, the parasitic capacitance of the memory cell due to the memory block can be effectively prevented, and the waveform of the write data signal is sluggish, and the write time is long-term or the write error occurs. In addition, the address signal ((:]?1; row address, CPU column address, LCD column address, etc.) from the logic circuit block is buffered by the buffer BFC1, and output to the memory block and The second-order transponder block. In addition, the memory control signals (read/write switching signals, CPU assignments, memory selection signals, etc.) from the _31 circuit block LB are used by the buffer BFD1... After being buffered, it is output to the memory block and the second-order transponder block. In addition, in the transponder block of Figure 2, there is also a buffer for extracting the material from the memory block. Specifically, the memory selection signal BANKM forms an active (H level), and selects its memory block (the first to the first memory block in the memory block) from its memory. The read data signal of the body block (the Jth memory block) is buffered and output to the read by the buffer BFE1, BFE2.. buffer corresponding to the repeater block of the memory block 112460.doc 51 1312570. Take the shell line RDOL, RD1L.... In addition, the bank selection signal BANKMb becomes inactive (L level), When the memory block (the first memory block) is formed in a non-selection state, the output states of the buffers BFE1, BFE2, . . . corresponding to the repeater block of the memory block are set to a high impedance state. The read data signal from the other memory block in which the memory select signal is actively formed can be correctly output to the logic circuit block LB. In addition, in the present embodiment, when access is from the host side, the selection corresponds to access. The memory block of the area 'selects only the character line machine of its memory block. Thereby, the read data field self-selected memory block is output to the read data line RDOL, RD1L via the repeater block. 7.3. Sub-pixel driver cell configuration / 22 display sub-pixel driver cell configuration example. In Figure 22, the data driver block contains image data whose respective outputs correspond to one sub-pixel portion.

The driver cell dr of the data driver DRa of Fig. 15 is constituted by sub-pixel driver cells SDC1, SDC2, SDC3. This SDC2 and SDC3 are composed of R (red) and G (green) by SDC2 and SDC3, respectively. At the time of Figure 22, SDC1, B (blue) sub-pixel 112460.doc • 52- 1312570 driver cell, corresponding to the first data signal R, G, B image data (Rl, Gl, B1 ) Input from the memory block. Then, the sub-pixel driver cells SDC1, SDC2, and SDC3 perform d/a conversion of the image data (R1, (1), Bl), and rotate the data signals (data voltages) of the first R, G, and B to correspond to Pads for R, G, and B on the first data line. Similarly, the driver cell DRC2 is composed of sub-pixel driver cells SDC4, SDC5, and SDC6 for R, G, and b, and corresponds to the image data of R, G, and B of the second data reed (R2, G2, B2). ) Input from the memory block. • Then the 'sub-pixel driver cells SDC4, SDC5, SDC6 perform D/A conversion of these image data (R2, G2, B2), and output the second R, G, B data signals (data voltage) to correspond to The solder pads for R, G, and B of the second data line. The other sub-pixel driver cells are also the same. Further, the number of sub-pixels is not limited to three, and may be four or more. Further, the arrangement of the sub-pixel driver cells is not limited to Fig. 22, and the sub-pixel driver cells for R, G, and b may be stacked and arranged in the D2 direction. 7.4 Configuration of Sense Amplifier and Memory Cell • Figure 23 shows an example of the configuration of a sense amplifier and a memory cell. The portion of the sense amplifier block corresponding to one pixel includes: sense amplifiers for R, SAR0 to SAR5, sense amplifiers SAG0 to SAG5 for G, and sense amplifiers SAB0 to SAB5 for use. In addition, in FIG. 23, two (generally a plurality of) sense amplifiers (and buffers) are stacked and arranged in the D1 direction, and then D1 of the first and second sense amplifiers S ARO, S AR1 in the stacked configuration. On the direction side, in the memory cell row (longitudinal cell) of two columns juxtaposed along the direction D1, the bit line of the upper side column of the cell line is connected to the first sense amplifier SAR0, the lower 112460.doc - 53- 1312570 The bit line of the memory cell in the side column is connected to the second sensing SAR1. Then, the _th and second sense amplifiers sar〇, SAR1 perform signal amplification of the image data read from the memory cell, whereby the 2-bit image data can be output from the SARI. The relationship between other sense amplifiers and memory cells is also the same.

In the case of Fig. 23, the reading of image data during one horizontal scanning period can be realized as follows. That is, during the first horizontal scanning period (selection period of the first scanning line), the word line WL1a is first selected, and the first reading of the image data is performed to output the first data signal DATAa. In this case, the image data from the sense amplifiers SAR0 to SAR5, SAG0 to SAG5, SABO to SAB5, R, 〇, b are input to the sub-pixel driver cells SDC1, SDC2, and SDC3, respectively. Secondly, during the same __ horizontal scanning period, the word line WL lb is selected, the second reading of the image data is performed, and the second data signal DATAb is output. In this case, the sensing amplifiers SAR0 to SAR5 are obtained. The image data of R, g, and B of SAG0~SAG5, SAB0~SAB5 are input to the sub-pixel driver cells SDC91, SDC92, and sdc93, respectively. 7_5 rearrangement wiring area. In this embodiment, rearrangement wiring for the arrangement order of the output lines of the rearranged sub-pixel driver cells (driver cells) can be arranged in the arrangement area of the sub-pixel driver cells (driver cells) (4) . For example, &, because the switching of the cloth (4) can be minimized, the width of the wiring area between the data driver block and the a solder pad can be reduced in the D2 direction, and a narrow slender can be realized. As shown in Figure 24, El, E2, the output signal of the sub-pixel driver cell (data H2460.doc • 54-1312570 L) is taken along the D2 direction (longitudinal direction). These take-up lines are taken from the lean-out driver block to take out the line for the round-out signal of the sub-pixel driver cells, as formed by the fourth layer of aluminum wiring layer ALD. Further, in the figure, the output lines connecting the sub-pixel driver cells and the pads P1' P2, P3·.. for the data lines of the display panel are disposed on the D2 direction side of the data driver block and the memory block. Then, the rearrangement wiring area (first and second rearrangement wiring areas) for rearranging the order of the take-out lines in Fig. 24 is provided in the arrangement area of the sub-pixel driver cells. Specifically, the rearranged wiring region is formed in a region above the first and second aluminum wiring layers ALA and ALB of the local line in the sub-pixel drive cell. Then, the rearranged wiring area is rearranged in the order in which the strips are arranged in the order in which the pads are arranged. In this case, the order of the pads may be arranged in the order in which the pads are arranged, or the order in which the pads are arranged may be changed by a predetermined rule. Further, the rearranged wiring area is a wiring area formed by the take-out line indicated by E1, E2 or the take-out line position changing line of E6 to E9 which will be described later. As shown in FIG. 24, the sub-pixel driver cells sdci, SDC2, SDC4, SDC5, SDC7, SDC8, . . . belong to the first group whose cell number is not a multiple of 3 (in a broad sense, a multiple of j 'J is an integer of 2 or more). The sub-pixel driver cells SDC3, SDC6, SDC9.. which are multiples of 3 are belonging to the second group. Then, the fetch line of the first group shown by 'E1' belongs to the output line of the output signals of the sub-pixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8, ... of the first group. The take-out lines of the first group shown by E1 are rearranged in the first rearranged wiring area. Specifically, in the first rearranged wiring area 112460.doc - 55 - 1312570 domain, the order of the take-out lines is rearranged in the order of ..., the pads P1, P2, p4, P5, P7, P8.. That is, the order of arrangement of the removal lines is rearranged by removing the pad arrangement order of the pads whose number of pads is a multiple of three. Thereby, in the D2 direction side boundary of the data driver block (removing 埠), the order lines of the output lines of the sub-pixel driver cells can be rearranged in the order of SDC1, SDC2, SDC4' SDC5, SDC7, SDC8... . In addition, the fetch line of the second group shown by E2 belongs to the take-out line of the output signal of the sub-pixel driving benefit cells SDC3, SDC6, SDC9.. The fetch line of the second group shown in E2 is rearranged in the second rearrangement wiring (four). Specifically, in the second rearranged wiring area, the order of the take-out lines is rearranged in the order of Tan 塾", P6, P9.., that is, the number of the solder 塾 is a multiple of 3 In the order of arrangement, the arrangement order of the rearrangement lines is such that the output of the sub-pixel driver cells can be rearranged in the order of SDC3, SDC6, SDC9... in the D2 direction side boundary (removing bee) of the negative material driver block. Lines are taken out of the line. In this way, when the rearranged wiring area is set in the sub-pixel driver and the order of the rearrangement lines is rearranged, the wiring area between the pad and the f-driver block can be shown as E3. The wiring layer switching in the area is suppressed to a minimum. Therefore, the width of the wiring area indicated by E3 can be reduced, and a narrow elongated wafer can be realized. In addition, in the wiring area of the clear display, the connection m The first group of taken-out wires and pads PI, P2 P4 PS p7 D are shown. ' Π P5, P7, P8.·. Use the connecting wire, if not in the third layer of the wiring layer ALC (In a broad sense, the line of the layer is given.) The cloth 4 is connected to the second group of the wire and the pad M of the second group. , p6, 112460.doc -56- 1312570 P9···Connected wire, as shown in E5, in the fourth layer of aluminum wiring layer ALD (broadly speaking, the layer of the layer different from the layer given) The wiring shown in FIG. 4 is connected to the line from the sub-pixel driver cell SDC 10 and the pad 10. The connection line shown in FIG. 5 is connected to the take-out wire and pad from the sub-pixel driver cell SDC9. Ρ9. At this time, the connection line of Ε4 is formed by the aluminum wiring layer ALC, and the connection line of Ε5 is formed by the aluminum wiring layer ALD of a layer different from ACL. Therefore, switching of the wiring layer is not required, Ε3 In the wiring area, the connection line of the crucible 4 and the connection line of the crucible 5 can be overlapped. Therefore, the width WIT of the wiring area of the crucible 3 in the D2 direction can be further reduced, and a narrow elongated wafer can be realized. In the embodiment of the present invention, the extraction position change line for extracting the take-out position indicated by El and E2 in Fig. 24 is wired in the rearrangement wiring region. The QCL1 and QCL2 are modified as shown in E6 to change the sub-pixel driver cell SDC1. , the output position of the output signal (output line) of SDC2 is used to take out the bit. Similarly, QCL4, QCL5, SDC4, SDC5 take-out position change line, E8, QCL7, QCL8, SDC7, SDC8 take-out position change line, E9, QCL10, QCL11, SDC10 The position change line of the SDC 11 is taken out. At this time, as shown by E6, the position change line QCL1 and QCL2 are taken across a plurality of sub-pixel driver cells sdCI and SDC2 arranged along the D1 direction, and the wiring is in the D1 direction (lateral direction). That is, the two sub-pixel driver cells SDC1, SDC2 arranged along the d1 direction are crossed, and the wiring lines 2 take out the position change lines QCL1, QCL2. Thereby, the output signals of the sub-pixel driver cells SDC1, SDC2 can be taken out from any position along the direction of 112460.doc - 57 - 1312570 D1 of the first rearrangement wiring region using the take-out line. That is, the take-out position changing line QCLi, qcl2 is routed in the aluminum wiring layer ALC of the third layer. Therefore, when a path of ALC and ALD is formed at any position of the extraction position changing lines QCL1 and QCL2 which are routed along the 〇1 direction, the wiring can be formed in the D2 direction from the position where the path is formed. The take-up line formed by ALD. Thereby, it is easy to arrange the arrangement order of the wire take-out line in the D2 direction from the arbitrary take-out position in the direction D1.

Fig. 25(A) shows an example of the use form of each aluminum wiring layer. For example, the first aluminum wiring layer ALA wired in the vertical or horizontal direction is used as the source/drain/gate connection line of the electric crystal of the circuit block. Further, a second aluminum wiring layer ALB mainly wired in the vertical direction is used as a power supply line, a signal line, a gray-scale electric supply line, or the like. Further, the third inscribed layer layer ALC mainly used in the horizontal direction is used as the take-out position change line of the data drive or the image data supply line of the memory. Further, a fourth aluminum wiring layer ALD mainly wired in the longitudinal direction is used as a data extraction line or a gray scale voltage supply line of the data driver. Further, a fifth aluminum wiring layer ALE which is mainly used for wiring the top metal in the lateral direction is used as a global line between the non-adjacent circuit blocks of the wiring. An example of the layout of the wiring layer ALC wired in the sub-pixel driver cell is shown in Fig. 25(B). In Fig. 25(B), the take-out position changing line and the dac driving line are wired in the D1 direction (horizontal direction) on the aluminum wiring layer ALC having a large width. Further, 18 image data supply lines such as one pixel portion are routed along the D1 direction on the aluminum wiring layer ALC. Thus, in the sub-pixel driver, many image data supply lines and the take-out position shown in Fig. 24 and the like are changed.

Ii2460.doc •58- 1312570 The wires are routed on the same layer of aluminum wiring layer alc. Further, in the present embodiment, the gray scale voltage supply line for supplying the gray scale voltage to the D/A converter DAC of the sub-pixel driver cell is wired in the D2 direction across a plurality of sub-pixel drive cells. Specifically, the gray scale voltage supply line is routed by effectively using the vacant area in which the take-out line is not disposed by the aluminum wiring layer ALD of the same layer as the take-out line. As described above, in the present embodiment, the take-out position changing line and the image data supply line in the D1 (horizontal) direction are wired on the aluminum wiring layer ALC. Further, the take-out line and the gray-scale voltage supply line along the D2 (longitudinal) direction are wired on the aluminum wiring layer ALD of a layer different from the aLC. Thereby, the two-layer aluminum wiring layers ALC and ALD can be used to effectively extract the position change line, the image data supply line, the take-out line, and the gray-scale voltage supply line. Therefore, it is possible to use the ALE for the global line or the like without using the Ilu wiring layer of other layers such as ale, thereby improving the wiring efficiency and realizing a narrow elongated wafer. Further, in the present embodiment, a rearrangement wiring region is provided in a region of the output portion SSq of the sub-pixel driver cell. As shown in FIG. 24, the first rearrangement wiring region is provided in the sub-pixel driver cells SDC1, SDC2 of the first group. The area of the output portion SSQ of SDC4, SDC5, SDC7, SDC8·'. Further, the second rearranged wiring area is provided in the area of the output portion SSQ of the sub-pixel driver cells SDC3, SDC6, SDC9, ... of the second group. Thereby, the area of the output portion S S Q of the sub-pixel driver cell can be effectively utilized to realize the rearrangement of the arrangement order of the fetch lines. That is, as shown in El, E2 of FIG. 24, when the line is taken out in the area of the output portion SSQ, and the area of the SSQ is set in the rearranged wiring area, the gray scale of the DAC area on both sides of the SSq can be arranged. Voltage supply line. Therefore, the wire extraction line and the gray scale voltage supply line can be routed on the same layer of aluminum 112460.doc .59· 1312570 wiring layer ALD, which can improve the wiring efficiency. Layout of 7·7 Sub-Pixel Driver Cell Figure 26 shows a detailed layout example of the sub-pixel driver cell. As shown in Fig. 26, each of the sub-pixel driver cells SDC1 to SDC180 includes a flash lock circuit LAT, a level shifter L/S, a D/A converter DAC, and an output portion SSQ. Further, other block circuits such as an FRC (frame rate control) circuit for gray scale control may be provided between the flash lock circuit LAT and the level shifter L/S. Each sub-pixel driver cell includes a latch circuit LAT that latches 6-bit image data from a sub-pixel cell portion of the memory block MB1. The level shifter L/S converts the voltage level of the 6-bit image data signal from the latch circuit LAT. The D/A converter DAC uses a gray scale voltage for D/A conversion of 6-bit image data. The output portion SSq includes an operational amplifier 〇p (connected voltage transponder) that performs impedance conversion of the output signal of the D/A converter DAC, and drives a data line corresponding to one sub-pixel cell. Further, the output unit ssq may include a transistor (switching element) for discharging, 8-color display, and DAC driving in addition to the operational amplifier OP. Then, as shown in FIG. 26, each of the sub-pixel driver cells (the first and second data drivers DRa, DRb) includes: a voltage level (in a broad sense, a first voltage level) configured with LV (low voltage) a circuit 2Lv region of a power supply operation (in a broad sense, a first circuit region); and a circuit for configuring a power supply operation of a voltage level of Mv (intermediate voltage) higher than Lv (in a broad sense, a second voltage level) The MV area (in the broadest sense, the second circuit area). At this time, the operation logic of the logic circuit block LB, the memory block, and the like is performed. In addition, 112460.doc -60· 1312570 MV is an operating voltage such as a D/A converter, an operational amplifier, and a power supply circuit. In addition, the output transistor of the scan driver supplies a voltage source of &HV (high voltage) (in the broadest sense, the third voltage level) to drive the scan line. The latch circuit LAT (or other block circuit) is disposed in the Lv region (first circuit region) of the sub-pixel driver cell. Further, an output portion SSQ including a D/A converter DAC or an operational amplifier 〇p is disposed in the MV area (second circuit area). Then, the signal of the voltage level of the level shifter is converted into a signal of the voltage level of the MV. Further, in Fig. 26, a buffer circuit BF1 is blown on the side of the sub-pixel driver cells SDC1 to SDC18?2D4. The buffer circuit BF 缓冲 buffers the driver control signal from the logic circuit block LB and outputs it to the sub-pixel drive cells SDC1 to SDC180. In other words, it functions as a repeater block of the drive control signal. Specifically, the buffer circuit BF1 includes a [乂 buffer" disposed in the LV area and an MV buffer disposed in the MV area. Then, the 1^¥ buffer receives the driver control signal (latch signal, etc.) from the voltage level of the LV of the logic circuit block LB, and buffers the LV area of the sub-pixel driver cell disposed on the D2 direction side thereof. The circuit (LAT) turns out. In addition, the Mv buffer receives the driver control signal (DAC control signal, output control signal, etc.) from the voltage level of the LV of the logic circuit block LB, and is buffered by the level shifter into a voltage level of the MV to be buffered. Then, the circuit (DAC, SSq) of the MV area of the sub-pixel driver cell disposed on the direction side thereof is output. Then, in the present embodiment, as shown in Fig. 26, 112460.doc • 61 · 1312570 sub-pixel driver cells SDC1 are arranged such that each MV region (or each LV region) of each sub-pixel driver cell is adjacent to the 01 direction. SDC180. That is, the adjacent sub-pixel drive cells sandwich the adjacent boundary along the D2 direction and the mirror arrangement is arranged such that the sub-pixel driver cells SDC1 and SDC2 are adjacent to each other with the MV area. In addition, the sub-pixel driver cells SDC3 and SDC91 are also arranged adjacent to each other in the MV area. Also. The sub-pixel driver cells SDC2 and SDC3 are arranged adjacent to each LV region. As shown in Fig. 26, when the MV areas are arranged adjacent to each other, it is not necessary to provide a guard ring or the like between the sub-pixel driver cells. Therefore, the width of the data driver block in the D1 direction can be made smaller than the method of adjoining the MV area and the Lv area, thereby reducing the area of the integrated circuit device. Further, by the arrangement method of Fig. 26, the MV area of the adjacent sub-pixel driver cell can be effectively utilized as the wiring area of the output line of the output signal of the sub-pixel driver cell, and the layout efficiency can be improved.

Further, as shown in Figs. 22 and 26, in the present embodiment, the first and second data drivers DRa, DRb are arranged such that their respective MV regions (second circuit regions) are adjacent to each other. In addition, the LV area (first circuit area) of the first data driver DRa is adjacent to the first memory block MB 1 (the Jth memory block) LV area of the second data driver DRb (the first circuit area) The configuration is adjacent to the first memory block MB 2 (the memory block of J+1). As shown in Figs. 22 and 26, the first memory block MB1 is disposed adjacent to the LV area of the sub-pixel driver cells SDCl, SDC4, SDC7, ..., SDC88 of the first data driver DRa. Further, the second memory block MB2 is disposed adjacent to the LV area of the sub-pixel driver cells SDC93, SDC96, SDC99"_SDC180 of the second data driver DRb. Then, the memory block 112460.doc -62 - 1312570 MBi, MB2 operates at the voltage level of the LV. Therefore, when the LV area of the sub-pixel driver cell is arranged adjacent to the memory block, the width of the driver macro cell formed by the data driver block and the memory block in the D1 direction can be reduced to obtain the product. The area of the bulk circuit device is small. 7·8 D/A converter Fig. 27 shows a detailed configuration example of a D/A converter (DAC) included in the sub-pixel driver cell. The D/A converter is a circuit for performing d/a conversion in a so-called T〇umament mode, and includes: gray scale voltage selectors slni to slnU, SLP1 to SLP11, and a predecoder 12A. At this time, the gray scale voltage selector SLN is a selector composed of a transistor (in a broad sense, a conductivity type), and the gray scale voltage selectors SLP1 to SLP11 are p-type (in a broad sense, the second conductive The transistor of the type) is formed as a selector, and the N-type and p-type transistors are paired to form a transfer gate. The N-type transistor constituting SLN1 is paired with the p-type transistor constituting slpi to constitute a transfer gate. On the input terminals of the gray scale voltage selectors SLN1 to SLN8 and SLP1 to SLP8, 'connect V0 to V3, V4 to V7, V8 to V11, V12 to V15, V16 to V19, V20 to V23, V24 to V27, V28 to Gray-scale voltage supply line for V31. Then, the pre-decoder 12 inputs the video data D0 to D5, and performs decoding processing as shown in the truth table shown in Fig. 28(A). Then, the selection signals S1 to S4 and XS1 to XS4 are output to the gray scale voltage selectors SLN1 to SLN8, SLP1 to SLP9, respectively. Further, selection signals S5 to S8, XS5 to XS8 are output to SLN9 and SLN10, SLP9 and SLP10, respectively, and S9 to S12, XS9 to XS12 are output to SLN11 and SLP11, respectively. 112460.doc -63 · 1312570 In the case of image data D0 to D5 (100000), as shown in the truth table of Fig. 28(A), the selection signals S2, S5, S9 (XS2, XS5, XS9) form the initiative. Thereby, the gray scale voltage selectors SLN1, SLP1 select the gray scale voltage VI, SLN9, SLP9 select SLN1, the output of SLP1, SLN11, SLP11 select the output of SLN9, SLP9. Therefore, the gray scale voltage VI is output to the output portion SSQ. Similarly, in the case of the image data D0 to D5 (〇1 〇〇〇〇), the selection signal S3 (XS3) forms the initiative. Therefore, the gray scale voltage selectors SLN1, SLP1 select the gray scale voltage V2' to output the gray scale voltage V2 to the output portion SSQ. • In addition, when the image data D0-D5 is (001〇〇〇), the selection signals si, S6, S9 (XS1, XS6, XS9) form the initiative. Therefore, the gray scale voltage selector SLN2, SLP2 selects the gray scale voltages V4, SLN9, SLP9 selects the output of SLN2 SLP2 'SLN11, and SLP11 selects the output of SLN9, SLP9. Therefore, the gray scale voltage V4 is output to the output portion SSQ. Then, in the present embodiment, as shown in FIG. 28(B) and (C), the gray-scale voltage supply line for the gray-scale voltages V0 to V31 is supplied to the 〇/eight converter of FIG. 27 across a plurality of sub-pixel driver cells. Route along the D2 (D4) direction. In Fig. 28(b), the gray scale voltage supply line straddles the subpixel driver cells SDC1, SDC4' SDC7 which are arranged in the D2 direction, and is wired in the (1) direction. In addition: these gray-scale voltage supply lines are as shown in Figure 28(B) (Muse-^, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, As shown in Fig. 28(B), in your sub-pixel driver cell, the configuration area of the eight converters is matched along the D2 direction. & rj configuration · N-type transistor region (卩-well) And the P-type transistor region (N-well). In addition, the circuit other than the D/A converter of the sub-pixel driver cell (output section, 1 vertical + shifter, flash lock power 112460.doc -64- The arrangement area of 1312570) is arranged along the D1 direction orthogonal to the D2 direction: an N-type transistor region (P-type well) and a P-type transistor region (N-type well). In other words, adjacent to the D2 direction The pixel driver cell is arranged with a mirror adjacent to the boundary adjacent to the D1 direction. If the driver cells SDC1 and SDC4 sandwich the adjacent boundary and the mirror is disposed, the SDC4 and the SDC7 sandwich the adjacent boundary and the mirror is arranged. N-type transistor of the gray-scale voltage selector SLN1 to SLN11 of the D/A converter of the sub-pixel driver cell SDC1, forming The N-type transistor region NTR1 of the sub-pixel driver cell shown in Fig. 28(B), the P-type transistor constituting the gray-scale voltage selectors SLP1 to SLP11 is formed in the P-type transistor region PTR1. Specifically, as shown in Fig. 28(C) The N-type transistors TRF1, TRF2 constituting the gray-scale voltage selector SLN11, and the N-type transistors TRF3 and TRF4 constituting the gray-scale voltage selectors SLN9, SLN10 are formed in the N-type transistor region NTR1. P-type transistor TRF5, TRF6 of gray scale voltage selector SLP11, and P-type transistor TRF7, TRF8 constituting gray scale voltage selector SLP9, SLP10 are formed in P-type transistor region PTR1. Then, sub-pixel driver cell other The N-type transistor region and the P-type transistor region of the circuit are arranged along the D1 direction, and the N-type transistor region NTR1 and the P-type transistor region PTR1 are arranged along the D2 direction. The D/A converter of Fig. 27, The N-type transistor constituting the gray scale voltage selector SLN1 and the P-type transistor constituting the gray scale voltage selector SLP1 form a transfer gate in pairs. Therefore, when wiring the gray scale voltage supply line along the D2 direction, it is possible to These P-type and N-type transistors are connected to the gray scale voltage. Lines can easily form a transfer gate and improve layout efficiency. 112460.doc -65 - 1312570 In addition, for circuits other than D/A converters, such as the θ-lock circuit, you need to input images from the memory block. Then, as shown in Fig. 28 (Β), the image data is supplied by the image (4) supply line routed in the direction of the buckle. Further, from the layout (4) of Fig. 26, in the sub-pixel driver The signal flow direction is in the direction of D1. Therefore, as shown in Fig. 28(Β), when the N-type transistor region and the p-type transistor region of the circuit other than the D/A converter are arranged side by side in the direction of (1), it can be effectively arranged along the flow direction of the signal. Therefore, the arrangement of the transistor regions of Fig. 28(B) forms an optimum layout in the sub-pixel driver cells of the % configuration. The present invention has been described in detail with reference to the preferred embodiments of the present invention, and it is understood that many modifications may be made without departing from the spirit and scope of the invention. Therefore, the modifications are all included in the scope of the invention. In the specification or the drawings, at least one time is used together with the terms of the broader or synonymous (first interface area, second interface area, etc.) (output side i/f area, input side I/F area, etc.) ), anywhere in the specification or schema, can be replaced with its different terms. Further, the structure, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in the embodiment, and various modifications can be made. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (A), (B) and (C) are explanatory views of a comparative example of the present embodiment. 2(A) and (B) are explanatory views of the mounting of the integrated circuit device. Fig. 3 is a view showing an example of the structure of the integrated circuit device of the embodiment. Figure 4 shows an example of various types of display drivers and their built-in circuit blocks. 112460.doc - 66- 1312570 Fig. 5 (A) and (B) are diagrams showing an example of a planar layout of the integrated circuit device of the present embodiment. Fig. 6(A) and (B) are diagrams showing an example of a sectional view of a system circuit device. Fig. 7 is a circuit configuration example of an integrated circuit device. Fig. 8(A)(B)(C) shows a configuration example of a data driver and a scan driver. 9(A) and (B) show examples of the configuration of a power supply circuit and a gray scale voltage generating circuit. Fig. 10 (A) (B) (C) shows a configuration example of a D/A converter and an output circuit. 11(A) and (B) are explanatory diagrams of a method of arranging adjacent memory blocks and data driver blocks. Fig. 12 (A) and (B) are explanatory views of a comparative example. Figure 13 (A) (B) is an explanatory diagram of the arrangement of the memory block and the data drive block. Fig. 14 is an explanatory diagram showing a method of reading image data several times during one horizontal scanning. Fig. 1 is a configuration example of a data driver and a driver cell. Fig. 16 (A) (B) (C) is a structural example of a memory cell. Fig. 17 is a diagram showing an arrangement example of a memory block and a driver cell in a horizontal cell type. Fig. 18 is a diagram showing an arrangement example of a memory block and a driver cell in a vertical cell state. 19(A) and (B) show examples of the structure of an electronic device. Fig. 20 (A) (B) is an explanatory diagram of a macrophageization method. Fig. 2 is a structural example of a repeater block. Fig. 22 shows an example of the arrangement of the sub-pixel driver cells. Fig. 23 is a configuration example of a sense amplifier and a memory cell. Fig. 24 is an explanatory view showing a wiring pad wiring method. 112460.doc •67· 1312570 Fig. 25(A)(B) is an explanatory view showing the use form and the like of the aluminum wiring layer. Fig. 26 is a configuration example of a sub-pixel driver cell. Fig. 27 is a configuration example of a D/A converter.

Fig. 28(4)(B) (C) is an explanatory diagram of the layout of the converter of the D/A converter. ., the truth table of the stolen and D / A [main component symbol description]

10 Integrated circuit device 12 Output side I/F area 14 Input side I/F area 20 Memory 22 Memory cell array 24 column address decoder 26 Row address decoder 28 Write/read circuit 40 Logic circuit 42 Control Circuit 44 Display Time Control Circuit 46. Host Interface Circuit 48 RGB Interface Circuit 50 Data Driver 52 Data Latch Circuit 54 D/A Conversion Circuit 56 Output Circuit 70 Scan Driver 112460.doc -68- 1312570 72 Shift Register 73 Scan Address generation circuit 74 Address decoder 76 Level shifter 78 Output circuit 90 Power supply circuit 92 Boost circuit 94 Regulator circuit 96 VCOM generation circuit 98 Control circuit 110 Gray scale voltage generation circuit 112 Selection voltage generation circuit 114 Gray scale voltage selection circuit 116 adjusts the registers CB1 C CBN first to Nth circuit blocks 112460.doc -69-

Claims (1)

1312570 X. The scope of application for patents·· 1.- The integrated circuit circuit is set up, and its special, Hui-Zhedian is in the direction of the third side of the opposite side of the self-integrated circuit. The direction 'sets the second side of the long side of the integrated circuit device to the direction of the opposite fourth side. From: the second direction 'includes the first along the first direction - ~: is the circuit block (Ν For an integer greater than 2), the first:, the first to the third circuit blocks include: At least the image data of the words! The memory block, and the == at least one data driver block for the active data line, wherein the memory block is adjacent to the data driving direction. Pure..." Description 2. As requested! The integrated circuit device, wherein the first to the first blocks include: & £ first to first memory blocks (1 is an integer of 2 or more); and for each of the first to the first memory blocks, The first to third data driver blocks are disposed adjacent to each other along the aforementioned first direction. 3. The integrated circuit device of claim 2, wherein when the opposite direction of the first direction is the third direction, the Jth memory block in the first to the first memory block < a third data direction block in the first to first data driver blocks adjacent to the third direction side of the [[], and adjacent to the first-direction side of the J-th memory block. The first J+1 memory block in the first to the first memory block, in the first direction side of the J+1th memory block, adjacent to the I12460.doc 1312570, the first block 0 ~ The first J+1 data in the first data drive block is the horse area. 4. For example, the integrated circuit of item 3 is located, wherein the foregoing is a device for synchronizing the bit slab between the foregoing and the chuan memory block, and the body block is the integrated circuit device of claim 2, wherein - When the direction is the third direction, 'in the first to the first memory: in the block: the third direction side of the first memory block (training), and the first to the first data are arranged adjacent to each other. In the driver block, the data drive % 5 ° is arranged on the first direction side of the first J memory block, and the J+1th data drive block in the first to the first data drive blocks is arranged. The first direction side of the J+1th data driver block is adjacent to the J+1th memory block in the first to the second memory blocks. An integrated circuit device in which, when accessing from the host side, only the word lines of the memory blocks corresponding to the access areas in the first to the second memory blocks are selected. 7. The integrated circuit device according to any one of claims 2 to 5, comprising a plurality of transponder blocks, each of which is arranged adjacent to each of the first to the first syllabic blocks. The buffer blocks respectively comprise buffers for reading data signals from the first to the first memory blocks, and are selected in the first-first memory block. In the case of the J memory block (1 g j < I), the read data signal from the aforementioned j-th memory block is forwarded by the 112460.doc 1312570 corresponding to the aforementioned j-th memory block. The buffer is buffered and output to the read data line. When the selected memory block becomes inactive and the j-th memory block becomes non-selected, the transponder corresponding to the j-th memory block is The output state of the buffer of the block is set to the 胄 impedance state. 8. As requested! The integrated circuit device of the fifth aspect, wherein the word core of the memory cell connected to the memory block is routed along the second direction in the memory block, and the data driver is Block output memory in the aforementioned memory block The bit line of the image data is routed along the first direction in the memory block. 9. The integrated circuit device according to any one of the preceding claims, wherein the data from the meta-memory block to the aforementioned data (four) block is read and stored in the memory area several times between i horizontal sweeps. Block image data. ' 10. =: 9 Γ 体 电路 电路 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The memory block is stored in the memory block. The driver block includes the data device driver along the foregoing J. Directions and stacking configuration of several 12 · As in Item 11 of the integrated circuit device, Fu Zhong Xi Chu, U in the number of data-driven test of the first data drive latch self-help ^^u In the first fire-fighting period, the block reads the image of the first reading of the image (10), and converts the image signal obtained by D/A to the image of the lock. 112460.doc 1312570 to the data signal output line, . The above several data driver memory blocks are flashed from the aforementioned data in the aforementioned first-before-be-loaded device, and the image is read for the second time during the door lock 7-level scanning. The data is converted (10) and output to the data signal output line by the DM 13 material signal. I3· The first one of the integrated circuits of the U, wherein the plurality of data drivers and the bucker drivers respectively comprise: the device is configured to operate in the first voltage region, & The first circuit of the circuit is configured with a second circuit region of the circuit that operates at a second voltage level than the first voltage level, and the first data driver of the second data driver A circuit area is adjacent to the flute. And a fifth memory block, wherein the first circuit region of the second data driver is disposed adjacent to the second memory block. The integrated circuit device of any one of the items 1 to 5, wherein the number of pixels in the horizontal scanning direction of the display panel is taken as the number of pixels, and the number of bits of the image data of the i pixel portions is taken as the PDB, and the memory area is used. The number of blocks in the block is taken as MBN. When the number of readings of the image data read from the memory block during one horizontal scanning is taken as RN, the sense amplifier block of the memory block includes the second direction along the foregoing direction. For the P sense amplifiers that are juxtaposed, the number P of the sense amplifiers is p = (MBNxRN). 15. The integrated circuit device of any one of claims 1 to 5, wherein the sense amplifier block of the memory block 112460.doc 1312570 is in the first direction of the plurality of sense amplifiers.隹1 configuration, such as the integrated circuit device of claim 15, wherein in the first direction side of the second sense amplifier being stacked, along the memory cell line of the two columns juxtaposed in the foregoing: The memory cell row of the upper side = read and connected to the aforementioned -_ amplifier, and the bit line of the memory of the lower side is connected to the second sense amplifier. The integrated circuit device of any one of the items 1 to 5, wherein the output line for driving the front block 15 block and the data line are electrically connected to each other; The data driver block is disposed on the first direction side and disposed on the first direction side of the memory block. 18. The integrated circuit device of claim 17, wherein the data driver block comprises a plurality of sub-pixel driver cells, wherein the respective transmission lines are data signals of image data of the i sub-pixel portions, The rearranged wiring area in which the output signal extraction lines of the pixel driver cells are rearranged is arranged in the arrangement area of the sub-pixel driving thieves. The integrated circuit device of claim 18, wherein the first plurality of sub-pixels drive the output line of the output signal take-out line of the sub-pixel driver cells of the first group to be in the first-rear arrangement The line areas are rearranged in a sequence, and the second group of the output lines of the output signal take-out lines belonging to the second group of sub-pixel driver cells are described in the second H2460.doc 1312570 rearrangement wiring. The areas are rearranged in order. 20. If the integrated circuit of any one of the claims 1 to 5 is set, the driver block contains several sub-pixels, and the above information corresponds to! The image of the sub-pixel part is the data signal of each rim greedy, which is used to supply the main image Gong gong from the memory block to the former; the image data supply for the pixel driver is total /a *. 0, the detection of a plurality of the aforementioned sub-pixel hindrance cells, and along the aforementioned first direction wiring. The device f is configured to: wherein the sub-pixel drive includes a DM conversion for converting the image f material using a gray scale voltage for supplying the gray scale voltage supply for the gray scale voltage in the D/A converter. The second direction wiring is spanned across a plurality of the aforementioned sub-pixels (four). ~耆 22. An integrated circuit device of claim 21, wherein an N-type transistor region and a p-type transistor region are disposed along the second direction in an arrangement region of the D/A converter of the sub-pixel driver cell, A circuit arrangement region other than the D/A converter of the sub-pixel driver cell is disposed with a _ transistor region and a p-type transistor region along the first direction. 23. The integrated circuit device of claim 22, wherein the N-type transistor and the p-type transistor are disposed in the transistor region, the p-type transistor region, and the p-type transistor region of the configuration region of the D/A converter. A transfer gate constituting the electric waste selector of the aforementioned D/A converter. The integrated circuit device according to any one of the preceding claims, comprising: 112460.doc 1312570, disposed on the second direction side of the first to Nth circuit blocks, along the fourth side a first interface region; and a second interface disposed along the second side of the first to Nth circuit blocks on the fourth direction side of the first to Nth circuit blocks when the opposite direction of the second direction is the fourth direction region. An electronic device comprising: the integrated circuit device according to any one of claims 1 to 5, and a display panel driven by the integrated circuit device. 112460.doc