JP5278453B2 - Integrated circuit device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slim, long and thin integrated circuit device and electronic equipment including the same. <P>SOLUTION: An integrated circuit device includes: first to N-th circuit blocks CB1 to CBN disposed along a D1 direction; a first interface area 12 provided at the D2 direction side of the CB1 to CBN; and a second interface area 14 formed at the D4 direction side of CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and the circuit block excluding the data driver block DB, and when widths in the D2 direction of the first interface area 12, the circuit blocks CB1 to CBN, and the second interface area 14 are set as W1, WB, and W2, respectively, a width W in the D2 direction of the integrated circuit device is expressed by W1+WB+W2&le;W&lt;W1+2&times;WB+W2. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

JP 2001-222249 A

  The present invention has been made in view of the technical problems as described above, and an object thereof is to provide a slim and long integrated circuit device and an electronic apparatus including the same.

  In the present invention, the direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the second side, which is the long side of the integrated circuit device, faces the second side. When the direction toward the fourth side is the second direction, the first to Nth circuit blocks (N is an integer greater than or equal to 2) arranged along the first direction, and the first to first The first interface region provided along the fourth side on the second direction side of the Nth circuit block and the direction opposite to the second direction as the fourth direction, And a second interface region provided along the second side on the fourth direction side of the first to Nth circuit blocks, and the first to Nth circuit blocks drive data lines. At least one data driver block and other than the data driver block When the widths of the first interface region, the first to Nth circuit blocks, and the second interface region in the second direction are W1, WB, and W2, respectively. In addition, the width W of the integrated circuit device in the second direction relates to the integrated circuit device in which W1 + WB + W2 ≦ W <W1 + 2 × WB + W2.

  In the present invention, the integrated circuit device includes first to Nth circuit blocks arranged along the first direction, and first and second interface regions. The first to Nth circuit blocks include a data driver block and circuit blocks other than the data driver block. Then, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 holds for the widths W1, WB, and W2 of the first interface region, the first to Nth circuit blocks, and the second interface region. According to the integrated circuit device in which such a relational expression is satisfied, the width in the second direction can be reduced while ensuring the width of the circuit block in the second direction (without making an excessive flat layout), and slim. And an elongated integrated circuit device can be provided. This makes it possible to achieve both ease of mounting and cost reduction of the apparatus. Further, since the circuit block is not excessively flat, the layout design is facilitated, and the development period of the apparatus can be shortened.

  According to the present invention, the first interface area is arranged on the second direction side of the data driver block without any other circuit block, and the second interface area is formed of the data driver block. You may make it arrange | position without passing through another circuit block in the said 4th direction side.

  In this way, the width of the first to Nth circuit blocks in the second direction can be set based on the width of the data driver block in the second direction. And at least in the portion where the data driver block exists, only one circuit block (data driver block) exists in the second direction, so that the layout of the data driver block is elongated without being excessively flattened. The integrated circuit device can be realized.

  In the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction. Each of the driver cells outputs a data signal corresponding to image data for one subpixel, and includes a plurality of subpixel driver cells arranged in the first direction in the driver cell. Good.

  If each driver cell is configured by arranging a plurality of subpixel driver cells along the first direction in this way, the width of each driver cell in the second direction can be reduced, and the second of the data driver block can be reduced. The width in the direction can also be reduced.

  In the present invention, a rearrangement wiring area for rearranging the arrangement order of the output lines for the output signals of the subpixel driver cells may be provided in the arrangement area of the subpixel driver cells.

  In this way, switching of the wiring layer in the wiring region between the pad and the data driver block can be minimized, and the width of the wiring region in the second direction can be reduced.

  In the present invention, the subpixel driver cell includes a D / A converter that performs D / A conversion of image data using a gradation voltage, and the D / A converter of the subpixel driver cell is arranged. In the region, an N-type transistor region and a P-type transistor region are disposed along the second direction, and in a region where a circuit other than the D / A converter of the subpixel driver cell is disposed, An N-type transistor region and a P-type transistor region may be disposed along.

  According to this configuration, for example, the signal line wired along the second direction with respect to the N-type transistor in the N-type transistor region and the P-type transistor in the P-type transistor region arranged along the second direction. Can be connected in common and layout efficiency can be improved. On the other hand, if the N-type transistor region and the P-type transistor region of the circuit other than the D / A converter are arranged along the first direction, an efficient layout along the signal flow becomes possible.

  According to the present invention, the transfer gate of the voltage selector of the D / A converter includes the N-type transistor region in the arrangement region of the D / A converter, the N-type transistor and the P-type transistor arranged in the P-type transistor region. May be configured.

  In this way, for example, signal lines wired along the second direction can be commonly connected to the N-type and P-type transistors constituting the transfer gate, and layout efficiency can be improved.

  In the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction. When the width of the driver cell in the second direction is WD and the width of the peripheral circuit portion included in the data driver block is WPCB, the width of the first to Nth circuit blocks The width WB in the second direction may be Q × WD ≦ WB <(Q + 1) × WD + WPCB.

  If a plurality of driver cells are arranged along the second direction in this way, image data signals from other circuit blocks arranged along the first direction can be efficiently input to these driver cells. it can. The width of the integrated circuit device in the second direction can be reduced by minimizing the width of the data driver block in the second direction.

  In the present invention, HPN is the number of pixels in the horizontal scanning direction of the display panel, DBN is the number of data driver blocks, and IN is the number of times image data is input to the driver cell in one horizontal scanning period. In this case, the number Q of the driver cells arranged along the second direction may be Q = HPN / (DBN × IN).

  In this way, the width of the first to Nth circuit blocks in the second direction can be set to an optimum width according to the number of data driver blocks and the number of times image data is input.

  In the present invention, the first to Nth circuit blocks may include at least one memory block for storing image data.

  In the present invention, the first interface area is arranged on the second direction side of the memory block without any other circuit block, and the second interface area is the first interface area of the memory block. It may be arranged on the direction 4 side without interposing other circuit blocks.

  In this way, the widths of the first to Nth circuit blocks can be set based on the width of the memory block. Since at least a circuit block (memory block) exists in the second direction at least in a portion where the memory block exists, a narrow integrated circuit device can be realized.

  In the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction. Each of the driver cells outputs a data signal corresponding to image data for one subpixel, and each of the subcells for R, G, and B arranged along the first direction in the driver cell. A portion corresponding to one pixel of the sense amplifier block including the pixel driver cell and included in the memory block may include R, G, and B sense amplifiers arranged along the second direction.

  Thus, if each driver cell is configured by arranging subpixel driver cells for R (red), G (green), and B (blue) along the first direction, the second of each driver cell is formed. The width in the direction of can be reduced. Also, the R, G, and B sense amplifiers corresponding to these R, G, and B subpixel driver cells are arranged in a portion corresponding to one pixel in the sense amplifier block. Therefore, the signal line can be efficiently connected between the subpixel driver cell and the sense amplifier.

  In the present invention, in the sense amplifier block of the memory block, a plurality of sense amplifiers may be stacked in the first direction.

  In this way, since the output pitch of the image data supply line from the memory block in the second direction can be narrowed, the width of the memory block in the second direction can be reduced.

  In the present invention, the memory cell column in the upper row of the two memory cell columns arranged along the first direction on the first direction side of the first and second sense amplifiers arranged in a stack. This bit line may be connected to the first sense amplifier, and the bit line of the memory cell column in the lower row may be connected to the second sense amplifier.

  In this way, a cell having a narrow width in the second direction can be used as the memory cell, and the memory block can be highly integrated.

  In the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction. When the width in the second direction of the driver cell is WD and the width in the second direction of the peripheral circuit portion included in the memory block is WPC, Q × WD ≦ WB <(Q + 1) × It may be WD + WPC.

  In this way, the width of the data driver block in the second direction can be minimized, and the width of the integrated circuit device in the second direction can be reduced.

  In the present invention, HPN is the number of pixels in the horizontal scanning direction of the display panel, DBN is the number of data driver blocks, and IN is the number of times image data is input to the driver cell in one horizontal scanning period. In this case, the number Q of the driver cells arranged along the second direction may be Q = HPN / (DBN × IN).

  According to the present invention, each of the sense amplifier blocks included in the memory block includes P sense amplifiers that each output 1-bit image data and are arranged along the second direction, When the width in the second direction is WS, the number of bits of image data for one pixel is PDB, and the width in the second direction of the peripheral circuit portion included in the memory block is WPC, P × WS ≦ WB <(P + PDB) × WS + WPC.

  In this way, the width of the integrated circuit device in the second direction can be reduced by minimizing the width of the memory block in the second direction.

  In the present invention, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN, and data is read from the memory block in one horizontal scanning period. When the number of read times of image data is RN, the number P of sense amplifiers arranged along the second direction may be P = (HPN × PDB) / (MBN × RN).

  In this way, the width in the second direction of the first to Nth circuit blocks can be set to an optimum width according to the number of blocks of the memory block and the number of times image data is read.

  In the present invention, image data stored in the memory block may be read a plurality of times in one horizontal scanning period with respect to an adjacent data driver block from the memory block.

  This reduces the number of memory cells in the second direction of the memory block, so that the width of the memory block in the second direction can be reduced, and the width of the integrated circuit device in the second direction is also reduced. It becomes possible.

  In the present invention, a first data driver of the plurality of data drivers latches image data read from the memory block for the first time in a first horizontal scanning period, and stores the latched image data. D / A conversion is performed, a data signal obtained by the D / A conversion is output to a data signal output line, and a second data driver of the plurality of data drivers is connected to the first horizontal from the memory block. The image data read for the second time in the scanning period is latched, D / A conversion of the latched image data is performed, and a data signal obtained by the D / A conversion is output to the data signal output line. Also good.

  In this way, each of the first and second data drivers need only latch the image data read for the first time and the second time and perform D / A conversion. Therefore, it is possible to prevent a situation in which the width of the integrated circuit device in the second direction becomes large due to the large scale of the first and second data drivers.

  In the present invention, the width W of the integrated circuit device in the second direction may be W <2 × WB.

  In this way, it is possible to reduce the width of the integrated circuit device in the second direction while ensuring a large width in the second direction of the first to Nth circuit blocks.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

1A, 1B, and 1C are explanatory diagrams of a comparative example of the present embodiment. FIGS. 2A and 2B are explanatory views for mounting an integrated circuit device. 1 is a configuration example of an integrated circuit device according to an embodiment. Examples of various types of display drivers and the circuit blocks they contain. 5A and 5B are plan layout examples of the integrated circuit device of this embodiment. 6A and 6B are examples of cross-sectional views of the integrated circuit device. 6 is a circuit configuration example of an integrated circuit device. 8A, 8B, and 8C are configuration examples of a data driver and a scan driver. 9A and 9B are configuration examples of a power supply circuit and a gradation voltage generation circuit. 10A, 10B, and 10C are configuration examples of a D / A conversion circuit and an output circuit. 11A and 11B are explanatory diagrams of the width of the integrated circuit device. 12A to 12E are explanatory views of the width of the data driver block. 13A and 13B are explanatory diagrams of the width of the memory block. 14A and 14B are explanatory diagrams of a comparative example. 15A and 15B are configuration examples of memory blocks. Explanatory drawing about the relationship between W1, W2, and WB. 17A and 17B are explanatory diagrams of the arrangement of memory blocks and data driver blocks. Explanatory drawing of the method of reading image data in multiple times in 1 horizontal scanning period. Data driver and driver cell arrangement example. 20A, 20B, and 20C are configuration examples of memory cells. An arrangement example of memory blocks and driver cells in the case of a horizontal cell. An arrangement example of memory blocks and driver cells in the case of a vertical cell. 23A and 23B are configuration examples of electronic devices. An arrangement example of subpixel driver cells. An example of arrangement of sense amplifiers and memory cells. Explanatory drawing of a pad wiring method. 27 (A) and 27 (B) are explanatory views of usage modes and the like of the aluminum wiring layer. 2 shows a configuration example of a subpixel driver cell. The structural example of a D / A converter. FIGS. 30A, 30B, and 30C are explanatory diagrams of a truth table of a sub-decoder of a D / A converter and a layout of the D / A converter.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1A shows an integrated circuit device 500 as a comparative example of the present embodiment. The integrated circuit device 500 of FIG. 1A includes a memory block MB (display data RAM) and a data driver block DB. The memory block MB and the data driver block DB are arranged along the direction D2. Further, the memory block MB and the data driver block DB are ultra flat blocks whose length along the D1 direction is longer than the width in the D2 direction.

  Image data from the host side is written in the memory block MB. The data driver block DB converts the digital image data written in the memory block MB into an analog data voltage and drives the data lines of the display panel. Thus, in FIG. 1A, the signal flow of the image data is in the direction D2. For this reason, in the comparative example of FIG. 1A, the memory block MB and the data driver block DB are arranged along the direction D2 in accordance with the flow of this signal. By doing so, a short path is formed between the input and the output, the signal delay can be optimized, and efficient signal transmission becomes possible.

  However, the comparative example of FIG. 1A has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, when a fine process is employed and the integrated circuit device 500 is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced. Therefore, as shown in FIG. 2A, there is a problem of difficulty in mounting. That is, the output pitch is desirably 22 μm or more, for example, but a simple shrink as shown in FIG. 2A has a pitch of 17 μm, for example, which makes mounting difficult due to the narrow pitch. Moreover, the frame of the glass of the display panel is widened, the number of pieces of glass is reduced, and the cost is increased.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the comparative example of FIG. 1A, in some products, as shown in FIG. 1B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match, the configuration of the memory and data driver changes. As shown in FIG. 1C, these pitches do not match. If the pitches do not match as shown in FIG. 1C, a useless wiring region for absorbing the pitch mismatch must be formed between the circuit blocks. In particular, in the comparative example of FIG. 1A in which the block is flat in the D1 direction, a useless wiring area for absorbing the pitch mismatch becomes large. As a result, the width W of the integrated circuit device 500 in the D2 direction is increased, the chip area is increased, and the cost is increased.

  On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost. That is, in the comparative example of FIG. 1A, the circuit configuration and layout of each circuit block are individually designed, and then the pitch and the like are adjusted, resulting in useless empty areas and inefficient design. Problems arise.

2. Configuration of Integrated Circuit Device FIG. 3 shows a configuration example of the integrated circuit device 10 of the present embodiment that can solve the above problems. In the present embodiment, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is defined as a first direction D1, and the opposite direction of D1 is defined as a third direction D3. Yes. The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 3, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side SD1. May be.

  As shown in FIG. 3, the integrated circuit device 10 of this embodiment includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. That is, in the comparative example of FIG. 1A, the circuit blocks are arranged in the D2 direction, but in this embodiment, the circuit blocks CB1 to CBN are arranged in the D1 direction. Further, each circuit block is not a very flat block as in the comparative example of FIG. 1A, but is a relatively square block.

  The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F region 12 (first I / O region) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second I / O area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks. That is, at least in the portion where the data driver block exists, there is only one circuit block (data driver block) in the direction D2. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, etc., it may be configured such that at least one of the I / F regions 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, it includes an output transistor for outputting a data signal to the data line and a scanning signal to the scanning line. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like are included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be further included.

  For example, FIG. 4 shows examples of various types of display drivers and circuit blocks incorporated therein. In a display driver for an amorphous TFT (Thin Film Transistor) panel with a built-in memory (RAM), circuit blocks CB1 to CBN include a memory, a data driver (source driver), a scanning driver (gate driver), a logic circuit (gate array circuit), It includes a gradation voltage generation circuit (γ correction circuit) and a power supply circuit block. On the other hand, in a display driver for a low-temperature polysilicon (LTPS) TFT panel with a built-in memory, the scanning driver can be formed on a glass substrate, so that the scanning driver block can be omitted. Also, the memory block can be omitted for an amorphous TFT panel without a memory, and the memory and scan driver blocks can be omitted for a low-temperature polysilicon TFT panel without a memory. Further, for a color super twisted nematic (CSTN) panel and a thin film diode (TFD) panel, the block of the gradation voltage generation circuit can be omitted.

  FIGS. 5A and 5B show examples of a planar layout of the integrated circuit device 10 of the display driver of this embodiment. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. FIG. 5A targets, for example, a display driver for QCIF and 32 gradations, and FIG. The display driver for gradation is targeted.

  5A and 5B, the first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense. I is 2). Including the above integer). The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  In FIG. 5A, MB1 of the memory blocks MB1 to MB4 (Jth memory block in a broad sense, 1 ≦ J <I) is placed on the D3 direction side of the data driver blocks DB1 to DB4. In a broad sense, the Jth data driver block) is arranged adjacent to each other. Further, a memory block MB2 (J + 1th memory block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB1. A data driver block DB2 (J + 1th data driver block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB2. The arrangement of the memory blocks MB3 and MB4 and the data driver blocks DB3 and DB4 is the same. In this way, in FIG. 5A, MB1, DB1, and MB2, DB2 are arranged symmetrically with respect to the boundary lines of MB1 and MB2, and MB3, DB3, and MB4 are arranged symmetrically with respect to the boundary lines of MB3 and MB4. , DB4 are arranged. In FIG. 5A, DB2 and DB3 are arranged adjacent to each other, but other circuit blocks may be arranged between them without adjoining them.

  On the other hand, in FIG. 5B, DB1 (Jth data driver block) of the data driver blocks DB1 to DB4 is on the D3 direction side of MB1 (Jth memory block) of the memory blocks MB1 to MB4. Adjacent to each other. Further, DB2 (J + 1th data driver block) is arranged on the D1 direction side of MB1. MB2 (J + 1th memory block) is arranged on the D1 direction side of DB2. DB3, MB3, DB4, and MB4 are similarly arranged. In FIG. 5B, MB1 and DB2, MB2 and DB3, and MB3 and DB4 are arranged adjacent to each other, but other circuit blocks may be arranged between them without being adjacent to each other. Good.

  5A has an advantage that the column address decoder can be shared between the memory blocks MB1 and MB2 and between the MB3 and MB4 (between the Jth and J + 1th memory blocks). On the other hand, according to the layout arrangement of FIG. 5B, there is an advantage that the wiring pitch of the data signal output lines from the data driver blocks DB1 to DB4 to the output side I / F region 12 can be made uniform, and the wiring efficiency can be improved. is there.

  The layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIGS. For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. Further, the memory block, the scan driver block, the power supply circuit block, the gradation voltage generation circuit block, or the like may be omitted. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  6A is an example of a cross-sectional view along the direction D2 of the integrated circuit device of this embodiment, and FIG. 6B is an example of a cross-sectional view of a comparative example. In the comparative example of FIG. 1A, as shown in FIG. 6B, two or more circuit blocks are arranged along the direction D2. In the D2 direction, a wiring region is formed between the circuit blocks or between the circuit block and the I / F region. Therefore, the width W of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a slim elongated chip cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened as shown in FIG. Incurs difficulty in implementation.

  On the other hand, in this embodiment, as shown in FIGS. 3, 5A and 5B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. Further, as shown in FIG. 6A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, as shown in FIG. 2B, the width W in the D2 direction can be narrowed while maintaining the length LD in the D1 direction of the integrated circuit device 10, and an ultra slim slim chip can be realized. As a result, the output pitch can be maintained at, for example, 22 μm or more, and mounting can be facilitated.

  In the present embodiment, since the plurality of circuit blocks CB1 to CBN are arranged along the direction D1, it is possible to easily cope with a change in product specifications and the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIGS. 5A and 5B, even when the number of pixels and the number of gradations of the display panel increase or decrease, the number of memory blocks and data driver blocks, the number of times image data is read out in one horizontal scanning period, etc. Just increase or decrease the number. FIGS. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. When developing a product for a low-temperature polysilicon TFT panel with a built-in memory, scanning is performed from among the circuit blocks CB1 to CBN. Just remove the driver block. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, in this embodiment, the influence of the circuit block on the other circuit blocks can be minimized, so that the design efficiency can be improved.

  In the present embodiment, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified with, for example, the width (height) of the data driver block and the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIGS. 5A and 5B, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors is increased or decreased, the direction of the gradation voltage generation circuit block or the power supply circuit block in the direction D1 This can be dealt with by increasing or decreasing the length.

  As a second comparative example, there is also a method in which, for example, the data driver block is elongated in the D1 direction, and other circuit blocks such as a memory block are arranged along the D1 direction on the D4 direction side of the data driver block. Conceivable. However, in the second comparative example, a data driver block having a large width is interposed between another circuit block such as a memory block and the output-side I / F region. Therefore, in the D2 direction of the integrated circuit device. The width W becomes larger, and it becomes difficult to realize a slim elongated chip. In addition, a useless wiring area is generated between the data driver block and the memory block, and the width W is further increased. Further, when the configuration of the data driver block or the memory block is changed, the pitch mismatch problem described with reference to FIGS. 1B and 1C occurs, and the design efficiency cannot be improved.

  Further, as a third comparative example of the present embodiment, a method in which only circuit blocks having the same function (for example, data driver blocks) are divided into blocks and arranged in the D1 direction is also conceivable. However, in the third comparative example, since the integrated circuit device can have only the same function (for example, the function of the data driver), various product development cannot be realized. On the other hand, in the present embodiment, the circuit blocks CB1 to CBN include circuit blocks having at least two different functions. Accordingly, as shown in FIGS. 4, 5A and 5B, there is an advantage that various types of integrated circuit devices corresponding to various types of display panels can be provided.

3. Circuit Configuration FIG. 7 shows a circuit configuration example of the integrated circuit device 10. The circuit configuration of the integrated circuit device 10 is not limited to that shown in FIG. 7, and various modifications can be made. The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). In this case, one pixel is composed of, for example, three subpixels (3 dots) of R, G, and B, and image data of, for example, 6 bits (k bits) is stored for each subpixel. The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22. The access area of the memory cell array 22 is defined by, for example, a rectangle having a start address and an end address as opposite vertices. That is, an access area is defined by the column address and row address of the start address and the column address and row address of the end address, and memory access is performed.

  The logic circuit 40 (for example, an automatic placement and routing circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation characteristic (γ characteristic) adjustment data (γ correction data) is output to the gradation voltage generation circuit 110 and voltage generation of the power supply circuit 90 is controlled. Further, it controls the write / read processing to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28. The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory to the display panel side. The host (MPU) interface circuit 46 implements a host interface that generates an internal pulse for each access from the host and accesses the memory. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to a memory using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  In FIG. 7, the host interface circuit 46 and the RGB interface circuit 48 access the memory 20 in units of pixels. On the other hand, to the data driver 50, image data designated by a line address and read in units of lines is sent for each line period at an internal display timing independent of the host interface circuit 46 and the RGB interface circuit 48.

  The data driver 50 is a circuit for driving the data lines of the display panel, and FIG. 8A shows a configuration example thereof. The data latch circuit 52 latches digital image data from the memory 20. The D / A conversion circuit 54 (voltage selection circuit) performs D / A conversion of the digital image data latched by the data latch circuit 52 and generates an analog data voltage. Specifically, a plurality of (for example, 64 levels) gradation voltages (reference voltages) are received from the gradation voltage generation circuit 110, and a voltage corresponding to digital image data is selected from the plurality of gradation voltages. And output as a data voltage. The output circuit 56 (drive circuit, buffer circuit) buffers the data voltage from the D / A conversion circuit 54 and outputs it to the data line of the display panel to drive the data line. Note that a part of the output circuit 56 (for example, an output stage of an operational amplifier) may not be included in the data driver 50 but may be arranged in another region.

  The scan driver 70 is a circuit for driving the scan lines of the display panel, and FIG. 8B shows a configuration example thereof. The shift register 72 includes a plurality of flip-flops sequentially connected, and sequentially shifts the enable input / output signal EIO in synchronization with the shift clock signal SCK. The level shifter 76 converts the voltage level of the signal from the shift register 72 into a high voltage level for scanning line selection. The output circuit 78 buffers the scanning voltage converted and output by the level shifter 76 and outputs it to the scanning line of the display panel to selectively drive the scanning line. Note that the scan driver 70 may have the configuration shown in FIG. In FIG. 8C, the scan address generation circuit 73 generates and outputs a scan address, and the address decoder performs a scan address decoding process. A scanning voltage is output via the level shifter 76 and the output circuit 78 to the scanning line specified by this decoding process.

  The power supply circuit 90 is a circuit that generates various power supply voltages, and FIG. The booster circuit 92 is a circuit that boosts the input power supply voltage and the internal power supply voltage by a charge pump method using a boosting capacitor and a boosting transistor, and generates a boosted voltage, and includes primary to quaternary boosting circuits and the like. be able to. The booster circuit 92 can generate a high voltage used by the scan driver 70 and the gradation voltage generation circuit 110. The regulator circuit 94 adjusts the level of the boosted voltage generated by the booster circuit 92. The VCOM generation circuit 96 generates and outputs a VCOM voltage supplied to the counter electrode of the display panel. The control circuit 98 controls the power supply circuit 90 and includes various control registers.

  A gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage, and FIG. 9B shows a configuration example thereof. The selection voltage generation circuit 112 (voltage division circuit) generates selection voltages VS0 to VS255 (R selection voltages in a broad sense) based on the high voltage power supply voltages VDDH and VSSH generated by the power supply circuit 90. Output. Specifically, the selection voltage generation circuit 112 includes a ladder resistor circuit having a plurality of resistor elements connected in series. Then, voltages obtained by dividing VDDH and VSSH by the ladder resistor circuit are output as selection voltages VS0 to VS255. Based on the gradation characteristic adjustment data set in the adjustment register 116 by the logic circuit 40, the gradation voltage selection circuit 114 is selected from among the selection voltages VS0 to VS255, for example, 64 in the case of 64 gradations ( In a broad sense, S voltages (R> S) are selected and output as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel. In the case of polarity inversion driving, a positive ladder resistance circuit and a negative ladder resistance circuit may be provided in the selection voltage generation circuit 112. Further, the resistance value of each resistance element of the ladder resistor circuit may be changed based on the adjustment data set in the adjustment register 116. Further, the selection voltage generation circuit 112 and the gradation voltage selection circuit 114 may be provided with an impedance conversion circuit (an operational amplifier having a voltage follower connection).

  FIG. 10A shows a configuration example of each DAC (Digital Analog Converter) included in the D / A conversion circuit 54 of FIG. Each DAC in FIG. 10A can be provided, for example, for each subpixel (or for each pixel), and is configured by a ROM decoder or the like. Then, based on the 6-bit digital image data D0 to D5 from the memory 20 and the inverted data XD0 to XD5, any one of the gradation voltages V0 to V63 from the gradation voltage generation circuit 110 is selected. Data D0 to D5 are converted into analog voltages. The obtained analog voltage signal DAQ (DAQR, DAQG, DAQB) is output to the output circuit 56.

  In addition, when the data signals for R, G, and B are multiplexed and sent to the display driver by the display driver for the low-temperature polysilicon TFT (in the case of FIG. 10C), for R and G , B image data can also be D / A converted using one common DAC. In this case, each DAC in FIG. 10A is provided for each pixel.

  FIG. 10B shows a configuration example of each output unit SQ included in the output circuit 56 of FIG. Each output unit SQ in FIG. 10B can be provided for each pixel. Each output unit SQ includes impedance conversion circuits OPR, OPG, and OPB (voltage follower-connected operational amplifiers) for R (red), G (green), and B (blue), and signals DAQR and DAQQ from the DAC , DAQB impedance conversion is performed, and data signals DATAR, DATAG, and DATAB are output to the R, G, and B data signal output lines. For example, in the case of a low-temperature polysilicon TFT panel, switch elements (switch transistors) SWR, SWG, and SWB as shown in FIG. 10C are provided, and data signals for R, G, and B are multiplexed. The impedance conversion circuit OP may output the data signal DATA that has been processed. Further, the data signal may be multiplexed over a plurality of pixels. Further, the output unit SQ may be provided with only a switch element or the like without providing the impedance conversion circuit as shown in FIGS.

4). 4.1 Width of Integrated Circuit Device 4.1 Elongated Integrated Circuit Device In this embodiment, as shown in FIG. 11A, the first to Nth circuit blocks CB1 to CBN include at least one for driving a data line. Includes data driver block DB. CB1 to CBN include circuit blocks other than the data driver block DB (circuit blocks that realize functions different from DB). Here, the circuit blocks other than the data driver block DB are, for example, logic circuit blocks (40 in FIG. 7). Alternatively, it is a gradation voltage generation circuit block (110 in FIG. 7) or a power supply circuit block (90 in FIG. 7). Alternatively, it is a memory block (20 in FIG. 7) in the case of a built-in memory, and a scan driver block (70 in FIG. 7) in the case of an amorphous TFT.

  In FIG. 11A, W1, WB, and W2 are an output side I / F area 12 (first interface area), first to Nth circuit blocks CB1 to CBN, and an input side I / F area, respectively. 14 (second interface area) in the D2 direction.

  In this embodiment, as shown in FIG. 11A, when the width of the integrated circuit device 10 in the D2 direction is W, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 holds. That is, in the comparative example of FIG. 6B, two or more circuit blocks are arranged along the direction D2. Therefore, the width W in the D2 direction is W ≧ W1 + 2 × WB + W2. On the other hand, in the present embodiment, the output-side I / F area 12 is arranged on the D2 direction side of the data driver block DB (or the memory block) without passing through other circuit blocks. That is, the data driver block DB and the output side I / F area 12 are arranged adjacent to each other. The input-side I / F area 14 is arranged on the D4 direction side of the data driver block DB (or memory block) without passing through other circuit blocks. That is, the data driver block DB and the input side I / F area 14 are arranged adjacent to each other. The other circuit blocks in this case are, for example, main macro circuit blocks (grayscale voltage generation circuit, power supply circuit, memory, logic circuit block, etc.) constituting the display driver.

  In the comparative example of FIGS. 1A and 6B, since W ≧ W1 + 2 × WB + W2, the width W in the D2 direction (short side direction) of the integrated circuit device 500 is increased, and a slim elongated chip is obtained. Cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened as shown in FIG. Incurs difficulty in implementation.

  On the other hand, in this embodiment, since no other circuit block is interposed between the data driver block DB and the I / F areas 12 and 14, W <W1 + 2 × WB + W2 holds. Therefore, the width W of the integrated circuit device in the direction D2 can be reduced, and a slim and slender chip as shown in FIG. 2B can be realized. Specifically, the width W in the D2 direction, which is the short side direction, can be W <2 mm, and more specifically, W <1.5 mm. In consideration of chip inspection and mounting, it is desirable that W> 0.9 mm. The length LD in the long side direction can be 15 mm <LD <27 mm. The chip shape ratio SP = LD / W can be set to SP> 10, and more specifically, SP> 12. In this way, according to specifications such as the number of pins, for example, W = 1.3 mm, LD = 22 mm, SP = 16.9, W = 1.35 mm, LD = 17 mm, SP = 12.6. An elongated integrated circuit device can be realized. As a result, the mounting can be facilitated as shown in FIG. Moreover, since the chip area is reduced, the cost can be reduced. In other words, both ease of mounting and cost reduction can be achieved.

  Note that the arrangement method of the comparative example in FIG. 1A is also reasonable if the direction of the signal flow of image data is taken into consideration. In this regard, in this embodiment, as shown in FIG. 11B, the output line DQL of the data signal from the data driver block DB is wired along the direction D2 in the DB. On the other hand, the data signal output line DQL is wired along the direction D1 (D3) in the output-side I / F region 12 (first interface region). Specifically, in the output-side I / F region 12, the data signal output line DQL is arranged along the D1 direction by using a global wiring that is lower than the pad and higher than the local wiring (transistor wiring) in the area. Wiring. In this way, even if an arrangement method in which no other circuit block is interposed between the data driver block DB and the I / F regions 12 and 14 as shown in FIG. It is possible to output properly to the display panel via the pad. If the data signal output line DQL is wired as shown in FIG. 11B, the data signal output line DQL can be connected to a pad or the like by using the output side I / F region 12, and the integrated circuit An increase in the width W in the direction D2 of the apparatus can be prevented.

  Note that the widths W1, WB, and W2 in FIG. 11A are the transistor formation regions (bulk region and active region) of the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Width. That is, in the I / F regions 12 and 14, an output transistor, an input transistor, an input / output transistor, a transistor of an electrostatic protection element, and the like are formed. In the circuit blocks CB1 to CBN, transistors constituting the circuit are formed. W1, WB, and W2 are determined based on a well region, a diffusion region, or the like where such a transistor is formed. For example, in order to realize a slimmer integrated circuit device, it is desirable to form bumps (active surface bumps) also on the transistors of the circuit blocks CB1 to CBN. Specifically, a resin core bump having a core formed of a resin and a metal layer formed on the surface of the resin is formed on the transistor (active region). The bumps (external connection terminals) are connected to pads arranged in the I / F regions 12 and 14 by metal wiring. In the present embodiment, W1, WB, and W2 are not the width of the bump formation region but the width of the transistor formation region formed under the bump.

  The widths of the circuit blocks CB1 to CBN in the D2 direction can be unified to the same width, for example. In this case, the widths of the circuit blocks may be substantially the same. For example, a difference of about several μm to 20 μm (several tens of μm) is within an allowable range. When circuit blocks having different widths exist in the circuit blocks CB1 to CBN, the width WB can be the maximum width among the circuit blocks CB1 to CBN. The maximum width in this case can be, for example, the width of the data driver block in the D2 direction. Alternatively, in the case of an integrated circuit device with a built-in memory, the width in the direction D2 of the memory block can be set. An empty area with a width of about 20 to 30 μm can be provided between the circuit blocks CB1 to CBN and the I / F areas 12 and 14, for example.

4.2 Width of Data Driver Block In this embodiment, as shown in FIG. 12A, the data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRC1 arranged side by side along the direction D2. DRCQ may be included. Here, each of driver cells DRC1 to DRCQ receives image data for one pixel. Then, D / A conversion of the image data for one pixel is performed, and a data signal corresponding to the image data for one pixel is output. Each of the driver cells DRC1 to DRCQ can include a data latch circuit, a DAC (DAC for one pixel) in FIG. 10A, and an output unit SQ in FIGS. 10B and 10C.

  When the width (pitch) in the D2 direction of the driver cells DRC1 to DRCQ is WD, and the width in the D2 direction of the buffer circuit BF1 or the like that is a peripheral circuit portion included in the data driver block DB is WPCB, the circuit block CB1 The width WB (maximum width) of CBN in the D2 direction can be set to Q × WD ≦ WB <(Q + 1) × WD + WPCB as shown in FIG.

  That is, in the present embodiment, the circuit blocks CB1 to CBN are arranged along the direction D1. Accordingly, signal lines for image data input from other circuit blocks (for example, logic circuit blocks and memory blocks) among the circuit blocks CB1 to CBN to the data driver block DB are wirings along the direction D1. The driver cells DRC1 to DRCQ are arranged along the D2 direction as shown in FIG. 12A in order to connect to the signal lines of the image data along the D1 direction. Each of the DRC1 to DRCQ is one pixel. Are connected to the signal line of image data.

  The width WB of the circuit blocks CB1 to CBN can be determined based on, for example, the width of the data driver DB in the D2 direction in an integrated circuit device without a memory. Accordingly, in order to reduce the width WB of the circuit blocks CB1 to CBN by reducing the width of the data driver block DB in the D2 direction, the width WB is set to Q × WD which is a width in which the driver cells DRC1 to DRCQ are arranged. On the other hand, it is desirable that the width WPCB of the peripheral circuit portion such as the buffer circuit BF1 is added. Then, considering the margin for the wiring region or the like, the width WB is Q × WD ≦ WB <(Q + 1) × WD + WPCB. In this way, the width of the data driver block DB in the direction D2 can be minimized, and the width WB of the circuit blocks CB1 to CBN can be reduced, so that an elongated integrated circuit device as shown in FIG. 2B can be provided. .

  Note that the number of pixels in the horizontal scanning direction of the display panel (when the data lines of the display panel are driven by sharing with a plurality of integrated circuit devices) is HPN. It is assumed that the number of data driver blocks (the number of block divisions) is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN. Note that IN is equal to the number of read times RN of image data in one horizontal scanning period to be described later. In this case, the number Q of driver cells DRC1 to DRCQ arranged along the direction D2 can be expressed as Q = HPN / (DBN × IN). For example, when HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30.

  Further, as shown in FIG. 12B, the data driver block DB may include a plurality of data drivers DRa and DRb (first to mth data drivers) arranged side by side along the direction D1. If a plurality of data drivers DRa and DRb are arranged (stacked) along the D1 direction in this way, the width W in the D2 direction of the integrated circuit device increases due to the size of the data driver. The situation can be prevented. The data driver has various configurations depending on the type of the display panel. Also in this case, according to the method of arranging a plurality of data drivers along the direction D1, data drivers having various configurations can be efficiently laid out. FIG. 12B shows a case where the number of data drivers arranged in the direction D1 is two, but the number of arranged data drivers may be three or more.

  FIG. 12C shows an example of the configuration and arrangement of the driver cell DRC. A driver cell DRC that receives image data for one pixel includes data latch circuits DLATR, DLATG, and DLATB for R (red), G (green), and B (blue). Each data latch circuit DLATR, DLATG, DLATB latches image data when the latch signal becomes active. The driver cell DRC includes the R, G, and B DACR, DACG, and DACB described with reference to FIG. The output unit SQ described with reference to FIGS. 10B and 10C is also included.

  The configuration and arrangement of the driver cell DRC are not limited to FIG. 12C, and various modifications can be made. For example, when a data driver for R, G, and B is multiplexed and sent to a display panel as shown in FIG. 10C by a display driver for a low-temperature polysilicon TFT, one common DAC is used. It is possible to perform D / A conversion of image data for R, G, and B (image data for one pixel). Accordingly, in this case, as shown in FIG. 12D, the driver cell DRC may include one shared DAC having the configuration of FIG. 12C and 12D, an R circuit (DLATR, DACR), a G circuit (DLATG, DACG), and a B circuit (DLATB, DACB) are arranged along the direction D2 (D4). Has been placed. However, as shown in FIG. 12E, R, G, and B circuits may be arranged along the direction D1 (D3).

4.3 Memory Block Width In the integrated circuit device with a built-in memory, the data driver block DB and the memory block MB can be arranged adjacent to each other in the direction D1, as shown in FIG.

  In this regard, in the comparative example of FIG. 1A, as shown in FIG. 14A, the memory block MB and the data driver block DB are arranged along the D2 direction, which is the short side direction, according to the signal flow. Is done. For this reason, the width of the integrated circuit device in the D2 direction is increased, and it is difficult to realize a slim elongated chip. In addition, if the number of pixels of the display panel, display driver specifications, memory cell configuration, etc. change, and the width in the D2 direction and the length in the D1 direction of the memory block MB and data driver block DB change, the effect will be different. The design block becomes inefficient.

  On the other hand, in FIG. 13A, since the data driver block DB and the memory block MB are arranged along the direction D1, the width W of the integrated circuit device in the direction D2 can be reduced. In addition, when the number of pixels of the display panel changes, it is possible to cope with this by dividing the memory block, so that the design can be made efficient.

  In the comparative example of FIG. 14A, since the word line WL is arranged along the direction D1 which is the long side direction, the signal delay in the word line WL is increased, and the reading speed of the image data is decreased. In particular, since the word line WL connected to the memory cell is formed of a polysilicon layer, this signal delay problem is serious. In this case, in order to reduce the signal delay, there is a method of providing buffer circuits 520 and 522 as shown in FIG. However, when this method is adopted, the circuit scale increases correspondingly, resulting in an increase in cost.

  On the other hand, in FIG. 13A, in the memory block MB, the word line WL is wired along the D2 direction which is the short side direction, and the bit line BL is arranged along the D1 direction which is the long side direction. The In this embodiment, the width W of the integrated circuit device in the direction D2 is short. Therefore, the length of the word line WL in the memory block MB can be shortened, and the signal delay at WL can be remarkably reduced as compared with the comparative example of FIG. Further, since it is not necessary to provide the buffer circuits 520 and 522 as shown in FIG. 14B, the circuit area can be reduced. In the comparative example of FIG. 14A, even when a part of the access area of the memory is accessed from the host, the word line WL that is long in the D1 direction and has a large parasitic capacitance is selected. Become. On the other hand, according to the method of dividing the memory in the D1 direction as in the present embodiment, the memory block (Jth memory block) corresponding to the access area at the time of host access (access from the host side) Since only the word line WL is selected, low power consumption can be realized.

  In this embodiment, as shown in FIG. 13A, when the width in the D2 direction of the peripheral circuit portion included in the memory block MB is WPC, Q × WD ≦ WB <(Q + 1) × WD + WPC. Can do. Here, the peripheral circuit portion is a peripheral circuit (row address decoder, control circuit) arranged on the D2 or D4 direction side of the memory cell array MA (data driver) or between the divided memory cell arrays (data drivers). Etc.) and wiring areas.

  In the arrangement of FIG. 13A, it is desirable that the width Q × WD of the driver cells DRC1 to DRCQ and the width of the sense amplifier block SAB are matched. If these widths do not match, it is necessary to change the wiring pitch of these signal lines when connecting the signal lines of the image data from the sense amplifier block SAB to the driver cells DRC1 to DRCQ. Wiring area is generated.

  In addition to the memory cell array MA, the memory block MB has peripheral circuit portions such as a row address decoder RD. Accordingly, in FIG. 13A, the width of the memory block MB is larger than the width Q × WD of the driver cells DRC1 to DRCQ by the width WPC of the peripheral circuit portion.

  The width WB of the circuit blocks CB1 to CBN can be determined based on the width in the direction D2 of the memory block MB in an integrated circuit device with a built-in memory. Therefore, in order to reduce the width WB of the circuit blocks CB1 to CBN by reducing the width in the direction D2 of the memory block MB, it is desirable that the width WB is Q × WD ≦ WB <(Q + 1) × WD + WPC. . By so doing, the width of the memory block MB in the direction D2 can be minimized and the width WB can be reduced, so that an elongated integrated circuit device as shown in FIG. 2B can be provided.

  FIG. 13B shows an arrangement relationship between the driver cells DRC1 to DRCQ and the sense amplifier block SAB. As shown in FIG. 13B, for a driver cell DRC1 that receives image data for one pixel, a corresponding sense amplifier for one pixel (sense amplifiers SAR10 to SAR15 for R, sense amplifier for G). SAG10 to SAG15 and B sense amplifiers SAB10 to SAB15) are connected. The same applies to the connection between the other driver cells DRC2 to DRCQ and the sense amplifier.

  As shown in FIG. 13B, the width WB (maximum width) in the D2 direction of the circuit blocks CB1 to CBN is equal to the width in the D2 direction of the peripheral circuit portion (row address decoder RD) included in the memory block. When the number of bits of image data for one pixel is PDB, it can be expressed as P × WS ≦ WB <(P + PDB) × WS + WPC. Here, when each of R, G, and B is 6 bits, PDB = 18.

  Note that the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN (= DBN), and data is read from the memory block in one horizontal scanning period. Assume that the number of times of reading image data is RN. In this case, the number P of sense amplifiers arranged along the direction D2 in the sense amplifier block SAB can be expressed as P = (HPN × PDB) / (MBN × RN).

  Note that the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of ineffective sense amplifiers such as sense amplifiers for dummy memory cells. The number P is the number of sense amplifiers that output 1-bit image data. For example, when 1-bit image data is switched and output by the first and second sense amplifiers and a selector connected to the output thereof, the first and second sense amplifiers and selectors are switched. The combination is equivalent to a sense amplifier that outputs 1-bit image data.

  FIGS. 15A and 15B show detailed layout arrangement examples of the memory block MB. FIG. 15A shows an arrangement example in the case of a horizontal cell to be described later. The MPU / LCD row address decoder RD performs word line selection control during host access and word line selection control during output to the data driver block (LCD). At the time of output to the data driver block, the sense amplifier block SAB amplifies the signal of the image data read from the memory cell array MA, and outputs the image data to the data driver block. The MPU write / read circuit WR performs control of writing image data to an access target memory cell (access area) in the memory cell array MA and reading image data during host access. The MPU write / read circuit WR can include a sense amplifier for reading image data. The MPU column address decoder CD performs selection control of a bit line corresponding to a memory cell to be accessed during host access. The control circuit CC controls each circuit block in the memory block MB.

  FIG. 15B shows an arrangement example in the case of a vertical cell described later. In FIG. 15B, the memory cell array includes a first memory cell array MA1 and a second memory cell array MA2. An MPU / LCD row address decoder RD is provided between the memory cell arrays MA1 and MA2. The MPU / LCD row address decoder RD selects one of the word lines of the memory cell arrays MA1 and MA2 when accessing from the host side. Further, when outputting image data to the data driver block, both word lines of the memory cell arrays MA1 and MA2 are selected. In this way, only the word line of the memory cell array to be accessed can be selected at the time of host access, so that the signal delay on the word line compared to the method of always selecting the word line of both memory cell arrays. And power consumption can be reduced.

  In the case of FIG. 15A, an MPU / LCD row address decoder provided on the D2 (or D4) direction side of the memory cell array MA, and in the case of FIG. 15B, provided between the memory cell arrays MA1 and MA2. The RD, the control circuit CC, and the wiring area thereof are peripheral circuit portions, and the width thereof is WPC.

  In the present embodiment, the arrangement of the driver cells and the sense amplifiers has been described on the assumption of the arrangement for each pixel. However, a modification may be made in which the arrangement is for each subpixel. Also, the subpixels are not limited to the R, G, and B subpixel configurations, and may be RGB + 1 (for example, white) 4-subpixel configurations.

4.4 Relationship between WB and W1, W2 In this embodiment, as shown in FIG. 16, the width W1 in the D2 direction of the output side I / F region 12 is set to 0.13 mm ≦ W1 ≦ 0.4 mm. it can. The width WB of the circuit blocks CB1 to CBN can be set to 0.65 mm ≦ WB ≦ 1.2 mm. Further, the width W2 of the input side I / F region 14 can be 0.1 mm ≦ W2 ≦ 0.2 mm.

  For example, in the output-side I / F region 12, pads having one or more stages in the D2 direction are arranged. As shown in FIG. 6A, by arranging an output transistor, an electrostatic protection element transistor, etc. under the pad, the width W1 of the output I / F region 12 is minimized. Yes. Therefore, considering the pad width (for example, 0.1 mm) and the pad pitch, 0.13 mm ≦ W1 ≦ 0.4 mm.

  On the other hand, in the input-side I / F area 14, a pad having one stage in the D2 direction is arranged. As shown in FIG. 6A, an input transistor, an electrostatic protection transistor, and the like are arranged under the pad so that the width W2 of the input side I / F region 14 is minimized. Yes. Accordingly, in consideration of the pad width and pad pitch, 0.1 mm ≦ W2 ≦ 0.2 mm. In the output-side I / F region 12, the number of pad stages in the D2 direction is set to a plurality of stages because the number (or size) of transistors to be arranged under the pad is in the input-side I / F region 14. This is because the output-side I / F area 12 is more in comparison.

  The width WB of the circuit blocks CB1 to CBN is determined based on the width in the direction D2 of the data driver block DB and the memory block MB as described with reference to FIGS. 12A and 13A. In order to realize an elongated integrated circuit device, the logic signal from the logic circuit block, the gradation voltage signal from the gradation voltage generation circuit block, and the power supply wiring are globally arranged on the circuit blocks CB1 to CBN. It is necessary to form by wiring. The total wiring width is about 0.8 to 0.9 mm, for example. Therefore, in consideration of these, the width WB of the circuit blocks CB1 to CBN is 0.65 mm ≦ WB ≦ 1.2 mm.

  Even if W1 = 0.4 mm and W2 = 0.2 mm, since 0.65 mm ≦ WB ≦ 1.2 mm, WB> W1 + W2 holds. When W1, WB, and W2 are the smallest values, W1 = 0.13 mm, WB = 0.65 mm, and W2 = 0.1 mm, and the width of the integrated circuit device is about W = 0.88 mm. Therefore, W = 0.88 mm <2 × WB = 1.3 mm holds. When W1, WB, and W2 are the largest values, W1 = 0.4 mm, WB = 1.2 mm, and W2 = 0.2 mm, and the width of the integrated circuit device is about W = 1.8 mm. Therefore, W = 1.8 mm <2 × WB = 2.4 mm holds. That is, W <2 × WB holds. If W <2 × WB is established in this way, a narrow integrated circuit device as shown in FIG. 2B can be realized.

5. Details of Memory Block and Data Driver Block 5.1 Block Division As shown in FIG. 17A, the display panel has VPN = 320 pixels in the vertical scanning direction (data line direction), and the horizontal scanning direction (scanning). Assume that the QVGA panel has HPN = 240 pixels in the line direction. Further, it is assumed that the bit number PDB of image (display) data for one pixel is 6 bits for each of R, G, and B, and PDB = 18 bits. In this case, the number of bits of image data necessary for displaying one frame of the display panel is VPN × HPN × PDB = 320 × 240 × 18 bits. Therefore, the memory of the integrated circuit device stores image data for at least 320 × 240 × 18 bits. Further, the data driver displays HPN = 240 data signals (data signals corresponding to 240 × 18 bits of image data) every horizontal scanning period (every period during which one scanning line is scanned). Output to the panel.

  In FIG. 17B, the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. The memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. Accordingly, each data driver block DB1 to DB4 outputs HPN / DBN = 240/4 = 60 data signals to the display panel every horizontal scanning period. Each of the memory blocks MB1 to MB4 stores (VPN × HPN × PDB) / MBN = (320 × 240 × 18) / 4 bits of image data. In FIG. 17B, the memory block MB1 and MB2 share the column address decoder CD12, and the memory block MB3 and MB4 share the column address decoder CD34.

5.2 Reading Multiple Times in One Horizontal Scan Period In FIG. 17B, each data driver block DB1 to DB4 outputs 60 data signals in one horizontal scan period. Therefore, it is necessary to read image data corresponding to 240 data signals for each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4.

  However, if the number of bits of image data to be read for each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the D2 direction. As a result, the width W in the direction D2 of the integrated circuit device is increased, and the slimming of the chip is prevented. In addition, the word line WL becomes long, which causes a problem of WL signal delay.

  Therefore, in the present embodiment, a method of reading image data stored in each of the memory blocks MB1 to MB4 from the memory blocks MB1 to MB4 a plurality of times (RN times) for each data driver block DB1 to DB4 in one horizontal scanning period. Is adopted.

  For example, in FIG. 18, as indicated by A1 and A2, the memory access signal MACS (word selection signal) becomes active (high level) only RN = 2 times in one horizontal scanning period. Thus, image data is read from each memory block to each data driver block RN = 2 times in one horizontal scanning period. Then, the data latch circuit included in the first and second data drivers DRa and DRb of FIG. 19 provided in the data driver block reads out the image based on the latch signals LATa and LATb indicated by A3 and A4. Latch data. A D / A conversion circuit included in the first and second data drivers DRa and DRb performs D / A conversion of the latched image data, and an output circuit included in DRa and DRb is obtained by D / A conversion. The data signals DATAa and DATAb are output to the data signal output lines as indicated by A5 and A6. Thereafter, as shown at A7, the scanning signal SCSEL inputted to the gate of the TFT of each pixel of the display panel becomes active, and the data signal is inputted and held in each pixel of the display panel.

  In FIG. 18, the image data is read twice in the first horizontal scanning period, and the data signals DATAa and DATAb are output to the data signal output line in the same first horizontal scanning period. However, the image data is read and latched twice in the first horizontal scanning period, and the data signals DATAa and DATAb corresponding to the latched image data are supplied to the data signal output lines in the next second horizontal scanning period. It may be output. Further, FIG. 18 shows the case where the number of times of reading RN = 2, but RN ≧ 3 may be possible.

  According to the method of FIG. 18, as shown in FIG. 19, image data corresponding to 30 data signals is read from each memory block, and each data driver DRa, DRb outputs 30 data signals. To do. As a result, 60 data signals are output from each data driver block. In this way, in FIG. 18, it is only necessary to read out image data corresponding to 30 data signals from each memory block in one reading. Therefore, the number of memory cells and sense amplifiers in the direction D2 in FIG. 19 can be reduced as compared with the method of reading only once in one horizontal scanning period. As a result, the width of the integrated circuit device in the D2 direction can be reduced, and an ultra slim slim chip as shown in FIG. 2B can be realized. In particular, the length of one horizontal scanning period is about 52 μsec in the case of QVGA. On the other hand, the memory read time is, for example, about 40 nsec, which is sufficiently shorter than 52 μsec. Therefore, even if the number of readings in one horizontal scanning period is increased from one to a plurality of times, the influence on the display characteristics is not so great.

  FIG. 17A shows a QVGA (320 × 240) display panel. If the number of readings in one horizontal scanning period is set to RN = 4, for example, the display panel corresponds to a VGA (640 × 480) display panel. It is also possible to increase the degree of design freedom.

  The plurality of readings in one horizontal scanning period may be realized by a first method in which a row address decoder (word line selection circuit) selects a plurality of different word lines in each memory block in one horizontal scanning period. Alternatively, the same word line in each memory block may be realized by a second method in which a row address decoder (word line selection circuit) selects a plurality of times in one horizontal scanning period. Alternatively, it may be realized by a combination of both the first and second methods.

5.3 Arrangement of Data Driver and Driver Cell FIG. 19 shows an arrangement example of the data driver and the driver cell included in the data driver. As shown in FIG. 19, the data driver block includes a plurality of data drivers DRa and DRb arranged in a stack along the direction D1. Each data driver DRa, DRb includes a plurality of 30 (Q in a broad sense) driver cells DRC1 to DRC30.

  When the word line WL1a of the memory block is selected and the first image data is read from the memory block as shown by A1 in FIG. 18, the first data driver DRa reads based on the latch signal LATa shown by A3. The output image data is latched. Then, D / A conversion of the latched image data is performed, and a data signal DATAa corresponding to the first read image data is output to the data signal output line as indicated by A5.

  On the other hand, when the word line WL1b of the memory block is selected and the second image data is read from the memory block as shown in A2 of FIG. 18, the second data driver DRb is based on the latch signal LATb shown in A4. The read image data is latched. Then, the latched image data is D / A converted, and a data signal DATAb corresponding to the second read image data is output to the data signal output line as indicated by A6.

  In this way, each data driver DRa, DRb outputs 30 data signals corresponding to 30 pixels, so that 60 data signals corresponding to 60 pixels in total are output. It becomes like this.

  As described above, the number Q of driver cells DRC1 to DRC30 arranged along the direction D2 can be expressed as Q = HPN / (DBN × IN). In the case of FIG. 19, since HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30. As described above, the number P of sense amplifiers arranged along the direction D2 in the sense amplifier block SAB can be expressed as P = (HPN × PDB) / (MBN × RN). In the case of FIG. 19, since HPN = 240, PDB = 18, MBN = 4, and RN = 2, P = (240 × 18) / (4 × 2) = 540.

5.4 Memory Cell FIG. 20A shows a configuration example of a memory cell (SRAM) included in the memory block. This memory cell includes transfer transistors TRA1 and TRA2, load transistors TRA3 and TRA4, and drive transistors TRA5 and TRA6. When the word line WL becomes active, the transfer transistors TRA1 and TRA2 are turned on, and image data can be written to the nodes NA1 and NA2 and image data can be read from the nodes NA1 and NA2. The written image data is held in the nodes NA1 and NA2 by a flip-flop circuit composed of transistors TRA3 to TRA6. Note that the memory cell of this embodiment is not limited to the configuration shown in FIG. 20A, and modifications such as using resistance elements as the load transistors TRA3 and TRA4 and adding other transistors are possible.

  20B and 20C show layout examples of memory cells. FIG. 20B shows a layout example of a horizontal cell, and FIG. 20C shows a layout example of a vertical cell. Here, as shown in FIG. 20B, the horizontal cell is a cell in which the word line WL is longer than the bit lines BL and XBL in each memory cell. On the other hand, as shown in FIG. 20C, the vertical cell is a cell in which the bit lines BL and XBL are longer than the word line WL in each memory cell. Note that WL in FIG. 20C is a local word line formed of a polysilicon layer and connected to the transfer transistors TRA1 and TRA2, but a metal layer word line for preventing signal delay of WL and stabilizing the potential. May be further provided.

  FIG. 21 shows an arrangement example of memory blocks and driver cells when the horizontal cell shown in FIG. 20B is used as the memory cell. FIG. 21 shows in detail a portion corresponding to one pixel in the driver cell and the memory block.

  As shown in FIG. 21, the driver cell DRC that receives image data for one pixel includes R, G, and B data latch circuits DLATR, DLATG, and DLATB. Each data latch circuit DLATR, DLATG, DLATB latches image data when a latch signal LAT (LATa, LATb) becomes active. The driver cell DRC includes the R, G, and B DACR, DACG, and DACB described with reference to FIG. The output unit SQ described with reference to FIGS. 10B and 10C is also included.

  The portion corresponding to one pixel in the sense amplifier block SAB includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. The bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR0 are connected to SAR0. In addition, the bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR1 are connected to the SAR1. The same applies to the relationship between other sense amplifiers and memory cells.

  When the word line WL1a is selected, image data is read from the memory cell MC to which the gate of the transfer transistor is connected to WL1a to the bit lines BL and XBL, and sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0. ... SAB5 performs signal amplification operation. DLATR latches 6-bit R image data D0R to D5R from SAR0 to SAR5, DACR performs D / A conversion of the latched image data, and output unit SQ outputs a data signal DATAR. . DLATG latches 6-bit G image data D0G to D5G from SAG0 to SAG5, DACG performs D / A conversion of the latched image data, and output unit SQ outputs a data signal DATAT. . DLATB latches 6-bit B image data D0B to D5B from SAB0 to SAB5, DACB performs D / A conversion of the latched image data, and output unit SQ outputs data signal DATAB. .

  In the case of the configuration shown in FIG. 21, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 18 as follows. That is, in the first horizontal scanning period (first scanning line selection period), first, the word line WL1a is selected to read the image data for the first time, and the first data is displayed as indicated by A5 in FIG. The signal DATAa is output. Next, in the same first horizontal scanning period, the word line WL1b is selected, the image data is read for the second time, and the second data signal DATAb is output as indicated by A6 in FIG. In the next second horizontal scanning period (second scanning line selection period), the word line WL2a is first selected to read the image data for the first time, and the first data signal DATAa is output. Next, in the same second horizontal scanning period, the word line WL2b is selected, the image data is read for the second time, and the second data signal DATAb is output. When horizontal cells are used in this way, a plurality of different word lines (WL1a, WL1b) in the memory block are selected in one horizontal scanning period, so that multiple readings in one horizontal scanning period can be realized.

  FIG. 22 shows an arrangement example of memory blocks and driver cells when the vertical cell shown in FIG. 20C is used as the memory cell. In the vertical cell, the width in the D2 direction can be made shorter than that in the horizontal cell. Therefore, the number of memory cells in the D2 direction can be doubled as compared with the horizontal cells. In the vertical cell, the column of memory cells connected to each sense amplifier is switched using column selection signals COLa and COLb.

  For example, in FIG. 22, when the column selection signal COLa becomes active, the memory cell MC on the column Ca side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. Is done. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. On the other hand, when the column selection signal COLb becomes active, the memory cell MC on the column Cb side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. The same applies to reading of image data of memory cells connected to other sense amplifiers.

  In the case of the configuration shown in FIG. 22, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 18 as follows. That is, in the first horizontal scanning period, first, the word line WL1 is selected, the column selection signal COLa is activated, the first reading of the image data is performed, and the first data signal is displayed as indicated by A5 in FIG. DATAa is output. Next, the same word line WL1 is selected in the same first horizontal scanning period, the column selection signal COLb is activated, and the second reading of the image data is performed. As shown in A6 of FIG. 18, the second data The signal DATAb is output. In the next second horizontal scanning period, the word line WL2 is selected, the column selection signal COLa is activated, the image data is read for the first time, and the first data signal DATAa is output. Next, the same word line WL2 is selected in the same second horizontal scanning period, the column selection signal COLb is activated, the image data is read a second time, and the second data signal DATAb is output. As described above, in the case of a vertical cell, the same word line in the memory block is selected a plurality of times in one horizontal scanning period, so that reading can be performed a plurality of times in one horizontal scanning period.

6). Electronic Device FIGS. 23A and 23B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic device may include components other than those shown in FIGS. 23A and 23B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  23A and 23B, the host device 410 is, for example, an MPU (Micro Processor Unit), a baseband engine (baseband processor), or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, an image processing controller (display controller) 420 in FIG. 23B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  The display panel 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. The display panel 400 can be constituted by an active matrix panel using switching elements such as TFTs and TFDs. Note that the display panel 400 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel.

  In the case of FIG. 23A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 23B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

7). Modification 7.1 Subpixel Driver Cell Arrangement FIG. 24 shows an arrangement example of subpixel driver cells. In FIG. 24, the data driver block includes a plurality of subpixel driver cells SDC1 to SDC180, each of which outputs a data signal corresponding to image data for one subpixel. That is, a plurality of subpixel driver cells are arranged along the D1 direction (a direction along the long side of the subpixel driver cell), and a plurality of subpixel driver cells are arranged along the D2 direction orthogonal to the D1 direction. . A data driver pad for electrically connecting the output line of the data driver block and the data line of the display panel is disposed on the D2 direction side of the data driver block. Data driver pads are also arranged on the D2 direction side of the memory block.

  For example, the driver cell DRC1 of the data driver DRa in FIG. 19 can be configured by the subpixel driver cells SDC1, SDC2, and SDC3 in FIG. Here, SDC1, SDC2, and SDC3 are subpixel driver cells for R (red), G (green), and B (blue), respectively, and R, G, and B corresponding to the first data signal. Image data (R1, G1, B1) is input from the memory block. The subpixel driver cells SDC1, SDC2, and SDC3 perform D / A conversion of these image data (R1, G1, and B1), and the first R, G, and B data signals (data voltages) are converted to the first data. Are output to the R, G, and B pads corresponding to the data lines.

  Similarly, the driver cell DRC2 includes R, G, and B subpixel driver cells SDC4, SDC5, and SDC6, and R, G, and B image data (R2, G2,. B2) is input from the memory block. Then, the subpixel driver cells SDC4, SDC5, and SDC6 perform D / A conversion of these image data (R2, G2, and B2), and the second R, G, and B data signals (data voltages) are the second. Are output to the R, G, and B pads corresponding to the data lines. The same applies to the other subpixel driver cells.

  Note that the number of subpixels is not limited to three, and may be four or more. Also, the arrangement of the subpixel driver cells is not limited to that shown in FIG. 24, and the R, G, and B subpixel driver cells may be stacked along the direction D2, for example.

7.2 Arrangement of Sense Amplifier and Memory Cell FIG. 25 shows an arrangement example of the sense amplifier and the memory cell. The portion corresponding to one pixel in the sense amplifier block includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. In FIG. 25, two (a plurality in a broad sense) sense amplifiers (and buffers) are stacked in the D1 direction. Of the two memory cell columns (vertical cells) arranged along the D1 direction on the D1 direction side of the stacked first and second sense amplifiers SAR0 and SAR1, the bit of the memory cell column in the upper row For example, the line is connected to the first sense-up SAR0, and the bit line of the memory cell column in the lower row is connected to the second sense amplifier SAR1, for example. Then, the first and second sense-up SAR0 and SAR1 perform signal amplification of the image data read from the memory cell, whereby 2-bit image data is output from SAR0 and SAR1. The same applies to the relationship between other sense amplifiers and memory cells.

  24 and 25, each of the driver cells includes a plurality of subpixel driver cells arranged along the direction D1 in the driver cell. Specifically, each of the driver cells includes subpixel driver cells for R, G, and B arranged along the direction D1. The portion corresponding to one pixel in the sense amplifier block included in the memory block includes R, G, and B sense amplifiers arranged along the direction D2.

  In the case of FIG. 25, readout of image data a plurality of times in one horizontal scanning period can be realized as follows. That is, in the first horizontal scanning period (first scanning line selection period), first, the word line WL1a is selected, the image data is read for the first time, and the first data signal DATAa is output. In this case, R, G, and B image data from the sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0 to SAB5 are input to the subpixel driver cells SDC1, SDC2, and SDC3, respectively. Next, in the same first horizontal scanning period, the word line WL1b is selected, the image data is read for the second time, and the second data signal DATAb is output. In this case, R, G, and B image data from the sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0 to SAB5 are input to the subpixel driver cells SDC91, SDC92, and SDC93, respectively.

7.3 Rearrangement Wiring Area In this embodiment, the rearrangement wiring area for rearranging the arrangement order of the output lines for the output signals of the subpixel driver cells (driver cells) is the subpixel driver (driver cell) arrangement area. Can be provided inside. In this way, switching of the wiring layer can be minimized, so that the width in the direction D2 of the wiring region between the data driver block and the pad can be reduced, and a slim and slender chip can be realized.

  For example, as indicated by E1 and E2 in FIG. 26, the output lines (data signals) of the output signals (data signals) of the subpixel driver cells are wired along the D2 direction (vertical direction), for example. These extraction lines are lines for extracting the output signal of the subpixel driver cell from the data driver block, and are formed by, for example, the fourth aluminum wiring layer ALD. In FIG. 26, pads P1, P2, P3,... For connecting the output lines of the subpixel driver cells and the data lines of the display panel are arranged on the D2 direction side of the data driver block and the memory block. .

  In FIG. 26, rearrangement wiring areas (first and second rearrangement wiring areas) for rearranging the arrangement order of these extraction lines are provided in the subpixel driver arrangement area. Specifically, the rearrangement wiring region is formed in a region above the first and second aluminum wiring layers ALA and ALB which are local lines in the subpixel driver cell. In this rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order corresponding to the arrangement order of the pads. Here, the order corresponding to the arrangement order of the pads may be the arrangement order of the pads themselves, or may be an order obtained by changing the arrangement order of the pads according to a predetermined rule. The rearrangement wiring area is a wiring area formed by extraction lines indicated by E1 and E2 and extraction position change lines E6 to E9 described later.

  For example, in FIG. 26, subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8... Whose cell number is not a multiple of 3 (in the broad sense, a multiple of J. J is an integer of 2 or more) The subpixel driver cells SDC3, SDC6, SDC9,... Belonging to one group and whose cell number is a multiple of 3 belong to the second group.

  The first group extraction line indicated by E1 is an output signal extraction line for the subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,... Belonging to the first group. The arrangement order of the extraction lines of the first group indicated by E1 is rearranged in the first rearrangement wiring area. Specifically, in the first rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order of the pads P1, P2, P4, P5, P7, P8. That is, the arrangement order of the extraction lines is rearranged in the arrangement order of the pads excluding the pad whose pad number is a multiple of 3. In this way, the output lines of the subpixel driver cells are extracted in the order of SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,... At the boundary (extraction port) on the D2 direction side of the data driver block. Are sorted and arranged.

  On the other hand, the extraction line of the second group indicated by E2 is an extraction line of output signals of the subpixel driver cells SDC3, SDC6, SDC9,... Belonging to the second group. The arrangement order of the second group extraction lines indicated by E2 is rearranged in the second rearrangement wiring region. Specifically, in the second rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order of the pads P3, P6, P9. That is, the arrangement order of the extraction lines is rearranged in the arrangement order of the pads whose pad number is a multiple of 3. In this way, the output lines of the output lines of the subpixel driver cells are rearranged in the order of SDC3, SDC6, SDC9,... At the boundary (extraction port) on the D2 direction side of the data driver block. Will come to be.

  Thus, if the rearrangement wiring area is provided in the subpixel driver and the arrangement order of the extraction lines is rearranged, the switching of the wiring layer in the area indicated by E3 which is the wiring area between the pad and the data driver block is minimized. Can be suppressed. As a result, the width WIT in the direction D2 of the wiring region indicated by E3 can be reduced, and a slim and slender chip can be realized.

  In the wiring area indicated by E3, the connection lines for connecting the first group extraction lines indicated by E1 and the pads P1, P2, P4, P5, P7, P8. Wiring is performed by three layers of aluminum wiring layers ALC (wires of a given layer in a broad sense). On the other hand, the connection line for connecting the second group lead-out line indicated by E2 and the pads P3, P6, P9..., As shown by E5, is the fourth aluminum wiring layer ALD (in a broad sense). Wired on a different layer than the given layer).

  For example, the connection line indicated by E4 is a line connecting the lead-out line from the subpixel driver cell SDC10 and the pad P10. On the other hand, the connection line indicated by E5 is a line connecting the lead-out line from the subpixel driver cell SDC9 and the pad P9. In this case, the connection line E4 is formed by the aluminum wiring layer ALC, and the connection line E5 is formed by the aluminum wiring layer ALD that is different from the ACL. Accordingly, it is not necessary to switch the wiring layer, and the E4 connection line and the E5 connection line can be overlapped in the E3 wiring region. As a result, the width WIT of the wiring region E3 in the direction D2 can be further reduced, and a slim and slender chip can be realized.

7.4 Extraction Position Change Line In this embodiment, extraction position change lines for changing the extraction positions of the extraction lines shown in E1 and E2 of FIG. 26 are wired in the rearrangement wiring area. For example, QCL1 and QCL2 indicated by E6 are extraction position change lines for changing the extraction positions of output signals (output lines) of the subpixel driver cells SDC1 and SDC2. Similarly, QCL4 and QCL5 indicated by E7 are take-out position change lines for SDC4 and SDC5, QCL7 and QCL8 indicated by E8 are take-out position change lines for SDC7 and SDC8, and QCL10 and QCL11 indicated by E9 are SDC10 and SDC11. It is an extraction position change line.

  Here, for example, as indicated by E6, the extraction position change lines QCL1 and QCL2 are wired in the D1 direction (lateral direction) across the plurality of subpixel driver cells SDC1 and SDC2 arranged along the D1 direction. That is, two take-out position change lines QCL1 and QCL2 are routed across the two subpixel driver cells SDC1 and SDC2 arranged along the direction D1. By doing so, it becomes possible to take out the output signals of the subpixel driver cells SDC1 and SDC2 from any position along the direction D1 of the first rearrangement wiring region using the takeout line.

  That is, the extraction position change lines QCL1 and QCL2 are wired by the third layer aluminum wiring layer ALC. Therefore, if vias of ALC and ALD are formed at arbitrary positions of the extraction position change lines QCL1 and QCL2 wired along the direction D1, the extraction line formed by ALD is moved from the via formation position to the direction D2. Can be wired. As a result, the extraction line can be wired in the D2 direction from an arbitrary extraction position in the D1 direction, and the arrangement order of the extraction lines can be easily rearranged.

  FIG. 27A shows an example of how each aluminum wiring layer is used. For example, the first aluminum wiring layer ALA wired in the vertical or horizontal direction is used as a source / drain / gate connection line of a transistor in a circuit block. The second aluminum wiring layer ALB mainly wired in the vertical direction is used as a power supply line, a signal line, a gradation voltage supply line, or the like. The third aluminum wiring layer ALC that is mainly wired in the horizontal direction is used as an extraction position change line for a data driver, an image data supply line for a memory, and the like. The fourth aluminum wiring layer ALD mainly wired in the vertical direction is used as a data driver lead-out line, a gradation voltage supply line, and the like. Further, the fifth aluminum wiring layer ALE, which is a top metal wired mainly in the horizontal direction, is used as a global line or the like for wiring between non-adjacent circuit blocks.

  FIG. 27B shows a layout example of the aluminum wiring layer ALC wired in the subpixel driver cell. In FIG. 27B, the take-out position change line and the DAC drive line are wired along the D1 direction (lateral direction) by the thick aluminum wiring layer ALC. Further, for example, 18 image data supply lines corresponding to one pixel are wired along the direction D1 by the aluminum wiring layer ALC. As described above, in the subpixel driver cell, a large number of image data supply lines and extraction position change lines indicated by E6 in FIG. 26 are wired by the same aluminum wiring layer ALC.

  In the present embodiment, the gradation voltage supply line for supplying the gradation voltage to the D / A converter DAC of the subpixel driver cell is wired along the D2 direction across the plurality of subpixel driver cells. . Specifically, the gradation voltage supply line is wired by effectively utilizing the empty area where the extraction line is not arranged by the aluminum wiring layer ALD of the same layer as the extraction line.

  Thus, in the present embodiment, the take-out position change line and the image data supply line along the D1 (lateral) direction are wired by the aluminum wiring layer ALC. On the other hand, the lead-out line and the gradation voltage supply line along the D2 (vertical) direction are wired by an aluminum wiring layer ALD which is a layer different from the ALC. In this way, the extraction position change line, the image data supply line, the extraction line, and the gradation voltage supply line can be efficiently wired using the two aluminum wiring layers ALC and ALD. Therefore, it is not necessary to use an aluminum wiring layer of another layer such as ALE, and ALE can be used for a global line or the like, so that the wiring efficiency can be improved and a slim and slender chip can be realized.

  In the present embodiment, a rearrangement wiring region is provided in the region of the output portion SSQ of the subpixel driver cell. For example, as shown in FIG. 26, the first rearrangement wiring region is provided in the region of the output part SSQ of the subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,. The second rearrangement wiring region is provided in the region of the output portion SSQ of the second group of subpixel driver cells SDC3, SDC6, SDC9,. In this way, rearrangement of the arrangement order of the extraction lines can be realized by effectively utilizing the area of the output part SSQ of the subpixel driver cell. That is, as shown in E1 and E2 of FIG. 26, if the extraction line is wired in the output portion SSQ area and the SSQ area is set as the rearrangement wiring area, the gradation voltage supply line is connected to the DAC area on both sides of the SSQ. Can be wired. Accordingly, the lead-out line and the gradation voltage supply line can be wired by the same aluminum wiring layer ALD, and the wiring efficiency can be improved.

7.5 Subpixel Driver Cell Layout FIG. 28 shows a detailed layout example of a subpixel driver cell. As shown in FIG. 28, each of the subpixel driver cells SDC1 to SDC180 includes a latch circuit LAT, a level shifter L / S, a D / A converter DAC, and an output unit SSQ. Note that another logic circuit such as an FRC (Frame Rate Control) circuit for gradation control may be provided between the latch circuit LAT and the level shifter L / S.

  A latch circuit LAT included in each subpixel driver cell latches 6-bit image data corresponding to one subpixel from the memory block MB1. The level shifter L / S converts the voltage level of the 6-bit image data signal from the latch circuit LAT. The D / A converter DAC performs D / A conversion of 6-bit image data using the gradation voltage. The output unit SSQ includes an operational amplifier OP (voltage follower connection) that performs impedance conversion of the output signal of the D / A converter DAC, and drives one data line corresponding to one subpixel. In addition to the operational amplifier OP, the output unit SSQ can include transistors for discharge, 8-color display, and DAC drive (switch elements).

  As shown in FIG. 28, each subpixel driver cell (first and second data drivers DRa and DRb) operates with a power supply having a voltage level of LV (Low Voltage) (first voltage level in a broad sense). A circuit that operates with a power supply of an LV region (first circuit region in a broad sense) in which a circuit is disposed and a voltage level (second voltage level in a broad sense) of MV (Middle Voltage) higher than LV is disposed. MV region (second circuit region in a broad sense). Here, LV is an operating voltage of the logic circuit block LB, the memory block MB, and the like. MV is an operating voltage of a D / A converter, an operational amplifier, a power supply circuit, and the like. Note that an output transistor of the scan driver is supplied with power at an HV (High Voltage) voltage level (third voltage level in a broad sense) to drive the scan line.

  For example, a latch circuit LAT (or other logic circuit) is arranged in the LV region (first circuit region) of the subpixel driver cell. In the MV region (second circuit region), a D / A converter DAC and an output unit SSQ having an operational amplifier OP are arranged. The level shifter L / S converts the LV voltage level signal into an MV voltage level signal.

  In FIG. 28, a buffer circuit BF1 (peripheral circuit portion) is provided on the D4 direction side of the subpixel driver cells SDC1 to SDC180. The buffer circuit BF1 buffers the driver control signal from the logic circuit block LB and outputs it to the subpixel driver cells SDC1 to SDC180. In other words, it functions as a repeater block for driver control signals.

  Specifically, the buffer circuit BF1 includes an LV buffer arranged in the LV area and an MV buffer arranged in the MV area. The LV buffer receives and buffers a driver control signal (such as a latch signal) having a voltage level of LV from the logic circuit block LB, and buffers the LV buffer in the LV region of the sub-pixel driver cell arranged on the D2 direction side (LAT). ). Also, the MV buffer receives a driver control signal (DAC control signal, output control signal, etc.) of the LV voltage level from the logic circuit block LB, converts it to the MV voltage level by the level shifter, and buffers it. Are output to the circuits (DAC, SSQ) in the MV region of the subpixel driver cells arranged in (1).

  In this embodiment, as shown in FIG. 28, the subpixel driver cells SDC1 to SDC180 are arranged so that the MV regions (or LV regions) of the subpixel driver cells are adjacent to each other along the D1 direction. That is, adjacent subpixel driver cells are mirror-arranged with an adjacent boundary along the direction D2. For example, the subpixel driver cells SDC1 and SDC2 are arranged so that the MV regions are adjacent to each other. The subpixel driver cells SDC3 and SDC91 are also arranged so that the MV regions are adjacent to each other. The subpixel driver cells SDC2 and SDC3 are arranged so that the LV regions are adjacent to each other.

  If the MV regions are arranged adjacent to each other as shown in FIG. 28, it is not necessary to provide a guard ring or the like between the subpixel driver cells. Therefore, the width of the data driver block in the direction D1 can be reduced compared with the method in which the MV region and the LV region are adjacent to each other, and the area of the integrated circuit device can be reduced.

  In addition, according to the arrangement method of FIG. 28, the MV region of the adjacent subpixel driver cell (driver cell) can be effectively used as the wiring region of the output line for the output signal of the subpixel driver cell (driver cell), and the layout efficiency can be improved. Can be improved.

  As shown in FIGS. 24 and 28, in the present embodiment, the first and second data drivers DRa and DRb are arranged so that their MV regions (second circuit regions) are adjacent to each other. The LV region (first circuit region) of the first data driver DRa is adjacent to the first memory block MB1 and the Jth memory block MB1, and the LV region (first circuit region) of the second data driver DRb. Are arranged adjacent to the second memory block MB2 (the J + 1th memory block). For example, in FIGS. 24 and 28, the first memory block MB1 is arranged adjacent to the LV region of the subpixel driver cells SDC1, SDC4, SDC7... SDC88 of the first data driver DRa. The second memory block MB2 is arranged adjacent to the LV region of the subpixel driver cells SDC93, SDC96, SDC99... SDC180 of the second data driver DRb. The memory blocks MB1 and MB2 operate with a power supply having a voltage level of LV. Therefore, if the LV region of the subpixel driver cell is arranged adjacent to the memory block in this way, the width of the driver macrocell constituted by the data driver block and the memory block in the direction D1 can be reduced, and the integrated circuit device can be reduced. The area can be increased.

7.6 D / A Converter FIG. 29 shows a detailed configuration example of the D / A converter (DAC) included in the subpixel driver cell. This D / A converter is a circuit that performs so-called tournament D / A conversion, and includes gradation voltage selectors SLN1 to SLN11, SLP1 to SLP11, and a predecoder 120.

  Here, the gradation voltage selectors SLN1 to SLN11 are selectors formed of N-type (first conductivity type in a broad sense) transistors, and the gradation voltage selectors SLP1 to SLP11 are P-type (second conductivity type in a broad sense). These N-type and P-type transistors are paired to form a transfer gate. For example, an N-type transistor constituting SLN1 and a P-type transistor constituting SLP1 are paired to constitute a transfer gate.

  The input terminals of the gradation voltage selectors SLN1 to SLN8 and SLP1 to SLP8 are V0 to V3, V4 to V7, V8 to V11, V12 to V15, V16 to V19, V20 to V23, V24 to V27, V28 to V31, respectively. Grayscale voltage supply lines are connected. The predecoder 120 receives the image data D0 to D5 and performs a decoding process as shown in the truth table of FIG. The selection signals S1 to S4 and XS1 to XS4 are output to the gradation voltage selectors SLN1 to SLN8 and SLP1 to SLP9, respectively. The selection signals S5 to S8 and XS5 to XS8 are output to SLN9 and SLN10, SLP9 and SLP10, respectively, and S9 to S12 and XS9 to XS12 are output to SLN11 and SLP11, respectively.

  For example, when the image data D0 to D5 is (100000), the selection signals S2, S5, and S9 (XS2, XS5, and XS9) become active as shown in the truth table of FIG. Thus, the gradation voltage selectors SLN1 and SLP1 select the gradation voltage V1, SLN9 and SLP9 select the outputs of SLN1 and SLP1, and SLN11 and SLP11 select the outputs of SLN9 and SLP9. Therefore, the gradation voltage V1 is output to the output unit SSQ. Similarly, when the image data D0 to D5 are (010000), the selection signal S3 (XS3) becomes active, so that the gradation voltage selectors SLN1 and SLP1 select the gradation voltage V2, and the output unit SSQ has a level. A regulated voltage V2 is output. When the image data D0 to D5 are (001000), the selection signals S1, S6, S9 (XS1, XS6, XS9) are activated. Therefore, the gradation voltage selectors SLN2 and SLP2 select the gradation voltage V4, SLN9 and SLP9 select the outputs of SLN2 and SLP2, and SLN11 and SLP11 select the outputs of SLN9 and SLP9. Therefore, the gradation voltage V4 is output to the output unit SSQ.

  In this embodiment, as shown in FIGS. 30B and 30C, the gradation voltage supply line for supplying the gradation voltages V0 to V31 to the D / A converter of FIG. 29 includes a plurality of subpixel drivers. Wiring is performed along the D2 (D4) direction across the cells. For example, in FIG. 30B, the gradation voltage supply line is wired in the D2 direction across the subpixel driver cells SDC1, SDC4, and SDC7 arranged in the D2 direction. Further, these gradation voltage supply lines are wired on the arrangement area of the D / A converter (gradation voltage selector) as shown in FIGS.

  More specifically, as shown in FIG. 30B, in the D / A converter arrangement region of the sub-pixel driver cell, an N-type transistor region (P-type well), a P-type transistor region ( N-type well) is arranged. On the other hand, in the arrangement region of circuits (output unit, level shifter, latch circuit) other than the D / A converter of the subpixel driver cell, an N-type transistor region (P-type well), P along the D1 direction orthogonal to the D2 direction. A type transistor region (N type well) is disposed. In other words, the subpixel driver cells adjacent along the D2 direction are mirror-arranged with an adjacent boundary along the D1 direction. For example, the driver cells SDC1 and SDC4 are mirror-arranged with the adjacent boundary therebetween, and SDC4 and SDC7 are mirror-arranged with the adjacent boundary interposed therebetween.

  For example, the N-type transistors constituting the gradation voltage selectors SLN1 to SLN11 of the D / A converter of the subpixel driver cell SDC1 are formed in the N-type transistor region NTR1 of the subpixel driver cell shown in FIG. P-type transistors constituting the voltage regulator selectors SLP1 to SLP11 are formed in the P-type transistor region PTR1. Specifically, as shown in FIG. 30C, the N-type transistors TRF1 and TRF2 constituting the gradation voltage selector SLN11 and the N-type transistors TRF3 and TRF4 constituting the gradation voltage selectors SLN9 and SLN10 are N-type. It is formed in transistor region NTR1. On the other hand, the P-type transistors TRF5 and TRF6 constituting the gradation voltage selector SLP11 and the P-type transistors TRF7 and TRF8 constituting the gradation voltage selectors SLP9 and SLP10 are formed in the P-type transistor region PTR1. The N-type transistor region and the P-type transistor region of other circuits of the subpixel driver cell are arranged along the direction D1, whereas the N-type transistor region NTR1 and the P-type transistor region PTR1 are arranged along the direction D2. Arranged.

  In the D / A converter of FIG. 29, for example, an N-type transistor constituting the gradation voltage selector SLN1 and a P-type transistor constituting the gradation voltage selector SLP1 form a pair to form a transfer gate. Therefore, if the gradation voltage supply line is wired along the D2 direction, the gradation voltage supply line can be commonly connected to these P-type and N-type transistors, and the transfer gate can be easily configured, and the layout can be realized. Efficiency can be improved.

  On the other hand, it is necessary to input image data from a memory block to a circuit other than the D / A converter, for example, a latch circuit. Then, as shown in FIG. 30B, this image data is supplied by an image data supply line wired along the direction D1. As is clear from the layout of FIG. 28, the direction of signal flow in the subpixel driver cell is the D1 direction. Therefore, if the N-type transistor region and the P-type transistor region of the circuit other than the D / A converter are arranged along the D1 direction as shown in FIG. 30B, an efficient layout along the signal flow is possible. become. Therefore, the arrangement of the transistor regions as shown in FIG. 30B is an optimal layout for the subpixel driver cells arranged as shown in FIG.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input-side I / F) described at least once together with different terms having a broader meaning or the same meaning (first interface region, second interface region, etc.) (Area, etc.) can be replaced with the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

CB1 to CBN 1st to Nth circuit blocks, 10 integrated circuit devices,
12 output side I / F area, 14 input side I / F area, 20 memory,
22 memory cell array, 24 row address decoder,
26 column address decoder, 28 write / read circuit,
40 logic circuit, 42 control circuit, 44 display timing control circuit,
46 host interface circuit, 48 RGB interface circuit,
50 data drivers, 52 data latch circuits, 54 D / A conversion circuits,
56 output circuit, 70 scan driver, 72 shift register,
73 scanning address generation circuit, 74 address decoder, 76 level shifter,
78 output circuit, 90 power supply circuit, 92 booster circuit, 94 regulator circuit, 96 VCOM generation circuit, 98 control circuit, 110 gradation voltage generation circuit,
112 selection voltage generation circuit, 114 gradation voltage selection circuit, 116 adjustment register

Claims (23)

The direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is defined as the first direction, and the second side, which is the long side of the integrated circuit device, is directed to the fourth side facing the first side. The first direction to the Nth circuit block (N is an integer of 2 or more) arranged along the first direction,
A first interface region provided along the fourth side on the second direction side of the first to Nth circuit blocks;
A second interface region provided along the second side on the fourth direction side of the first to Nth circuit blocks when a direction opposite to the second direction is a fourth direction. and,
Global wiring for wiring between non-adjacent circuit blocks among the first to Nth circuit blocks;
Including
The first to Nth circuit blocks are:
Including at least one data driver block and a logic circuit block for driving the data lines;
When the widths of the first interface region, the first to Nth circuit blocks, and the second interface region in the second direction are W1, WB, and W2, respectively, width W in the second direction, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 der is,
An integrated circuit device, wherein a logic signal from the logic circuit block is supplied to the global wiring. In claim 1,
The first interface region is arranged on the second direction side of the data driver block without passing through other circuit blocks,
The integrated circuit device, wherein the second interface region is arranged on the fourth direction side of the data driver block without passing through another circuit block. In claim 1 or 2,
  The first to Nth circuit blocks are:
An integrated circuit device comprising: first to fourth data driver blocks arranged along the first direction as the at least one data driver block. In any one of Claims 1 thru | or 3,
  The integrated circuit device, wherein the logic circuit block is a circuit that generates a control signal for controlling display timing. In any one of Claims 1 thru | or 4,
An integrated circuit device, wherein a logic signal line from the logic circuit block is formed by the global wiring above the local wiring that is a wiring in the circuit block. In any one of Claims 1 thru | or 5,
  The integrated circuit device, wherein the first interface region is provided with a pad having a plurality of stages in the second direction. In any one of Claims 1 thru | or 6.
  The integrated circuit device, wherein the first interface region includes a pad and a circuit element disposed under the pad. In any one of Claims 1 thru | or 7,
  An integrated circuit device characterized in that SP> 10 when the length in the long side direction of the integrated circuit device is LD and the chip shape ratio is SP = LD / W. In any one of Claims 1 thru | or 8.
  The data driver block is:
  An integrated circuit device comprising Q driver cells, each of which outputs a data signal corresponding to image data for one pixel and is arranged along the second direction. In claim 9 ,
The width in the second direction prior SL driver cells and WD, the width in the second direction in the peripheral circuit portion in which the data driver block includes the case of a WPCB, the circuit blocks of the first to N The width WB in the second direction is Q × WD ≦ WB <(Q + 1) × WD + WPCB. In claim 9 or 10 ,
When the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and the number of input times of image data input to the driver cell in one horizontal scanning period is IN,
The number Q of the driver cells arranged along the second direction is Q = HPN / (DBN × IN). In any of claims 9 to 11,
  A gradation voltage generating circuit for generating a gradation voltage;
  Each of the driver cells is
  An integrated circuit device comprising: a D / A converter that performs D / A conversion of image data using the gradation voltage from the gradation voltage generation circuit. In claim 12,
  An integrated circuit device, wherein a grayscale voltage signal line for supplying the grayscale voltage to the driver cell is formed by a global wiring in an upper layer than a local wiring that is a wiring in a circuit block. In claim 12 or 13,
  Each of the driver cells is
  A data latch circuit for latching the image data;
  An output circuit for buffering the data voltage from the D / A converter and outputting it to the data line;
  The D / A converter is
An integrated circuit device, wherein a voltage corresponding to the image data is selected from a plurality of gradation voltages from the gradation voltage generation circuit and is output as the data voltage. In claim 14,
  The integrated circuit device, wherein the data latch circuit, the D / A converter, and the output circuit are arranged along the first direction. In claim 14,
  The integrated circuit device, wherein the data latch circuit, the D / A converter, and the output circuit are arranged along the second direction. In any of claims 9 to 16 ,
Each of the previous SL driver cell,
An integrated circuit device comprising: a plurality of subpixel driver cells, each of which outputs a data signal corresponding to image data for one subpixel, and is arranged in the driver cell along the first direction. In claim 17 ,
An integrated circuit device, wherein a rearrangement wiring region for rearranging an arrangement order of output signal take-out lines of the subpixel driver cells is provided in an arrangement region of the subpixel driver cells. In any one of Claims 1 thru | or 18 .
The first to Nth circuit blocks are:
An integrated circuit device comprising at least one memory block for storing image data. In claim 19 ,
The first interface region is arranged on the second direction side of the memory block without passing through another circuit block,
The integrated circuit device, wherein the second interface region is arranged on the fourth direction side of the memory block without passing through another circuit block. In claim 19 or 20 ,
An integrated circuit device, wherein the image data stored in the memory block is read a plurality of times in one horizontal scanning period from the memory block to the adjacent data driver block. Any one of claims 1 to 21
The integrated circuit device, wherein the width W of the integrated circuit device in the second direction is W <2 × WB. An integrated circuit device according to any one of claims 1 to 22 ,
A display panel driven by the integrated circuit device;
An electronic device comprising:

Images