TWI306305B - Method for identifying defective substrate - Google Patents

Method for identifying defective substrate Download PDF

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Publication number
TWI306305B
TWI306305B TW095132127A TW95132127A TWI306305B TW I306305 B TWI306305 B TW I306305B TW 095132127 A TW095132127 A TW 095132127A TW 95132127 A TW95132127 A TW 95132127A TW I306305 B TWI306305 B TW I306305B
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TW
Taiwan
Prior art keywords
substrate
substrate unit
wafer
layer
opening portion
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TW095132127A
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Chinese (zh)
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TW200812047A (en
Inventor
En Li Lin
Chun Ter Su
Pei Cheng Huang
Kaun I Cheng
Kun Ming Huang
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Siliconware Precision Industries Co Ltd
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Priority to TW095132127A priority Critical patent/TWI306305B/en
Publication of TW200812047A publication Critical patent/TW200812047A/en
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Publication of TWI306305B publication Critical patent/TWI306305B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Description

1306305 九、發明說明: 【發明所屬之技術領域】 本發明係有關-種劣品辨識技術,更 關於-種辨識劣品基板之方法。 平而。之係有 【先前技術】 在半導體封裝件製程中,用於承财導體晶片之基板 結構’除以單顆方式進行晶片之料製裎外,為 數其::…及降低成本,一般係以條狀⑽p)方式將複 曰連結—起以構成—㈣板,以便同時進行複數 日日片之封裝作業,就基板片而言,每一片基板片包含有數 個基板早7^,同時,通常於該基板片上進行上片(Die ::=、銲線(WireB,^ 二IS:,等封震作業❿ ^力此疋否正常’以便由機台自動檢知損壞基板單元之所 立置’使封裝作業能跳過該損壞基板單元。如此,可省 ,略對該損壞基板單元進行封裝作業所花費之材料成本,更 可避免晶片黏接至損壞基板單元上形成不良品。 m2,廠^作中發現基板不良品時,通常會配合 料廠要求,以人工方式在損壞的基板單元上塗佈油墨 =標記⑽仙g),以免晶片黏接至損壞基板單元 t成不良品。而傳統的標記方法,係先利用光學檢測或 外减檢查專方式在基板片上逐—檢視基板單元,當發現基 板片上出現損壞基板單元時,於該損壞基板單元封裝線土 Line)外之邊條簡單地註記上不良品』 19259 5 1306305 Π 有損壞基板單元之基板片置入-油墨標記機, 上:由::印刷技術(Screen Printing)在該損壞基板單元 你…二、Ί進行烘烤(Curing )及清洗作業(Cleaning), 件形、於抽壞基板單元置晶區外側之光學辨識基準點 (FuhicialMwk)可為該油墨所遮覆。 惟’此種油墨塗佈作業會增加封裝的製程及成本,易 使標記油墨在、坤钱·卩r . . w 〇Β …… g)期間因為油墨溶劑之蒸發產 揮乳體釋散(即釋氣現象(Outgasing))而污染至其 他正常基板單元。而且’當進行模壓製程(Molding)時, 基板片夹置於上下模具之間,模具產生之高溫亦容易造成 油墨軟化而導致標記處之油墨沾染到模具表面,使得模壓 完成後,原標註在損壞基板單元之標記處不易判讀,而需 要再次以人工重複標記而增加成本 #於前述問題,台灣發明專利2498〇1號案中揭示出 —種辨識劣σσ基板之方法,主要係以雷射燒灼劣品基板單 元表面上之光學辨識基準點(FidudalMark),使機台之 影像檢視系統(例如CCD攝影機)找不到該 ^ 準點,而自動檢知該基板單元為劣品。 土 惟,以雷射燒灼技術去除該光學辨識基準點時,所燒 灼之區域必須涵蓋該光學辨識基準點,而由於目前電射^ 小功率下其切割深度至少丨0.26mm,目此會挖開該光學 辨識基準點周圍之基板部分。是以,當基板厚度因半導體 封裝體高度需求而降至〇.26mm以下時(例如目前已有 .136mm之產σσ ),應用此專利技術進行燒灼時會貫穿基 19259 6 1306305 板而形成通孔。如第4圖所示, 射燒灼技術燒灼靠近㈣線(如 使用現行之雷 點以形成雷射標記所™辨識基準 基板在進行模壓作業時,劣品基板單元與良 進細,如第5圖所示,樹㈣在進 二':!:將容易從前述雷射燒灼損害基板單元31,所 而流至該基板30背面。而且,由於劣品 :早L、良品基板單元相距甚近,流至該基板%背面之 L脂很ΐ易污㈣良品基板單元的锡球銲塾5〇 (歸 a使得為良品之基板單元受到影響。 =外’由於基板線路(Layom)設計之限制,約有糾 支法設置光學辨識基準點,致無法使用雷射燒灼 =:该光學辨識基準點以形成雷射標記,故亦限制此 專利技術之應用領域。 ^外’由於光學_基準點係設於#近基板單元間之 刀剔邊界’因此在進行雷射燒灼㈣成雷射標記時,易造 成燒灼至良品基板單元及煙薰以基板單元問題。因此, 如何開發m於有效辨識劣品基板之際,可避免上述雷 射燒灼技術所造成之不良,亦無傳統油墨污染問題,進而 解決習知技術之缺點,為當今亟待思考之課題。 【發明内容】 點,本發明之一目的在於 而毋須燒灼其光學辨識基 鑒於以上所述習知技術之缺 提供一種辨識劣品基板之方法, 準點。 19259 7 1306305 , 本發明之再一目的為提供一種辨識劣品基板之方 法’可避免雷射燒灼劣品基板單元之光學辨識基準點形成 貫穿基板之通孔,甚而導致後續封㈣屢作㈣,封㈣ 脂溢流至良品基板單元銲球墊所造成之污染問題。 本發明之又-目的為提供一種辨識劣品基板之方 法’可避免雷射燒灼光學辨識基準點時,容易燒灼到良品 基板單元及煙薰良品基板單元等問題。 本發明之另一目的為提供一種辨識劣品基板之方 法,可避免使用油墨標記而污染良品基板單元問題。 為達^上揭及其他目的,本發明提供一種辨識劣品基板 、方法η亥方法之步驟係包括:提供一由多數基板單元構 成之基板片,該基板片包含有至少一損壞基板單元,且各 基板單元表面覆蓋有絕緣層;以及於該損壞基板單元之絕 緣層形成開窗部’俾由該開窗部供辨識該出損壞基板單元。 於-較佳實施態樣中,該基板單元中央具有晶片接置 =(如Pad),且該開窗部係形成於該晶片接縣。該絕緣 :下係元成有金屬層,且該開窗部係外露出該金屬層。較 4地,該金屬層係為銅層。 7另一實施態樣中,該基板單元具有晶片接置區以外 ::片接置區’且該開窗部係形成於該非晶片接置區。 ^曰曰片接置區係形成有接地銲塾,且該開 垓接地銲墊。 可^返辨識劣品基板之方法中,形成該開窗部之方法係 ^以雷射進行之,且該絕緣層係可為例如拒銲劑層 19259 8 1306305 (solder mask)。 r 由於本發明所提供辨識劣品基板之方法係於基板片 之、、邑緣層開„又開_部’遠開窗部可外露出絕緣層下之金屬 層或接地銲塾,由該金屬層或接地銲塾吸收形成該開窗部 之雷射熱量及反射雷射光線,故不會燒穿基板,而可解決 習知辨別劣品基板時使用雷射燒灼用於定位之光學辨識基 準點所造成之種種問題。同時,應用本發明可避開基板線 路,故亦可避免習知技術僅能應用於有限裝置之缺失。 是以’相較於習知技術而言’本發明可於有效辨識劣 品基板之際而不會貫穿基板,且不須燒灼該光學辨識基準 點。另由於本發明之辨識點遠離基板單元間之切割 1 文不會造成燒焦良品基板單元或煙薰良品基板單元,同時 由墨標記而污染良品基板單元問題,進而提 =業利用價值’相對已克服先前技術所存在之缺失。 【實施方式】 =明之辨識劣品基板方法係發現基板片上出現損 1早70時’於基板片投入封裝作業前實施之,以便於 封裝作業壞基板單元的所在位置,使: 線作業能跳過該損壞基板單元而不會浪 寸 實施例配合所附圖式詳細說明本發明辨識二= 各項實施步驟。 力口暴板方法的 第一實施例 請參閱第1及第2圖,係顯示本發 方法的整體流程示意圖。 辨識另扣基板之 19259 9 1306305 l 貝施例中辨識劣品基板之方法係先提供基板片 個基板土單η1上以切割線1 〇 ( CUUing Line)劃分出複數 ' 70 ,且该等基板單元11中至少包含有一或多 個損壞基板單元11,。 一 本實施例之每一基板單元11分別具有-第-表面及 • 一相對之第二表面(未圖示),各基板單元之第一表面形 成有諸如銅層之金屬層(未圖示)並覆蓋有如拒銲劑層 (s〇iderMask)之絕緣層114,且該基板單元”之大致中 央處定義有晶片接置區112。各基板單元u靠近角端位置 •附近則可設有至少一可供上片機台與銲線機台定位辨識之 光學辨識基準點Π3 (FiducialMark)。當然,於其他實 靶例例中亦可應用設有其他基板單元數量之基板片,而非 偈限於本實施例之圖式所示者。而且,由於基板片之結構 與製法均屬習知者,故於此不再為文贅述。 接著,於該損壞基板單元之絕緣層丨14形成開窗部, '•俾由該開窗部供辨識該出損壞基板單元。於本實施例中, 當發現該基板片1中有損壞基板單元1Γ時,如第2圖所 示,係以例如二氧化碳雷射或uv雷射燒灼該損壞基板單 元11’的晶片接置區Π2之部分絕緣層ι14以形成開窗部 Π5 ’於該開窗部115則外露出該絕緣層114下之金屬層 116(如放大之剖面示意圖所示)。由於該金屬層116可為例 如鍺紅色之銅層’故可與該絕緣層114明顯區別。 同時,由於該金屬層116可吸收雷射之熱量,且雷射 之光線可由該金屬層116予以反射,故於形成該開窗部j i 5 ίο 19259 1306305 保護基板,而不致燒穿該基板片1。此外,雖本實施 形成例如矩形之開窗部115,但所屬技術領域中具 匕ί知識者可加以變化與修改,而非以此為限。 先以來’當上片機台(未圖示)黏接晶片之前便可 > 口之衫像檢視系統來檢視該開窗部115,以辨識出 ^莫^板單(U ’且可由該影像檢視系統檢視該光學辨 !:準點:13’以決定晶片上片位置。例如,可將機台設 躍模式(Sklp),將機台之影像檢視系統檢視到該 “ =5之損縣板單元跳過諸如^上片及打線等製 =意的是,以機台之影像檢㈣_識基板單元之 技術與作用原理係屬習知者,故於此不再多作說明。 劣σ習^技術’本實施例之方法係直接以雷射燒灼 :土板早凡诸如拒銲劑層之絕緣層,同時藉由該絕緣層 ::如銅層之金屬層可保護基板不被雷射貫穿,進而避免 穿過該!射之貫穿通孔而污染良品基板單元 ^ ,應用本之方法不卿除光學辨識基準 可避免習知技術中因光學辨識基準點與基板切割 邊界接近,容易燒到良品基板單元及煙黨良品基板單元等 問題。因此,本發明辨識劣品基板單元之方法於有效辨識 =基==貫穿基板,且不須燒灼該光學辨識基 ^ rr 同時亦可避免使用油墨 在之各項缺失。 相對已解決先爾所存 第二實施例 19259 11 I3〇63〇5 睛參閱第3圖,係為本發明辨識劣 二實施例之示意圖,與第一實施例相同或近似之元件係: ^或近似之元件符號表示,並省略詳細之敘述,以使本 木之說明更清楚易懂 、本發明之第二實施例與第一實施例最大不同之處在 於:第-實施例係於晶片接置區形成開窗部,第二實施例 則係於非晶片接置區形成該開窗部。 本實施例係於該晶片接置區112以外之非晶片接置區 1士17形成該開窗部115,。於本實施射,射於設計基板 日守預設例如無電性魏Μ料或接地料ιΐ8於非晶片 接置區117。當發現該基板片2中有損壞基板料u,時, 係於該非晶片接置區117具有無電性功能之空銲塾或接地 鲜塾118之部分形成開窗部⑴,,以於該開窗冑115,外露 出該絕緣層114下之無電性功能之空銲塾或接地焊墊 ns;當基板單元&良品時,則可由該絕緣@ ιΐ4遮蓋其下 之無電性功能之空銲墊或接地銲墊118。 /、 當然,雖本實施例中於該晶片接置區ii2右下角之非 晶片接置區117形成該開窗部115’’但該開窗部ιΐ5,亦可 形成於其他位置之非晶片接置區117中。 如此-來’便可於黏接晶片之前先由機台之影像檢視 系統檢視基板單元是否具有該開窗部115,,以辨識出該損 壞基板單元1Γ。而且,關窗部115,料露出紗電性貝 功能之空銲塾或接地銲塾118,故不會產生電性及信賴性 19259 12 !3〇63〇5 « *或非=不論該開窗部115,115,設於前述晶片接置區112 解=彡置區117 ’均毋須考量基板線路之設計,故可 技術受限於基板線路而無法使用雷射燒灼技術燒 大::辨識基準點以形成雷射標記之問題,故亦相對擴 大本發明之應用領域。 八 U上所述之具體實施例,僅係用以例釋 =揭而非用以限定ί發明之可實施範缚’在二 鲁6 -之精神與技術祀4下’任何運用本發明所揭示内 谷而完成之等效改變及修飾,均仍 圍所涵蓋。 【圖式簡單說明】 第1圖係顯示本發明辨識劣品基板之方法的第一 例尚未形成開窗部之基板片之示意圖; 只e 第2圖係顯示第i圖之基板片已形成開 圖; |、不思 第3圖係顯示本發明辨識劣品基板之方法的第 例已於基板片形成開窗部之示意圖; 、 第4圖係顯示習知技術進行雷射標記後之基板 意圖;以及 τ 第5圖係顯示第4圖之基板片進行封裝之剖 【主要元件符號說明】 Θ I 基板片 10 切割線 II 基板單元 19259 13 1306305 11, 損壞基板單元 112 晶片接置區 113 光學辨識基準點 114 絕緣層 115、 115’ 開窗部 116 金屬層 117 非晶片接置區 118 接地銲墊 20 晶片 30 基板 3Γ 基板單元 40 通孔 50 錫球銲墊 60 樹脂 100 雷射標記1306305 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an inferior product identification technique, and more to a method for identifying an inferior substrate. Flat. There are [previous techniques] In the semiconductor package process, the substrate structure used for the conductor chip is divided into a single method for wafer processing, which is: ... and cost reduction, generally The (10)p) method connects the retanning to form a (four) plate for simultaneously performing the packaging operation of the plurality of Japanese wafers. In the case of the substrate sheet, each of the substrate sheets includes a plurality of substrates as early as possible, and at the same time, usually The top sheet is placed on the substrate sheet (Die:==, wire bonding (WireB, ^2 IS:, etc., etc.) if the machine is automatically detected to damage the substrate unit. The operation can skip the damaged substrate unit. Thus, the material cost of packaging the damaged substrate unit can be saved, and the defective material can be prevented from being adhered to the damaged substrate unit by the bonding of the wafer. When a defective substrate is found, it is usually applied to the damaged substrate unit by manual application of ink = mark (10) centimeter) in order to prevent the wafer from being bonded to damage the substrate unit t into a defective product. The conventional marking method Firstly, the substrate unit is inspected on the substrate piece by optical inspection or external subtraction inspection. When the damaged substrate unit is found on the substrate piece, the edge strip outside the damaged substrate unit line line) is simply not marked. Good product 19259 5 1306305 基板 Substrate sheet with damaged substrate unit - Ink marking machine, Top: by: Screen Printing in the damaged substrate unit... Second, CCuring and cleaning (Cleaning), the shape of the optical identification reference point (FuhicialMwk) on the outside of the crystallizing area of the substrate unit can be covered by the ink. However, this kind of ink coating operation will increase the manufacturing process and cost of the package, and it is easy for the marking ink to be released during the evaporation of the ink solvent during the process of marking ink (ie, 坤r·.r 〇Β g) It is contaminated to other normal substrate units due to outgasing. Moreover, when the mold is Molding, the substrate sheet is sandwiched between the upper and lower molds, and the high temperature generated by the mold is also likely to cause the ink to soften and the ink at the mark is contaminated on the surface of the mold, so that the original label is damaged after the molding is completed. The marking of the substrate unit is not easy to interpret, and it is necessary to manually repeat the marking to increase the cost. In the above-mentioned problem, the Taiwan invention patent No. 2498〇1 discloses a method for identifying a poor σσ substrate, mainly by laser burning. The optical identification reference point (FidudalMark) on the surface of the substrate unit makes the image inspection system of the machine (such as a CCD camera) unable to find the exact point, and automatically detects that the substrate unit is inferior. In the case of removing the optical identification reference point by laser cauterization, the area of the burning must cover the optical identification reference point, and since the current cutting depth is at least 0.26 mm under the low power, the eye will be dug. The optical recognition substrate portion around the reference point. Therefore, when the thickness of the substrate is reduced to less than 2626 mm due to the height requirement of the semiconductor package (for example, σσ of .136 mm is currently produced), the patented technique is used to form a through hole through the base 19259 6 1306305 when cauterized. . As shown in Figure 4, the cauterization technique is burned close to the (four) line (if the current thunder point is used to form the laser mark, the identification reference substrate is used to perform the molding operation, the inferior substrate unit is fine and fine, as shown in Fig. 5 As shown, the tree (four) is in the second ':!: it will easily damage the substrate unit 31 from the aforementioned laser, and flow to the back of the substrate 30. Moreover, due to the inferior product: the early L, the good substrate unit is very close, the flow The L grease to the back side of the substrate is very smudged. (4) The solder ball of the good substrate unit is 5〇 (the substrate unit of the good substrate is affected. The outer layer is limited by the design of the substrate line (Layom). The correction method sets the optical identification reference point, so that the laser cauterization cannot be used. =: The optical identification reference point is used to form the laser mark, which also limits the application field of this patented technology. ^External 'Because optical _ reference point system is set at # When the laser is burned (4) into a laser mark, it is easy to cause a problem of burning to a good substrate unit and a smoked substrate unit. Therefore, how to develop m to effectively identify a poor substrate Avoidable The above-mentioned laser cauterization technology does not have the problem of traditional ink pollution, and thus solves the shortcomings of the prior art, which is an urgent problem to be considered today. [Invention] It is an object of the present invention to eliminate the need for cauterization. In view of the above-mentioned shortcomings of the prior art, a method for identifying an inferior substrate is provided, which is on time. 19259 7 1306305, a further object of the present invention is to provide a method for identifying a poor substrate, which can avoid a laser burning inferior substrate unit. The optical identification reference point forms a through hole penetrating through the substrate, and even causes the subsequent sealing (4) to repeatedly (4) and seal (4) the problem of contamination caused by the grease overflowing to the solder ball pad of the good substrate unit. The present invention is also intended to provide a poor identification. The method of the substrate can avoid problems such as easy burning of the good substrate unit and the smoked substrate unit when the laser is burned by the optical identification reference point. Another object of the present invention is to provide a method for identifying a poor substrate, which can be avoided. The problem of ink marking and contaminating the good substrate unit. The present invention provides a discrimination for the purpose of The step of the inferior substrate and the method includes: providing a substrate piece composed of a plurality of substrate units, the substrate piece comprising at least one damaged substrate unit, and each substrate unit surface is covered with an insulating layer; and the damaged substrate The insulating layer of the unit forms a window opening portion 俾 by the window opening portion for identifying the damaged substrate unit. In a preferred embodiment, the substrate unit has a wafer connection = (eg, Pad) in the center, and the window is opened. The portion is formed in the wafer connection county. The insulation: the lower element is formed with a metal layer, and the fenestration portion exposes the metal layer. The fourth metal layer is a copper layer. The substrate unit has a wafer connection region: a chip connection region ′ and the window opening portion is formed in the non-wafer connection region. The 曰曰 chip connection region is formed with a ground pad, and the opening is Ground pad. In the method of recognizing the inferior substrate, the method of forming the window portion is performed by laser, and the insulating layer may be, for example, a solder resist layer 19259 8 1306305 (solder mask). The method for identifying the inferior substrate provided by the present invention is based on the substrate sheet, and the edge layer of the opening layer can open the metal layer or the grounding pad under the insulating layer. The layer or grounding pad absorbs the laser heat of the windowing portion and reflects the laser beam, so that the substrate is not burned through, and the optical identification reference point for laser positioning for positioning when the poor substrate is discerned can be solved. At the same time, the application of the present invention can avoid the substrate circuit, so that it can be avoided that the prior art can only be applied to the lack of a limited device. The present invention can be effective as compared with the prior art. When the inferior substrate is identified, the substrate does not penetrate through the substrate, and the optical identification reference point does not need to be cauterized. Moreover, since the identification point of the present invention is far away from the substrate unit, the burnt-good substrate unit or the smoked good substrate is not caused. The unit, which is marked by the ink to contaminate the good substrate unit, and the value of the industry's use has relatively overcome the shortcomings of the prior art. [Embodiment] Now the damage occurs on the substrate sheet at 70 o'clock before the substrate sheet is put into the packaging operation, so as to facilitate the location of the substrate unit in the packaging operation, so that: the line operation can skip the damaged substrate unit without the cooperation of the embodiment. The figure is a detailed description of the identification of the present invention = the implementation steps. The first embodiment of the method for the force burst is referred to the first and second figures, which is a schematic diagram showing the overall flow of the method. 19259 9 1306305 l The method for identifying the inferior substrate in the case of the first embodiment is to provide a substrate sheet, the substrate sheet η1 is divided into a plurality of '70 by a CUUing Line, and the substrate unit 11 includes at least one Or a plurality of damaged substrate units 11. Each of the substrate units 11 of the present embodiment has a -first surface and an opposite second surface (not shown), and the first surface of each substrate unit is formed with a copper such as copper. A metal layer of a layer (not shown) is covered with an insulating layer 114 such as a solder resist layer, and a wafer contact region 112 is defined substantially at the center of the substrate unit. Each substrate unit u is close to the corner end position. • At least one optical identification reference point Π3 (FiducialMark) can be provided for positioning and identification of the upper machine and the wire bonding machine. Of course, substrate sheets having the number of other substrate units can be applied to other practical examples, and are not limited to those shown in the drawings of the present embodiment. Moreover, since the structure and the manufacturing method of the substrate sheet are well-known, they will not be described herein. Next, a window opening portion is formed on the insulating layer 14 of the damaged substrate unit, and the window portion is used to identify the damaged substrate unit. In the present embodiment, when it is found that the substrate unit 1 is damaged in the substrate piece 1, as shown in FIG. 2, the wafer receiving area Π2 of the damaged substrate unit 11' is cauterized by, for example, a carbon dioxide laser or a uv laser. A portion of the insulating layer ι14 is formed to form a fenestration portion '5'. The fenestration portion 115 exposes the metal layer 116 under the insulating layer 114 (as shown in an enlarged schematic cross-sectional view). Since the metal layer 116 can be, for example, a copper layer of magenta, it can be clearly distinguished from the insulating layer 114. At the same time, since the metal layer 116 can absorb the heat of the laser, and the light of the laser can be reflected by the metal layer 116, the fenestration portion is formed to protect the substrate without burning through the substrate sheet 1 . In addition, although the present embodiment forms, for example, a rectangular window opening portion 115, variations and modifications may be made without departing from the scope of the invention. First, when the filming machine (not shown) is bonded to the wafer, the window opening portion 115 can be viewed by the image viewing system to identify the board (U' and can be used by the image. The inspection system checks the optical discrimination!: On-time: 13' to determine the position of the wafer. For example, you can set the machine to the jump mode (Sklp) and view the image inspection system of the machine to the "=5 damage county board unit. Skip the system such as ^ film and wire. It means that the technology and function principle of the machine image inspection (4) _ the substrate unit are well-known, so there is no more explanation here. The method of the present embodiment is directly laser-burned: the soil plate is exposed to an insulating layer such as a solder resist layer, and the insulating layer: a metal layer such as a copper layer can protect the substrate from being penetrated by the laser, and further Avoid passing through the through hole to contaminate the good substrate unit ^, the method of applying this method is not clear, the optical identification standard can avoid the prior art, because the optical identification reference point is close to the substrate cutting boundary, and it is easy to burn to the good substrate unit. And the tobacco party good substrate unit and other issues. Therefore, this The method for identifying the inferior substrate unit is effective to identify = base == through the substrate, and the optical identification base rr is not required to be cauterized at the same time, and the use of the ink in the absence of the ink can be avoided. 19259 11 I3〇63〇5 Eyes refer to FIG. 3, which is a schematic diagram of the second embodiment of the present invention. The same or similar components as the first embodiment are: ^ or approximate component symbol, and detailed description is omitted. In order to make the description of the present invention clearer and easier to understand, the second embodiment of the present invention is largely different from the first embodiment in that the first embodiment forms a window opening portion in the wafer attachment region, and the second embodiment The window opening portion is formed in the non-wafer receiving region. In this embodiment, the window opening portion 115 is formed in the non-wafer receiving region 1 outside the wafer receiving region 112. The substrate is preset to be, for example, an electroless conductive material or a ground material ΐ8 in the non-wafer receiving region 117. When the substrate material 2 is found to have damage to the substrate material u, the non-wafer receiving region 117 has an electroless function. Air soldering or grounding Forming a window opening portion (1) for exposing the open soldering pad or the grounding pad ns of the non-electricity function under the insulating layer 114; when the substrate unit & good product, the insulating layer is available The ΐ4 covers the empty pad or the ground pad 118 of the non-electricity function underneath. /, of course, in the embodiment, the fenestration portion 117 is formed in the non-wafer receiving region 117 in the lower right corner of the wafer receiving region ii2. 'But the opening portion ιΐ5 can also be formed in the non-wafer receiving region 117 at other locations. Thus, the image viewing system of the machine can be used to check whether the substrate unit has the window before the bonding of the wafer. The portion 115 is configured to recognize the damaged substrate unit 1Γ. Moreover, the window closing portion 115 exposes the blank soldering wire or the grounding soldering pad 118 of the electromechanical function, so that electrical and reliability are not generated. 19259 12 !3 〇63〇5 « * or not = regardless of the window opening 115, 115, the chip placement area 112 is disposed in the solution area 117', and the design of the substrate line is not required, so the technology is limited by the substrate line. Can't burn with laser ablation technology:: Identify reference points to form laser markers The problem is also relatively broadening the field of application of the present invention. The specific embodiments described above are for illustrative purposes only and are not intended to limit the implementation of the inventions in the context of the spirit and technology of the invention. The equivalent changes and modifications made by the inner valley are still covered. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a first example of a method for identifying a substrate inferior to the present invention, which has not yet formed a window portion; only FIG. 2 shows that the substrate sheet of the i-th diagram has been formed. FIG. 3 is a schematic view showing a first example of the method for identifying a poor substrate according to the present invention, and a window portion is formed on the substrate sheet; and FIG. 4 is a schematic view showing a substrate after laser marking by a conventional technique. And τ Fig. 5 shows the section of the substrate sheet of Fig. 4 for packaging. [Main component symbol description] Θ I Substrate sheet 10 Cutting line II Substrate unit 19259 13 1306305 11, Damaged substrate unit 112 Wafer connection area 113 Optical identification Reference point 114 insulating layer 115, 115' windowing portion 116 metal layer 117 non-wafer receiving region 118 ground pad 20 wafer 30 substrate 3 基板 substrate unit 40 through hole 50 solder ball pad 60 resin 100 laser mark

Claims (1)

13〇63〇5 十、申請專利範圍: .種辨識劣品基板之方法,係包括·· 包含由多數基板單元構成之基板片,該基板片 有基板單元,且各基板單元表面覆蓋 百化緣層;以及 文血 *4=壞基板單元之絕緣層形成開窗部,以外露 識該出_^^層’俾由該開窗部之金屬層供辨 2·如申請專利範圍第i 雷射方式形成。 Μ’该開窗部係以 3.二!,f利範圍第1項之方法,其中,該基板單元且 4如;=置區,且該開窗部係形成於該晶片接置區内、。 •如申请專利範圍第3項之方法,龙ώ 5. 係形成於該基板單元中央。〃中’該晶片接置區 其中’該絕緣層下係 其中’該金屬層係為 如申請專利範圍第1項之方法 形成有金屬層。 如申請專利範圍第5項之方法 鋼層。 如申請專利範圍第1項之方法, a u ^ 其中’該基板片具有 二ί 置區以外之非晶片接置區,且 "亥開囱部係形成於該非晶片接置區。 如申請專利範圍第7項之方法,f士 區係形成有接地銲墊,且該開4非θθ片接置 墊。 開由部係外露出該接地銲 19259 15 1306305 9. 如申請專利範圍第7項之方法,其中,該非晶片接置 區係形成有不具電性功能之空銲墊,且該開窗部係外 露出該空銲墊。 10. 如申請專利範圍第1項之方法,其中,該絕緣層係為 拒鮮劑層。 16 1925913〇63〇5 X. Patent Application Range: A method for identifying a poor substrate includes: a substrate sheet composed of a plurality of substrate units, the substrate sheet having a substrate unit, and each substrate unit surface covered with a bedding layer And Wenfeng*4=Insulation layer of the bad substrate unit forms a window opening portion, and the outside _^^ layer '俾 is identified by the metal layer of the window opening portion. 2. For example, the i-th laser mode of the patent application scope form. The method of the opening of the window is the method of the first item, wherein the substrate unit and the fourth portion are formed in the wafer connection region, . • As in the method of claim 3, the dragon ώ 5. is formed in the center of the substrate unit. In the middle of the wafer, the wafer is disposed in the middle of the insulating layer, wherein the metal layer is formed by a method as in the first aspect of the patent application. For example, the method of applying the patent scope of item 5 steel layer. The method of claim 1, wherein the substrate sheet has a non-wafer receiving region other than the region, and the "opening portion is formed in the non-wafer receiving region. For example, in the method of claim 7, the grounding pad is formed in the area, and the opening 4 is not a θθ piece. The method of claim 7, wherein the non-wafer connection region is formed with an empty pad having no electrical function, and the window opening portion is externally exposed. The empty pad is exposed. 10. The method of claim 1, wherein the insulating layer is a layer of a repellent agent. 16 19259
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