TWI305984B - Differential signaling transmission circuit - Google Patents

Description

1305984 玖, invention description: [Technical field to which the invention pertains] The present invention takes precedence over the US provisional patent _ 0 π , the monthly case No. 6/399,71 1 , which was filed on August 1, 2002, 苴庐Bamboo "+ shouts as "a low-voltage differential signal driver with an improved matching ethics." The invention relates to signal transmission on a conductive structure. [Prior Art] It is often necessary to transmit a data signal in a manner that provides a relatively fast transfer speed in the case where the power consumption is relatively small. Many of these applications use differential signal modes such as low voltage differential signals - ν〇ΐί - secret (10) (four) signalmg; LVDS). Suppressing common mode noise inherent in a differential scheme allows for low dust consumption when implemented, and low voltage swing in an LVDS application allows for high speed transmission. Moreover, drivers for such systems can be implemented in complementary metal-oxide-semiconductor (CMOS) or metal-oxide-semiconductor (MOS), which provides lower static power consumption. The differential signal circuit can be used to drive paired or unpaired transmission lines such as twisted pair cables, conductors in ribbon cables, or parallel trace differentials on a circuit board. Small noise (electromagnetic interference ("EMI") that interferes with other devices or signal lines. Applications for differential signals and LVDS include image transmission (such as in a digital camera or between a camera and a host), Video image transmission (such as from one

O:\87\87182.DOC 1305984 Host computer or processor to a display screen (such as in a laptop or a flat panel display device) or at a distance of a few meters) and other high-speed transmission of data (such as a high-speed magnetic Slice storage interface). In summary, a low voltage differential signaling solution offers many benefits such as less power consumption, lower leg firing, good common mode noise rejection, lower cost cable interface, and simplified transmitter design (10)s. The structure of the /output interface, which illustrates the low electrical termination impedance and low voltage swing of this scheme. The documentation defining the LVDS transmission scheme includes the ANSI/TIA/EIA-644 standard, the IEEE i596.3 standard (Extensible Interface LVDS or "SCI_LVDS") and subsequent revisions. Figure 2 shows an embodiment of an LVDS driver circuit. In this circuit, 'use N-channel MOS field-effect 曰曰曰 body (仏1 (1_valent as transis^r; FET) NP1, NP2, NS1, and NS2 via - load 1〇 use switching current. The input signals SN and sp of the state, the four transistors function as a current guiding unit for switching the direction of a driving current (provided by the current source CSR1) and providing a differential wheel to the resistive load The current returned by the signal from the 3 hp load is transferred to the current sink CSK1. Figure 3 shows a circuit that does not include a two-digit inverter that can be used to generate an input signal for the circuit of Figure 2 from a single digit §§ ^ and sp. Fig. 4 is a schematic diagram of the circuit of Fig. 2, which illustrates how the current source CSR1 and the current slot CSK1 are actually implemented (where cmc represents a current mirror circuit) to maintain a desired offset voltage. The driver circuit in FIG. 4 comprises a three-regulated operational amplifier (〇pamP) (Xb X2 and X3), two series resistors R2, R3, and a current source and a switching transistor unit pcb NC1.

O:\87\87182.DOC 1305984 A mimicking circuit. Figure 5 shows an alternative LVDS driver circuit in which an offset voltage VQff is applied between a pair of series source-to-terminal resistors R4 and R5. 6 shows a circuit that can be used to generate an analog differential signal to drive the circuit of FIG. 5, and FIG. 7 is a schematic diagram of the circuit of FIG. 5, which is how the current current source is actually implemented using a particular current mirror configuration. The CSP and the current tank CSN are described. The term "exemplary" is used herein to mean an example only and does not necessarily represent a preferred or preferred value or example. When an N-well method is used to implement an LVDS driver circuit as shown in Figure 2 or Figure 4, the transistors NP 1 and NP2 may be subject to body effects. Therefore, the effective "ON" resistance of these transistors can be relatively high compared to the resistance values of PM0S with similar configuration settings of comparable sizes. The resulting voltage drops across transistors NP1 and NP2 can force the minimum value required for the power supply potential (VDD) to be greater than the desired value. Another drawback of the LVDS driver circuit shown in Figure 4 can be caused by the inherent offsets in the feedback loops of the operational amplifiers X2 and X3. As a consequence of such offsets, the "Imitation" transistor PC0 matches the current source PC1, and the "Imitation" transistor NC0 matches the current tank NC1 may not be sufficient to ensure the current and current source delivered to the current slot NC1. The match between the currents provided by PC 1. Conversely, the current flowing from the positive terminal of the driver to the load (and the current flowing from the load to the negative terminal of the driver) can be switched "ON" by the current switching transistors NP1, NP2, NS1, NS2. The resistance value and the resistance value of the load R1 are defined. Therefore, when there is a mismatch between "Imitation" transistor ΝΡ0 1305984 and either of the current switching transistors NP1 and NP2, or between "Imitation" transistor NS0 and any of the current switching transistors NS1 and NS2, The circuit may be susceptible to large variations in the voltage drop across R1. In addition, a driver using a conventional single-ended digital control circuit as shown in Figure 3 may suffer from timing distortion due to the mismatch between the SNs applied to the driver inputs and the signal rise-downs. Figure 7 illustrates another LVDS driver circuit. A driver circuit shown in Figure 7 does not utilize the emulation circuit but attempts to directly set an output common-mode voltage using two resistors R4 and R5 and a voltage regulator, XI. Applied to the driver = the control signals are, for example, analog signals provided by the differential control signal generator as shown in Fig. 6 (in this case, 卯 = 32, 33 and = = ^, material). To reduce the power consumption of the circuit in Figure 7 and reduce the loading of load R1, it may be necessary to implement R4 and R5 using a relatively large value of the effective resistance (i.e., compared to the effective resistance of Rl). However, when all of the current switching transistors (^PS2, NS1, NS2) are turned off, although the output common mode of the circuit is good, it is good, but when the R4 and sink (DC) resistance values are Or greater than the resistance value of the motor source csp or greater than the resistance value of the current slot CSN, the driver: can encounter - problem (such as the actual output common mode voltage may change). For example, °, when (1) there is a current mismatch between the current source CSP and the current tank CSN and (7) the current source CSP and the current tank CSN are short-channel current sources, this can occur. Figure 8 illustrates the example of Figure 7, which shows the effective resistance of various components, specifically not the norm. In this example, it can be seen that the actual output (4) is not only set by the reference potential Vref but also by the orbital potential (six)

0: V87\87 丨 82.DOC 1305984 p〇tentiai) VDD to set. In order to reduce the effect of % or V(10)D on the output common-mode voltage in this _circuit, it is necessary to reduce the resistance value with which the load of the output resistor Ri and/or the power consumption of the driver circuit may increase. Furthermore, reducing the resistance by (10) can cause an increase in the current flowing through it. In order to handle the increase in current, this situation may require widening of ^ and R5' resulting in an increase in the area of the wafer. Some specific embodiments of the invention disclosed herein may be used to solve one or more of the problems set forth above. However, the solution to such problems should not be considered as a feature, an object, or other limitation of the invention. The specific embodiments of the present invention are applicable regardless of the existence or solution of any such problems, and the scope of the present invention is only as defined in the patents of the issued patents. [Embodiment] FIG. 9 shows a schematic diagram of a driver circuit using PMOS (PS1, squeak and face (10) (Cong, NS2) transistors in accordance with an embodiment of the present invention. In an exemplary implementation In the example, the main system of the four transistors is connected as a switch to each power source (ie, the body of ps 1 and Vdd are connected, and the body of NS1 and NS2 is connected to Vss). It is also required that the transistor PS1 can be matched with PS2. The transistor NS1 can be matched with the NS 2. The 忒 driver circuit also includes a bias or control circuit 丨丨〇. The circuit includes transistors PC0 and NC0, which respectively replicate the current source transistor PC1 and the current slot transistor NC1, • Transistors PS0 and NS0, which respectively replicate current switching transistors PS1/2 and NS1/2; and resistors R2 and R3, which replicate the load R1' in series and define an offset voltage V〇ff at its junction. 1305984 With this replicated current path, the current flowing through PC0 is equal to the current flowing through NC0, and thus the current flowing through PC 1 can match the current flowing through NC 1. In other words, from the positive terminal of the driver to the Load R1 The current can be matched to the current flowing from the load R1 into the negative terminal, thereby generating less EMI. For this driver, the output common mode voltage is based on the replica current path (PC0, PS0, R2, R3, NS0, NC0). And a comparator (the feedback operational amplifier XI) is well defined. The feedback operational amplifier XI compares a reference voltage Vref with the offset voltage VQff and biases the current consuming transistors NC0, NC1 to maintain the voltages The feedback operational amplifier XI can receive the reference voltage Vref from a node external to the current path of the driver circuit (or otherwise independent of the current paths). For example, the feedback operational amplifier XI can be self-contained such as a bandgap This potential is received at a reference circuit of a reference signal generator, etc. The feedback operational amplifier XI can be transconductive such that the offset voltage node is unloaded. Thus, a circuit implementation as shown in FIG. 9 can be applied. The solution is to ensure that the offset voltage VQff and the output common mode voltage value are both equal to the reference voltage Vref. It is required that the transistor PC0 and PC1 are well matched. The body NC0 is well matched with the NC 1. The consistency between a pair of adjacent circuit elements can be improved by constructing one or more dummy elements therebetween (e.g., during an engraving process). Crystal matching (such as PC0 and PC1, and NC0 and NC1) can be improved by adding dummy transistors between and/or around the transistors during construction. Figure 1 illustrates the driver circuit of Figure 9. In an embodiment, the circuit includes virtual cells NC2, NC3, NC4, PC2, PC3, and PC4, which are arranged side by side between and around NC0 and NC1, and between PC0 and PC1 and around %1305984. In another embodiment, the dummy cells can be used to increase the match between the current switching transistors OP1 and PS2 and/or between the current switching transistors NS1 and NS2. It should be noted, however, that adding dummy components reduces the area of the available wafer (or instead increases the circuit size).

In another embodiment of the driver circuit as shown in FIG. 9 or FIG. 10, the replica transistors PC0, PS0, NS0, and NC0 are implemented such that their channel width values are the respective transistors of the transistors PCI, PS1, NS1, and NC1. A normal score (1 / K). In this case, the resistance value of (R2 + R3) is implemented as a common multiple (K) of the resistance value of R1. To ensure that the replicated current flowing through PC0 and NC0 is substantially equal to a fraction (1/K) of the driver current flowing through PC1 and NC1, the dummy cells can be placed side by side, such as transistors PC0 and PC1 and/or Transistors NC0 and NC1. In this embodiment, it may be desirable for one or more dimensions of each dummy transistor to match the respective dimensions of the adjacent transistors. Where the virtual cell is between two different sized transistors, it may be desirable for one or more dimensions of the imaginary cell to be an arithmetic or geometric mean of the respective dimensions of the peripheral transistors. Alternatively, the dimensions of the dummy cells alternately at locations with current carrying transistors may be selected to conform to or approximate a particular arithmetic or geometric progression at the junction with the current carrying transistors. Resistors R2, R3 can be implemented as connected resistors or active components (such as MOSFETs) to provide a fixed (or alternatively controllable and/or compensated) resistance. Although other embodiments are possible, R2 and R3 are typically implemented to have the same electrical resistance. An alternative embodiment of a circuit shown in Figure 9 or Figure 10 is O:\87\87182.DOC -12- 1305984 embodying the other components of the driver circuit (or only the (four) or the current switching current path) A wafer includes pins that are externally compliant (and can be selected and changed, for example, as needed) to feed w, R3. As shown in Figures 9 and 1B, in a current mirror configuration, the transistor PC5 is coupled to the transistors PC0 and PC1 (and possibly to the virtual unit). Other known current mirror configurations can also be used, such as the singular cascode amplifier or the modified surface current mirror (eg, Sed_ Smith published in Oxford University (4) 9 i, 3rd edition, "Microelectronic Circuits" The figure shows a _driver circuit according to another embodiment of the present invention, which includes a control circuit 120. The driver circuit includes two pairs of rs (PS1, PS2) and a deletion _ _, the main body of which can be two The positive pole is connected to the negative power supply rail. To achieve a desired differential output voltage on the resistive load R1, this can be implemented,

Generating a drive current that is equal to the power 4, and a bias circuit in the source transistor pci and the replica (as shown in Figure 4, an emulation circuit (10)) to define the round-trip common mode power is different. The control electric I of Figure 11 falls (here is - I here: a feedback loop to reverse the current slot transistor (10). In this circuit, at least one of the sinus resistors R1 is loaded ', ' (column In order to reduce the load power, although the heart; and the size of 5: the same size as the required size - = but usually R4_ will be implemented with the shown -:, = less - copy bias (four) The road can also be implemented with less U. The power consumption is reduced compared with the circuit shown in Figure 4 or Figure 9.

O:\87\S7182.DOC -13- 1305984 The configuration of the amplifier x i is used to compare a reference voltage: - common mode. Operational amplification, X1 can be derived from the driver's electrical section (or otherwise independent of the current path)

Reference Voltage I For example, the operational amplifier X1 can receive this potential from a reference circuit such as a bandgap I. The operational amplifier can be transposed so that the observed voltage node is unloaded. Therefore: the amplification XI adjusts the voltage at the node between the anatomy 4 and the erection 5 to the output parameter = voltage W by indirectly setting the output common mode power by controlling the current slot NC1 = using illusion ', then _, _115 The feedback sergeant advantage 'the circuit of Figure u can be implemented' such that the electrical "transmission" delivered to the current sink (10) is equal to the current received from the current source pci. The electrical body PC5 can be replaced with another current mirror configuration as described above. Similarly, a dummy cell can be added as above to improve the matching between the pair of current switching transistors (e.g., PS 1 and PS 2). The current switching transistors PS1, NS1, M2 and NS2 shown in Figures 9, 1 and 11 can be controlled by input signals SN and SP applied to their terminals (or "control electrodes"). These input beliefs (4) may be complementary orbital to orbital quantities provided by the symmetric control signal generators of Figure 2. - The input data signal DT1 and a complementary signal DTm are both sampled by the pulse signal CK1 and the same complementary signal (5) (10). The output signals SP and SN have equal rise and fall times. (Each complementary signal DTIN and CK1N can be obtained by, for example, passing the corresponding signal of one of the signals 〇τι and (3) through a digital inverter.) Therefore, a driver circuit shown in FIGS. 9, 忉 and U The pulse width can be maintained.

O:\87\871S2.DOC -14- 1305984 Figure 12 shows the same control single J circuit, which can be used to provide track, main track control signals to a driver circuit as described herein (Figures 2, 4, 5 7 Or 9 to 11 because the number of ups, downs, and drops does not match, so the special control will suffer from the influence of the guard and distortion. As long as the _ said that the same track to track control unit in January is - a symmetric arrangement, that is, the circuit can be applied to generate signals SP and SN' having a number of equal and hundreds of equal rise and fall times so that the signal is turned on and off. The pulse width of the structure is maintained. The circuit can also be operated in the case where the complementary signal imN is delayed relative to the data signal DT1 or the complementary signal ck1N is delayed relative to the pulse signal CK1. Even if this is the case, the elements can be implemented as long as the elements of the two control units can match a circuit such that the signals have equal rise and fall times. In the circuit of Figure 2, when the signal CK1 is low (ie, when the analog switches P2/N2 and P6/N6 are on), Transistor The gates of p3, N3, p7 & N7 are likely to be in a floating state. This condition can result in unstable or wasted operation of inverters P3/N3 and P7/N7. Figure 13 shows another embodiment of this circuit. This can be used to avoid this situation. When the analog switches P2/N2 and ?6^6 are in the on state, this embodiment includes the analog switches P2A/N2A and P6A/N6A in the off state, and vice versa. The floating gate state of transistors P3, N3, P7 and N7 can be avoided. Figure 14 shows an example of a timing diagram for this circuit in which signal CK1N is delayed relative to signal cki. In particular, this example shows that the two data values are adjacent. The change between the pulse periods' then there is no data value change between adjacent clock cycles, followed by 0:\g7«7182.D0C -15- 1305984 Another data value change. It can be seen that if not introduced The data values SP and SN may have equal rise and fall times. Figure 15 shows a variation of the circuit of Figure 13, in which the inverters P1A/N1A and P5A/N5A are omitted. In the case where the load is increased on P1/N^p5/N5, This circuit is applicable. In addition, in some applications of the circuit as shown in Figures 12, 13 or 15, although the output signals may not be of a strict track-to-track type, it is acceptable to directly from the analog switches. The output terminals (ie P2m2W6/N6_ terminals) obtain these output signals. In this case, the inverters 3, P4/N4, P7/N7 and P8/N8 can be omitted. With the traditional output driver In contrast to controlling the electric bass, the output driver and the operation of the control circuit in accordance with a particular embodiment of the present invention can provide several benefits. As described above, the matching between the current flowing from the positive terminal of the _driver circuit shown in Figs. 9 and 1G and the current flowing through the negative terminal can reduce the surface to be emitted. The matching of this current value can be attributed to the feedback loop and virtual unit shown in _, ^. In Figure u, the ❹(4) office does not need to use additional replica transistors and virtual cells to ensure that the defined-output common-mode voltage' consumes less power. The circuit shown in Fig. 4 is different from the output resistor R1 to increase the load, and the values of the R1 and R5 in the graph u ‘, ', , , °·%Η can be as large as possible. Therefore, this circuit is applied. On the other hand, with respect to the strength of the circuit area in Fig. 3, the same track-to-orbit control diagram and motion diagram 9 as those described in Fig. 3 are not opposite to the control circuit 13 and 丨5. A driver is shown in the figure; the road:: can be used for: The output signals will not be affected by the rise and fall times, and the other is not allowed to make the paper mismatch.

O:\87\87182.DOC -16- 1305984 True (four) rings. However, as indicated above, 'the specific potential benefits of a particular example or implementation should not be taken as a general requirement of the invention: the scope of the invention is only by the scope of the issued patents/ Derogatory. Moreover, the present invention may use active components (e.g., bipolar transistors, heterojunction devices, in some cases (e.g., without specifically claiming the need for a device), in addition to the elements explicitly described or referenced herein. , Jinyuan semiconductor field effect transistor (metal.insulatGr_semie () ndu coffee coffee transistor; MISFET), and / or other current control device magical [simplified schematic] Figure 1 illustrates an example of an LVDS input / output interface Figure 2 shows an LVDS driver circuit; Figure 3 shows a digital control circuit used with the driver circuit of Figure 2; Figure 4 shows the -lvds driver circuit of an emulation circuit; Figure 5 shows an LVDS driver circuit; An analog output control generator that is not used with the driver circuit of FIG. 5; FIG. 7 shows an embodiment of the driver circuit of FIG. 5; FIG. 8 shows a model of the driver circuit of FIG. 9 shows a circuit according to a specific embodiment of the present invention; FIG. 10 shows an embodiment of the circuit of FIG. 9; (10) FIG. 5 shows an embodiment of the present invention in accordance with an embodiment of the present invention. Administration of a block diagram; FIG. 12 according to the present invention play out - of specific embodiments of the - signal generator

O:\87\87182.DOC, 17-1305984 circuit; Figure 13 shows an embodiment of the circuit of Figure 12; Figure 14 shows a timing diagram of the circuit of Figure 13; and Figure 15 shows an embodiment of the circuit of Figure 13. [Description of Symbols] CK1 Clock Signal CK1N Complementary Signal CMC Current Mirror Circuit CSK1, CSN Current Slot CSR1 ' CSP Current Source DC DC DTI Data Signal DT1N Complementary Signal N1, N3, N4, N5, N7, N8 Inverter N2, N6 analog switch NCO emulation transistor NCI current source NC2, NC3, NC4 virtual unit NP1, NP2, NS1, NS2 transistor PI, P3, P4, P5, P7, P8 inverter P2 ' P6 analog switch PCO Crystal PCI current source PC2, PC3, PC4 virtual early element '182.DOC - 18 -

O:\87\87182.DOC 1305984 PC5 transistor PS1, PS2 transistor R1 - R5 resistor SN, SP input signal V〇d ' Vgnd ' Vss voltage Voff offset voltage Vref reference voltage XI, X2, X3 operational amplifier 110, 120 control circuit O:\87\87182.DOC -19-

Claims (1)

Replacement of this application | 7 years picking, patent application scope: a circuit for the #号 transmission, the circuit includes: - current source; 电流 a current slot of a current control terminal; / with - current guide to the output node a circuit, the current directing circuit configured to receive current from the current source and to pass current to the current slot 'and the current directing circuit configuration is configured to provide a differential to a load connected across the output sections And a control circuit comprising a voltage regulator configured to compare a reference voltage to an offset voltage: generating an adjusted voltage, f, the current slot The current control terminal is configured to receive the adjusted voltage. 2. The signal transmission circuit of the first item of claim 4, wherein the electric production circuit comprises two switches, each of which has an input node: Roll out the print-' and its configuration is set to supply current to each output node or receive current from the output node according to a potential at the input node. 3. As claimed in item 2 a signal transmission circuit, wherein each switch of the current conducting circuit comprises a first transistor and a second: a body, and a day, wherein the first transistor level of each switch is set and configured to be conductive a motor responsive to a high potential at each input node and substantially non-conductive to respond to a low potential at each input node, and wherein the second transistor configuration of each switch is configured and configured The transmission circuit, wherein the current leads the first transistor and a second transistor, each switch of the signal guiding circuit of claim 2 includes: And wherein each of the first transistors is a PM〇s transistor, and each of the second transistors is an NMOS transistor. 5. The signal transmission circuit of claim 4, wherein each And a first electro-optic system configured to receive current from the current source, and wherein the second electro-optic system is configured to pass current to the current sink. 6. Signal transmission as claimed in the scope of claim Circuit, the The circuit further includes a transistor coupled to a current control terminal of the current source in a current mirror configuration. 7. The signal transmission circuit of claim i, wherein the voltage regulator 8. An operational amplifier. 8. The signal transmission circuit of claim 1, wherein the control circuit further comprises a pair of series resistors, wherein the voltage regulator is configured to obtain the bias from the junction between the pair of resistors 9. The signal transmission circuit of claim 1, wherein each external node of the pair of resistors is electrically coupled to one of the respective output nodes of the current steering circuit. The signal transmission circuit of the item: the control circuit further comprising a replica current slot having a current control terminal electrically coupled to the current control terminal of the current slot, and the 871S2-970104.doc β positive Replace Page—Copy current source. U. The signal transmission circuit of claim 10, wherein the control circuit further comprises an electrical body system that is consuming a current control terminal of the current source in a current mirror configuration. α is the signal transmission circuit of claim 10, wherein the voltage regulator is an operational amplifier. 13. The signal transmission circuit of claim 1, wherein the replica current source has a channel width that is less than a channel width of the current source by a first ratio, and wherein the replica current slot has a channel The width, which is smaller than the channel width of one of the current slots, is the first ratio. M. The signal transmission circuit of claim 1, wherein the circuit comprises at least one virtual transistor, wherein 'the at least one virtual electro-crystal system is located at a selected one of the group consisting of: Next to the current source, next to the current tank, next to the replica current source, next to the replica current tank, between the current source and the replica current source, and between the current sink and the replica current sink. 15. The signal transmission circuit of claim 1, wherein the control circuit further comprises a first replica current switching transistor and a second replica current switching transistor, wherein the first replica current switching transistor The system is configured to receive current from the replica current source, and the second replica current switching transistor system is configured to pass current to the replica current sink. 16. The signal transmission circuit as claimed in claim 15 wherein the first 87182-970104.doc 1 (more) i replacement page The replica current switching transistor is a PM 〇s transistor, and wherein the second replica current switching transistor is a NMOS transistor. The signal transmission circuit of claim 15, wherein the control circuit further comprises a pair of series resistors, wherein 'the first replica current switching transistor system is electrically coupled to an external node of the pair of resistors And wherein the second replica current switching transistor system is electrically coupled to another external node of the pair of resistors. 18. The signal transmission circuit of claim 17, wherein the voltage regulator is configured to obtain the offset voltage from the junction between the pair of resistors. 19. The signal transmission circuit of any one of claims 1 to 18, wherein the circuit is embodied in an integrated circuit. 20. The signal transmission circuit of any of the preceding claims, further comprising: a display panel configured to receive the differential signal. A control signal generator comprising: a first control unit comprising: - a first-inverter configured to invert a data signal, and a - analog-to-digital switch comprising an input terminal, An output terminal, a first control terminal and a second control terminal; and a first control unit comprising: - a second inverter 'configured to reverse the number of the data signal, and a second analogy The switch includes an input terminal wheel terminal 87182-970104.doc 1505983⁄4. / jade replacement page f ·· ->«·· I a first control terminal and a second control terminal; wherein, the first An analogy relationship configured to receive the inverted data signal at the wheeled terminal, and wherein the second analog relationship is configured to receive the inverted complementary data signal at the input terminal, and wherein the a class of open relationship configured to receive a clock signal at the first control terminal and a complementary signal of the clock signal at the second control terminal, and wherein the second analogy The system is configured to receive a clock signal at the first control terminal and a complementary signal of the clock signal at the second control terminal, and wherein when the first control terminal is at a high potential and the first When the two control terminals are at a low potential, the configuration of the first analog switch is set to have a closed state, and when the first control terminal is at a low potential and the second control terminal is at a high potential The configuration of the first analog switch is set to have an open state, and wherein the second analog switch is when the first control terminal is at a high potential and the second control terminal is at a low potential The configuration system is configured to have a closed state, and when the first control terminal is at a low potential and the second control terminal is at a high potential, the configuration of the second analog switch is set to have an open state . 22. The control signal generator of claim 21, further comprising a third inverter configured to receive the data signal and generate the complementary data signal, and a fourth inverter configured to The clock is received and the complementary clock signal is generated. 87182-970104.doc 23. A low voltage differential signal driver comprising circuitry for performing signal transmission as claimed in any one of claims 1 to 18. 87182-970104.doc {nJ 130598牟121163 Patent Application Chinese Illustration Replacement (January 1996) Pickup, Drawing: Painting One 3.3mA -►· Zo=50 ohm •· 87182-960105.doc 1305984 Country 2 CSR1 wake up 3 87182-960105.doc 1305984 87182-960105.doc 1305984 I- nr ΛΗΙ 87182-960105.doc -4- 1305984 J 87182-960105.doc 1305984 87182-960105.doc 1305984 Painting 8 VDD 3.6V 87182-960105.doc 1305984 Drawing 9 87182-960105.doc 1305984 87182-960105.doc 1305984 ii , ι : ^ 182 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 960105.doc -11 - 1305984 J !Si8 s r-d N4 P4 H 1113 SP SN 1 87182-960105.doc -12- 1305984 87182-960105.doc _ 13_ I1305984 DTI CK1 CK2 SP climbing DTI 2 87182-960105.doc • 14-