JP2010166472A - Differential signal drive circuit and differential signal transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-voltage differential signal drive circuit small in circuit scale, operable at a high common voltage even if a power voltage is lowered, suppressed in reflection at an end of a transmission line, and capable of performing stable transmission. <P>SOLUTION: The low-voltage differential signal drive circuit includes: a first drive signal power source for outputting a first voltage; a second drive signal power source for outputting a second voltage different from the first voltage; and an output changeover means for distributing and outputting outputs of the respective signal power sources to first and second output terminals. The low-voltage differential signal drive circuit can be provided by forming at least either of the drive signal power sources with a resistor having a resistance value nearly equal to the characteristic impedance of a transmission line arranged between the power source and the output terminal, and a current source connected to the resistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technical field of a low voltage differential signal driving circuit, and more particularly to a low voltage differential signal driving circuit operable with a low power supply voltage and a low voltage differential signal transmission system using the same.

  Conventionally, an interface of a low voltage differential signal represented by LVDS (Low Voltage Differential Signal) when image data generated by an image sensor in a mobile phone or a digital camera is transferred to another signal processing chip at high speed. Is used. By reducing the number of digital signals that make up the bus, the system can be reduced in size and weight, and the generation of unwanted radiation (EMI) that affects image quality can be greatly reduced. It is an important technology. In recent years, the amount of image data to be handled has increased, and the demand for higher speed has been increasing. Therefore, the transmission rate has been increased. As a result, deterioration of waveform quality due to reflection at the end of the transmission line has become a problem. For this reason, it is necessary to consider each impedance matching of the output and transmission line of the driver on the transmitting side and the terminating resistor on the receiving side.

  A method for realizing an LVDS driver considering impedance matching is disclosed in Patent Document 1. The circuit is shown in FIG. 1, and a voltage source (17) and a matching resistor (12) for giving an output impedance substantially equal to the characteristic impedance of the transmission line are connected in series on the VDD side. A high level output voltage source (11) is connected to the VH node. Similarly, on the GND side, a voltage source (14) composed of a voltage source (18) and a matching resistor (15) for giving an output impedance substantially equal to the characteristic impedance of the transmission line is connected to the VL node. Is done. Between the VH node and the VL node, there is a switch matrix composed of transistors (12a, 12b, 13a, 13b), which is driven so that one of the output terminals OUT + and OUT- is connected to VH and the other is connected to VL. . The voltages of the two output terminals are transmitted to the receiving device side by the transmission line, where they are terminated by the terminating resistor (14), and received by a low voltage differential signal receiving apparatus (not shown).

  By the way, it is important to improve the waveform quality as the speed increases, but it goes without saying that in order to increase the speed, it is important to use a miniaturized process. However, the power supply voltage tends to gradually decrease with the miniaturization, and new standards for LVDS are emerging one after another. On the other hand, however, there is still a strong need to use a conventional standard in order to shorten the design period or reduce development costs in the design of new product equipment. However, since the conventional LVDS standard has been established in accordance with the high voltage so far, when trying to lower the power supply voltage of the LSI itself, a relatively high output voltage must be output even though the power supply voltage is low. Disappear.

  For example, the Sub-LVDS interface standard is used in the CCP2 (Compact Camera Port) of the SMIA standard and the CSI-1 (Camera Serial Interface) defined by the MIPI Alliance. A certain common voltage is set to 0.9 V as a standard, and two differential outputs swing with an amplitude of 150 mV around the common voltage. If the power supply voltage is 1.8 V, this common voltage is preferably located near the midpoint of the power supply voltage. However, when the power supply voltage drops to, for example, 1.1 V, the common voltage moves to the power supply voltage side. It becomes very close, and the margin for operating the circuit normally becomes smaller.

Taking the case of configuring a Sub-LVDS driver with a power supply voltage of 1.1 V as an example, how each node voltage in FIG. 1 will be described in detail. Consider each node voltage when “L” is applied to IN + and “H” is applied to IN− in FIG.
In order to simplify the explanation, it is assumed that the on-resistances of the transistors (12a, 12b, 13a, 13b) are zero ideal switches. Since IN + is “L”, the PMOS transistor (12a) is turned on and the NMOS transistor (12b) is turned off. Therefore, the OUT + node is connected to the VH node, and the voltage at the OUT + node is equal to the voltage at VH. Conversely, since IN− is “H”, the PMOS transistor (13a) is turned off and the NMOS transistor (13b) is turned on. Therefore, the OUT− node is connected to the VL node, and the voltage of the OUT− node is the voltage of VL. Will be equal.

  In the Sub-LVDS system, the common voltage is 0.9 V and the amplitude is 150 mV. Therefore, when a high state is output, the VH voltage is 0.9 V + 150 mV / 2 = 0.975 V, and when a low state is output, the VL voltage It is necessary to set it as 0.9V-150mV / 2 = 0.825V. At this time, the current flowing through the termination resistor (100Ω) is 150 mA, and the VH0 voltage that is the output voltage of the voltage source (17) is determined by this current and the resistance value of the matching resistor (12). Since the value of the matching resistor needs to be about 50Ω in order to match the characteristic impedance of the transmission line, the VHO voltage is VH + 150 mA × 50Ω = 1.05V. A voltage corresponding to the difference between the VDD and VH0 voltages (hereinafter referred to as Vcal) is generated by the voltage source (17). However, the VH0 voltage is determined only by the Sub-LVDS standard and the matching resistance value regardless of the VDD. Since it is a fixed value that is determined, Vcal becomes relatively small when the VDD voltage becomes low. For example, when VDD = 1.1V, it is necessary to make Vcal = 0.05V very small.

  As a configuration circuit example of the high-level output voltage source (11), FIG. 2 shows a drain contact method and FIG. 3 shows a source grounding method. There are differences between NMOS and PMOS depending on the method, but in both cases Vcal The voltage corresponds to the drain-source voltage of the output transistor, and decreasing the Vcal voltage means that the drain-source voltage of the output transistor must be decreased.

US Pat. No. 6,867,618

However, in order to reduce the potential difference between the drain and the source, it is necessary to increase the size of the transistor, and the area occupied by the driver with respect to the entire LSI chip becomes extremely large, increasing the cost of the chip and the chip size. There is a problem that disadvantages such as hindering downsizing of the device occur due to an increase in mounting area accompanying the increase.
In view of such circumstances, the present invention intends to provide a low voltage differential signal driving circuit capable of operating at a high common voltage even with a low power supply voltage with a small circuit scale.

  In order to solve the above problems, the first invention provides a first drive signal voltage source that outputs a first voltage, and a second drive signal that outputs a second voltage different from the first voltage. In a low-voltage differential signal driving device having a voltage source and output switching means for distributing and outputting the output of each signal voltage source to the first and second output terminals, at least one drive signal voltage source is A low-voltage differential signal driving device comprising a resistor provided between a power supply terminal and an output terminal and a current source connected to the resistor. The low-voltage differential signal driving device further comprises current adjusting means for adjusting the current value of the current source so that the first voltage becomes a predetermined voltage value.

  The second invention is a differential signal transmission system comprising a low voltage differential signal driving device, a low voltage differential signal receiving device, and a transmission line connecting between the low voltage differential signal driving device and the low voltage differential signal driving device. A first drive signal power supply for outputting a voltage; a second drive signal power supply for outputting a second voltage; and an output switching means for distributing the outputs of the signal power supplies to the first and second output terminals, respectively. And at least one of the drive signal voltage sources includes a resistor having a resistance value substantially the same as the characteristic impedance of the transmission line provided between the power source and the output terminal, and a current connected to the resistor. A low-voltage differential signal transmission system comprising a power source.

  According to the present invention, it is possible to realize a low voltage differential signal driving circuit capable of operating at a high common voltage even with a low power supply voltage and capable of stable transmission with little reflection of a transmission signal with a small circuit scale. .

It is the figure which showed the conventional differential signal drive circuit. It is a circuit diagram of a drain common type voltage source. It is a circuit diagram of a common source voltage source. It is the figure which showed the differential signal drive circuit in this-application Example. It is a figure for demonstrating the principle of replacement of a voltage source and a current source. It is the figure which showed the electric current adjustment circuit in an Example of this application.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 4 shows a circuit diagram of this embodiment. The difference from the conventional example is only the high-level output voltage source (41) arranged on the VDD side and the inside thereof. In the figure, the same reference numerals as those in FIG. Unlike the conventional example, the high-level output voltage source (41) is a matching resistor (12) disposed between the power supply voltage VDD and the VH node, and a current source (43) disposed between the VH node and GND. Consists of That is, in the prior art, the high-level output voltage source (11) is composed of a resistor and a voltage source, but in the present embodiment, it is composed of a resistor and a current source. Thus, conventionally, when the power supply voltage is lowered, the voltage difference between both ends of the voltage source (17), that is, when the Vcal voltage is reduced to 0.05 V or the like, it is difficult to make a voltage source (17) operating between them. However, in the present embodiment, as shown in the figure, an equivalent electrical characteristic can be obtained by arranging the current source (43) between a large potential difference (about 0.975 V) between GND and VH, so that the power supply voltage is low. Even in this case, the high-level output voltage source (41) can be realized without difficulty. In this way, by configuring the high-level output voltage source with the matching resistor and current source instead of the matching resistor and voltage source, the Sub-LVDS driver can be integrated inside the LSI even when the power supply voltage becomes low. Becomes easy.

  FIG. 5 is a diagram for explaining equivalence of the replacement of the voltage source and the current source. (A) shows a diagram of the replacement of a basic voltage source and a current source that are generally well known, in which a voltage source having a voltage value of V and a resistor having a resistance value of R are connected in series; A current source having a current value of I = V / R and a resistor having a resistance value of R connected in parallel are equivalent. Next, (b) is a case where the voltage of GND in (a) is replaced with VDD and the polarity of the voltage source is reversed. Further, (c) is a rewritten version without changing the topology. As can be seen, the left of (c) corresponds to the high-level output voltage source (11) of FIG. 1, and the right of (c) corresponds to the high-level output voltage source (41) of FIG. Although both have a difference in the form of using a voltage source or a current source as a circuit, it can be seen that the obtained electrical characteristics are equivalent.

Here, as described in the conventional example, when the Sub-LVDS system is realized with the power supply voltage of 1.1V, the VH0 voltage is 1.05V and the Vcal voltage is 0.05V. The current value (Ical) required at the source is Vcal / R = 1 mA when R = 50Ω, and this current itself is required separately from the current (1.5 mA) for driving the termination resistor. Since it can be realized with a power supply voltage as low as 1.1 V, the overall power consumption can be made rather small.
Since the Vcal voltage changes according to VDD, the Ical current needs to be adjusted according to the power supply voltage.

Hereinafter, a specific example for performing appropriate current adjustment according to VDD will be described.
FIG. 6 shows a circuit for adjusting the Ical current. A voltage corresponding to 1/2 of VDD is input to the non-inverting input terminal of the operational amplifier (63a) by the resistance voltage dividing circuit. The output of the operational amplifier (63a) is connected to the gate of the PMOS (62a), the source of the PMOS (62a) is connected to the inverting input terminal of the operational amplifier (63a), and the source voltage of the PMOS (62a) is 1 of the VH0 voltage. A feedback loop is formed to be equal to / 2. Similarly, a voltage half of VH0 generated by a reference voltage generation circuit (not shown) is input to the non-inverting input terminal of the operational amplifier (63b), and the source voltage of the PMOS (62b) becomes equal to the VH0 / 2 voltage. Thus, another feedback loop is formed.

Each PMOS source is connected to a constant current source (61a, 61b) set so as to pass an equal current (Ibias). Between the sources, the same resistance value as that of the matching resistor (12) in FIG. 4 is connected. A voltage-current conversion resistor (65) is connected. Since the source of each PMOS is feedback controlled to a voltage of VH0 / 2 and VDD / 2, a difference current (ΔI) proportional to the difference flows through the voltage-current conversion resistor.
Here, ΔI is expressed as ΔI = (VDD / 2−VH0 / 2) / R = (Vcal / 2) / R, and ΔI is subtracted from the current (Ibias) of the constant current source in the PMOS (62a). A current (Ibias−ΔI) flows, and a current (Ibias + ΔI) obtained by adding ΔI to the current of the constant current source flows through the PMOS (62b).

  The current flowing through the PMOS (62a) is folded by a current mirror composed of NMOS (64a, 64b) and added at the node where the drains of the NMOS (64b) and PMOS (62b) are connected. An adjustment current of (Ibias + ΔI) − (Ibias−ΔI) = 2 × ΔI = Vcal / R is output as Ical, and is output by being folded back by a current mirror composed of NMOS (66a, 66b). The circuit shown in FIG. 6 functions as the current source (43) shown in FIG. 4, and the high-level output voltage source shown in FIG. 4 constitutes (41) to give Vcal, and finally does not depend on VDD. A predetermined VHO voltage can be obtained.

  Here, although the voltage of the VH node is a high voltage close to the power supply voltage of 0.975 V, only the NMOS transistor (66b) whose source is grounded to GND is connected to this, and the drain-source described above is connected. There is no problem of inter-voltage, and an LVDS driver having a high common voltage with a low power supply voltage can be easily realized with a small-sized transistor.

  The differential signal driving circuit of the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention. For example, in the present embodiment, the case where the resistance value of the matching resistor (12) and the voltage-current conversion resistor (65) in the current adjustment circuit are made equal is described. Thus, the current consumption of the current adjusting circuit shown in FIG. 6 can be reduced by amplifying the obtained small current by changing the size ratio of the NMOS (65a) and the NMOS (65b). Is possible.

  Further, in the embodiment of the present invention, the on-resistance of the transistors constituting the switch matrix is assumed to be zero, but since the actual resistance has a finite resistance, impedance matching with the transmission line is only the resistance value of the matching resistance. Needless to say, it is also necessary to consider the on-resistance of the transistor.

  In addition, the current adjustment described above need not be performed over the entire power supply voltage range, and may be performed only for a part of the power supply voltage range as long as the output voltage and other specifications are allowed. .

  Furthermore, although the operational amplifier is used in the present embodiment, an equivalent circuit can be realized without using the operational amplifier, and in this embodiment, the difference between the VH0 voltage and the VDD voltage is converted into an Ical current in an analog manner. It will be apparent to those skilled in the art that the same effect can be obtained even if the digital control is performed as an alternative means.

11, 41... High level output voltage source, 16... Low level output voltage source, 17, 18... Voltage source, 12, 15... Matching resistor, 12 a, 12 b, 13 a, 13 b. .. Transistors forming a switch matrix, 14... Termination resistor, 43... Current source, 61a, 61b .. constant current source, 62a, 62b... PMOS transistor, 63a, 63b. 64a, 64b, 66a, 66b ... NMOS transistors

Claims (6)

A first drive signal voltage source that outputs a first voltage; a second drive signal voltage source that outputs a second voltage different from the first voltage; In the low voltage differential signal driving device having the output switching means for distributing and outputting to the second output terminal, at least one of the driving signal voltage sources includes a resistor provided between the power supply terminal and the output terminal, A low-voltage differential signal driving device comprising a current source connected to the resistor.   2. The low-voltage differential signal driving device according to claim 1, further comprising current adjusting means for adjusting a current value of the current source so that the first or second voltage becomes a predetermined voltage value.   2. The low voltage differential signal driving device according to claim 1, wherein the current adjusting means adjusts a current value based on a power supply voltage and a resistance value of the resistor.   In a differential signal transmission system comprising a low voltage differential signal driving device, a low voltage differential signal receiving device, and a transmission line connecting between the low voltage differential signal driving device, the low voltage differential signal driving device outputs a first voltage. 1 drive signal power supply, a second drive signal power supply for outputting a second voltage different from the first voltage, and an output for distributing the output of each signal power supply to the first and second output terminals, respectively. And at least one of the drive signal voltage sources is connected to a resistor having a resistance value substantially the same as the characteristic impedance of the transmission line provided between the power source and the output terminal, and the resistor. A low-voltage differential signal transmission system comprising a current source.   5. The low voltage differential signal transmission system according to claim 4, further comprising current adjusting means for adjusting a current value of the current source so that the first or second voltage becomes a predetermined voltage value.   5. The low voltage differential signal transmission system according to claim 4, wherein the current adjusting means adjusts a current value based on a power supply voltage and a resistance value of the resistor.