TWI304620B - Dielectric layer, composition and method for forming the same - Google Patents

Dielectric layer, composition and method for forming the same Download PDF

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TWI304620B
TWI304620B TW095102236A TW95102236A TWI304620B TW I304620 B TWI304620 B TW I304620B TW 095102236 A TW095102236 A TW 095102236A TW 95102236 A TW95102236 A TW 95102236A TW I304620 B TWI304620 B TW I304620B
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dielectric layer
photosensitive
composition
oxide
layer according
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TW095102236A
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TW200729350A (en
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Wei Ling Lin
Pang Lin
Tarng Shiang Hu
liang xiang Chen
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Ind Tech Res Inst
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Priority to US11/308,387 priority patent/US7829137B2/en
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Priority to US12/883,185 priority patent/US20110001221A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/478—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a layer of composite material comprising interpenetrating or embedded materials, e.g. TiO2 particles in a polymer matrix
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C24/00—Coating starting from inorganic powder
    • C23C24/08—Coating starting from inorganic powder by application of heat or pressure and heat
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Composite Materials (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Inorganic Insulating Materials (AREA)

Description

97-08-18 1304620 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種場效電晶體用之組成物、材料層 與其形成方法，且特別是有關於一種介電層以及形成此介 電層之組成物及方法。 【先前技術】97-08-18 1304620 IX. Description of the Invention: [Technical Field] The present invention relates to a composition for a field effect transistor, a material layer and a method for forming the same, and in particular to a dielectric layer and formation thereof The composition and method of the dielectric layer. [Prior Art]

場效電晶體的半導體載子傳輸，是於閘極施予電壓， 在半導體間與閘極介電層間之介面形成足夠的誘導電荷以 促使電子傳輸。為使場效電晶體於低壓操作下即擁有高電 流值iD’除了半導體之載子移鱗、通道長度比以外，尚 =料關。閘介縣賴厚愈、介電常數愈高，則電 3M公司於美國專利第μ%?% 高介電常數介電層，1 θ以太 專利中冒k出一種 料所形成的懸浮溶液來塗佈^乍、口粉體混入高分子材 所製作的介電層其表面會形成層。然而，以此法 易造成漏電路俚’岐得^ 、表面平整度不佳， 【發明内容】 L偏冋。 本發明的目的是提供一 數、低漏電流特性、高均勻户^电層，其具有高介電常 本發明的再-目的是提平整度等特性。 電流特性之介電層的製 :有高介電常數、低漏 於低溫下製作。 / 、裟程簡易、成本低且可 本發明的另— 目的是提供一 種㈣製作介電層之組成 5 1304620 97-08-18 :)正.本j ______________ —一·.—„ _________________j :呈=組，均相且成本低，可於低溫下以簡易的製程製 作具有咼”電常數、低漏電流特性之介電層。 本發明提出-種用以製作介電層之組成物， 種液態的金狀氧化物，用以做為高介麵驅滅其溶劑 以及一種感光型或非感光型高分子介質。 ” 依照本發明實施例所述，上紐㈣The semiconductor carrier transport of the field effect transistor is to apply a voltage to the gate to form a sufficient induced charge between the inter-semiconductor and the gate dielectric layer to promote electron transport. In order to make the field effect transistor have a high current value iD' under low voltage operation, in addition to the semiconductor carrier scale and channel length ratio, it is still closed. In Laijie County, Lai Houyu, the higher the dielectric constant, the 3M company in the United States patents μ%?% high dielectric constant dielectric layer, 1 θ Ethernet patents in the suspension of a material formed by a coating solution ^ The dielectric layer produced by mixing the bismuth and the port powder into the polymer material forms a layer on the surface. However, this method easily causes the leakage circuit to be defective, and the surface flatness is not good, and the content of the invention is L partial. SUMMARY OF THE INVENTION It is an object of the present invention to provide a low current leakage characteristic and a high uniformity electrical layer which has a high dielectric constant. The re-purpose of the present invention is to improve the uniformity and the like. The dielectric layer of current characteristics is produced by a high dielectric constant and low leakage at low temperatures. /, simple process, low cost and another aspect of the present invention - the object is to provide a (four) composition of the dielectric layer 5 1304620 97-08-18 :) 正. This j ______________ - one ·.-„ _________________j: = The group is homogeneous and low in cost, and a dielectric layer having a 咼"electric constant and a low leakage current characteristic can be produced in a simple process at a low temperature. The invention proposes a composition for forming a dielectric layer, a liquid gold oxide, which is used as a high interface to extinguish its solvent and a photosensitive or non-photosensitive polymer medium. According to an embodiment of the invention, the upper button (four)

= :、Zr、Ta、Si、Ba、Ge„f__: 上处感光，或非感光型高分子.介f包括聚亞醯胺、聚酸 胺、聚乙烯醇、聚乙烯紛、聚丙烯酸醋、環氧化物、聚氨 基甲酸酉旨、含氟高分子、聚石夕氧烧、聚酉旨、聚丙稀猜、聚 苯乙稀或聚乙稀*。 、本發明提出—種介電層的製造方法，此方法是將上述 組成物形成在-基底上，然後進行烘烤製程，以去除溶劑， 並使得金屬烷氧化物中的金屬形成金屬氧化物。 依照本發明實施例所述，上述烘烤製程包括一軟烤步= :, Zr, Ta, Si, Ba, Ge„f__: Upper sensitized, or non-photosensitive polymer. The medium f includes polyamidoamine, polyamine, polyvinyl alcohol, polyethylene, polyacrylic acid vinegar, Epoxide, polyurethane, fluorine-containing polymer, poly-stone, polystyrene, polystyrene, polystyrene or polyethylene*. The present invention proposes the manufacture of a dielectric layer. The method comprises the steps of: forming the above composition on a substrate, followed by a baking process to remove the solvent, and causing the metal in the metal alkoxide to form a metal oxide. According to the embodiment of the invention, the baking is performed. The process includes a soft baking step

驟及-硬烤步驟。軟烤步驟是於代至HC，或室溫至 100 C ’或至/皿至80 c的溫度下進行。硬烤步驟是於〇 〇c 至300 C’或至’里至200C，或室溫至15〇它的溫度下進行。 本發明提出-種介電層，其包括一感光型或非感光型 高分子介質以及⑽喊光型或非感光型高分子介質之中 的非晶相金屬氧化物。 依照本發明實施例所述，上述非晶相金屬氧化物包括 m Ta、Si、Ba、以或Hf的氧化物。感光型或 非感光型南分子介質包括聚亞醯胺、聚醯胺、聚乙烯醇、 6 1304 6M twf.doc/006 =稀齡、聚丙婦酸、環氧化物、聚氨酸酯、含氣 =子、聚魏燒、聚醋、聚丙稀腈、聚苯乙烯或聚乙烯。 θ =層可以做為~效電晶體及薄膜電晶體之間介電層或 疋笔容H之介電層’或應用於高頻元件中。 八本發明所形成的介電層除了包括感光型或非感光型高 二㈣之外’在感光型或非感光型高分子介質中還具有 化物。此金屬氧化物呈非晶相而非結晶相，其介電 吊间可用以提升所形成之介電層的整體介電常數。此 ，由於此金屬氧化物是由均相的組成物烘烤而成。相較 金屬氧化物顆粒摻在高分子介f中形成懸浮液 =;l $層’本發明之减物的成膜均自性佳且 的介電層其金魏化物在介質巾分佈 抗，。… 版及祕電晶體的閘介電層、電容器中 層一甚至抑應用於高頻元件中，並且所形成之二 ’包壓、咼開口率、低耗能之特性。 ’、 另外，由於形成介電層的溫度可控制在低溫 應用於可撓式基板中。 b 了 “為讓本發明之上述和其他目的、特徵和優 易懂，下文特舉較佳實施例，並配合所 鮮、 明如下。 坏附圖式，作詳細說 【實施方式】 本發明之介電層是以一種液相的組成物烘 液相組成物係由感光型或非感光型高分子介二而成。此 丨貝、有機金屬Step - hard baking step. The soft bake step is carried out on behalf of HC, or at room temperature to 100 C ' or to / to 80 c. The hard roasting step is carried out at a temperature of from 〇c to 300 C' or to from inside to 200C, or from room temperature to 15 Torr. The present invention proposes a dielectric layer comprising a photosensitive or non-photosensitive polymeric medium and (10) an amorphous phase metal oxide in a flashing or non-photosensitive polymeric medium. According to an embodiment of the invention, the amorphous phase metal oxide comprises an oxide of m Ta, Si, Ba, or Hf. Photosensitive or non-photosensitive Southern molecular media including polyamidoamine, polyamine, polyvinyl alcohol, 6 1304 6M twf.doc/006 = lean age, polyglycolic acid, epoxide, polyester, gas = child, poly Wei, poly vinegar, polyacrylonitrile, polystyrene or polyethylene. The θ = layer can be used as a dielectric layer between the dielectric and the thin film transistor or a dielectric layer of the writing capacitor H or in a high frequency component. The dielectric layer formed by the present invention has a compound in a photosensitive or non-photosensitive type polymer medium except for a photosensitive or non-photosensitive type. The metal oxide is in an amorphous phase rather than a crystalline phase, and its dielectric hanger can be used to increase the overall dielectric constant of the dielectric layer formed. Thus, since the metal oxide is baked from a homogeneous composition. Compared with the metal oxide particles doped in the polymer medium f to form a suspension =; l * layer 'the reduction of the invention is good film formation and the dielectric layer of the gold derivative is distributed in the medium towel. The gate dielectric layer of the plate and the crystal cell, and the middle layer of the capacitor are even applied to the high-frequency component, and the characteristics of the package, the opening ratio, and the low energy consumption are formed. In addition, since the temperature at which the dielectric layer is formed can be controlled to be applied to the flexible substrate at a low temperature. The above and other objects, features, and advantages of the present invention will be described in the following description of the preferred embodiments of the present invention. The dielectric layer is a composition of a liquid phase, and the composition of the liquid phase is formed by a photosensitive or non-photosensitive polymer. The mussel and the organic metal are formed.

I3046^Qtwf>d〇c/006 化合物以及溶劑所構成。感光型或非感光型高分子介質包 括聚亞醯胺(polyimide〉、聚醯胺(polyamide)、聚乙稀醇 (polyvinylalcohol)、聚乙烯酚(polyvinylphenol)、聚丙烯酸酉旨 (polyacrylate)、環氧化物（epoxy)、聚氨基曱酸酯 (polyurethane)、含氟高分子（fluoropolymer)、聚石夕氧燒 (polysiloxane)、聚酯（polyester)、聚丙烯腈 (polyacrylonitrile)、聚笨乙稀（p〇lyStyrene)、聚乙烯 (polyethylene) 〇 有機金屬化合物，為一種呈液體狀的金屬烷氧化物， 其結構為： 其中Μ包括八卜氾、&、乜、以、批、&或班，〇11為含有 1至10個碳的烷氧基，如甲氧基、乙氧基、丙氧基、異丙氧 基、丁氧基、異丁氧基、戊氧基、己氧基、庚氧基、辛氧基、 壬氧基、癸氧基' 2·曱基壬氧基、3_曱基壬氧基、4_曱基壬 ,、5_曱基壬氧基、3_乙基辛氧基、4_乙基辛氧基、“基^ 氧基、4_異丙基庚氧基、2_曱基辛氧基、 ^ 基辛氧基、3-乙基庚氧基、4-乙基庚氧基、2_;:=基4: 美4;甲乙基=氧基广乙基己氧基、2-甲基己氧基、 Ψ基錄基，基戊氧基、 2-甲基丙乳基、2_甲氧基_3_乙氧基等；η為！至$。 當有機金屬化合物為A1的烧氧化物時，I3046^Qtwf>d〇c/006 Compound and solvent. The photosensitive or non-photosensitive polymer medium includes polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, and epoxy. Epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene (p) 〇 lyStyrene), polyethylene 〇 organometallic compound, is a liquid metal alkoxide, the structure of which: Μ includes 八卜泛, &, 乜, 、, batch, & 〇11 is an alkoxy group having 1 to 10 carbons such as methoxy, ethoxy, propoxy, isopropoxy, butoxy, isobutoxy, pentyloxy, hexyloxy, g. Oxy, octyloxy, decyloxy, decyloxy ' 2 fluorenyl decyloxy, 3 fluorenyl decyloxy, 4 fluorenyl hydrazine, 5 fluorenyl methoxy, 3-ethyl Octyloxy, 4-ethyloctyloxy, "oxy", 4-isopropylisoheptyloxy, 2-nonyloctyloxy, ^yloctyloxy, 3-ethylheptyl , 4-ethylheptyloxy, 2_;:= group 4: US 4; methyl ethyl group = oxy-polyethylhexyloxy, 2-methylhexyloxy, decyl, pentyloxy, 2-methylpropane acrylate, 2-methoxy-3- ethoxy, etc.; η is ! to $. When the organometallic compound is a burned oxide of A1,

Al(OCH2CH2〇CH3)3。當有機金屬化合物為冰^ 時，其實例舍括·下M^ . 9、元氧化物 八貝例匕括.T1(oc4H9)4。當有機金屬化合物為办的燒 8 13046淡— 氧化物時，其實例包括Zi^OQHn) 4。當有機金屬化合物為Al(OCH2CH2〇CH3)3. When the organometallic compound is ice ^, the examples are given by the following M ^ . 9, the elemental oxide eight shells include .T1 (oc4H9) 4. When the organometallic compound is a burnt 813046 light-oxide, examples thereof include Zi^OQHn) 4. When the organometallic compound is

Ta的烷氧化物時，其實例包括Ta(〇C2H5)5。當有機金屬化合 物為Si的烷氧化物時，其實例包括Si(〇CH3)4。當有機金屬 化合物為Ba的烷氧化物時，其實例包括Ba(〇C4H9)2。當有 機金屬化合物為Hf的烧氧化物時，其實例包括 當有機金屬化合物為Ge的烧氧化物時，其實例包括 Ge(OC2H5)4。 ’、、 本發明之組成物中的溶劑則是用來溶解感光型或非感光 型南分子介質，使其與有機金屬化合物互溶成一均相液 體。此溶劑例如是水、甲醇(methan〇1)、乙醇(ethan〇1)、異 丙醇（isoProPano1)、丁醇（butanol)、四氳呋喃 (tetrahydrofuran)、甲醯胺(formamide)、N-曱基·2_σ比咯烷酮 (N-methylpyirolidone，ΝΜΡ)、ν，Ν-二甲基乙醯胺 (N，N-dimethylacetamide ，DMAc)、Ν，Ν-二甲基甲醯胺 (N，N-dimethylf0rma?1ide，DMF)、二曱基亞,(dime%1 sulfoxide ’ DMSO)、γ-丁内脂(r_butyr〇lact〇ne)、二曱基 2 米吐琳酉同（1，3_dimethyHimidazolidinone ，DMI) 〇 本發明之組成物可用來形成電晶體的閘介電層，茲以 下實施例來說明之。 立圖1繪示本發明之頂接觸(top contact)結構之電晶體示 意圖。圖2繪示本發明之底接觸(b〇tt〇m c〇ntact^#構之電 晶體不意圖。 —凊麥照圖1與圖2,在基板1〇〇上形成閘極1〇2,然後， 將本發明之組成物形成在電極1〇2上。基板丨⑻例如是硬 9 1304620 18758twf.doc/006 式基板如玻璃基板或是矽基板，或是可撓式基板。閘極l〇2 之材質例如是銦錫氧化物。然後，依序進行軟烤和硬烤， 將組成物中的溶劑去除，並使得有機金屬化合物中的金屬 形成金屬氧化物，以完成閘介電層104之製作。 本發明之組成物可以採用直接圖案化(direct patterning；) 的方法來形成在基板100上。或者，可以先將組成物塗佈 在基板100上，進行烘烤後，再進行圖案化。直接圖案化 的方法例如是狹缝模具式塗佈(slot die coating)、凸版印刷 法(flexographic coating)、贺墨塗佈法(inkjet printing)、微 接觸式印刷（microcontact printing)、奈米印刷 (nanoimprinting)、網板印刷(screen printing)。塗佈的方法 例如是旋轉塗佈法（spin coating)、浸泡式塗佈法（dip coating)、噴塗法(spary);圖案化的方法例如是微影、蝕刻 法、雷射蝕刻法(laserablation)。烘烤製程可以先在較低的溫 度下進行軟烤，之後，再於較高的溫度下進行硬烤。軟烤 及更烤的/ΒΠ：度與組成物中的溶劑的種類有關。軟烤的溫度 可，疋0 °C至150°C，較佳的是在室溫至1〇〇〇c之間，更佳 的疋在至溫至80°C之間。硬烤的溫度可以是〇 〇c至3〇〇c>c， 較佳的是室溫至200〇C，更佳的是室溫至15〇τ。 、之後，再形成圖案化的半導體層10ό以及源極108、 曰木〇元成如圖1所示之頂接觸(top contact)結構之電 曰脰或疋如圖2所示之底接觸伽㈤⑺^血以)結構之電 晶體。 本毛明之組成物除了可用來製作場效電晶體及薄膜電 1304620 18758twf.doc/006 晶體之閑介電層之外，還可用來製作電容器之介電層，或 是應用於高頻元件中。 實例1When the alkoxide of Ta is used, examples thereof include Ta(〇C2H5)5. When the organometallic compound is an alkoxide of Si, examples thereof include Si(〇CH3)4. When the organometallic compound is an alkoxide of Ba, examples thereof include Ba(〇C4H9)2. When the organic metal compound is a burned oxide of Hf, examples thereof include when the organometallic compound is a burned oxide of Ge, and examples thereof include Ge(OC2H5)4. The solvent in the composition of the present invention is for dissolving a photosensitive or non-photosensitive south molecular medium to be mutually soluble with an organometallic compound to form a homogeneous liquid. Such solvents are, for example, water, methanol (methan〇1), ethanol (ethan〇1), isopropanol (isoProPano1), butanol, tetrahydrofuran, formamide, N-oxime. N-methylpyirolidone (N), ν, N-N-dimethylacetamide (DMAc), hydrazine, hydrazine-dimethylformamide (N, N- Dimethylf0rma?1ide, DMF), dime%1 sulfoxide 'DMSO, γ-butyrolactone (r_butyr〇lact〇ne), dimercapto 2 m thiophene (1,3_dimethyHimidazolidinone, DMI) The composition of the present invention can be used to form a gate dielectric layer of a transistor, as explained in the following examples. Figure 1 depicts a transistor schematic of a top contact structure of the present invention. 2 shows the bottom contact of the present invention (b〇tt〇mc〇ntact^# is not intended for the transistor. - FIG. 1 and FIG. 2, the gate 1〇2 is formed on the substrate 1〇〇, and then The composition of the present invention is formed on the electrode 1 〇 2. The substrate 丨 (8) is, for example, a hard 9 1304620 18758 twf.doc/006 substrate such as a glass substrate or a germanium substrate, or a flexible substrate. The material is, for example, indium tin oxide. Then, soft baking and hard baking are sequentially performed to remove the solvent in the composition, and the metal in the organometallic compound forms a metal oxide to complete the fabrication of the gate dielectric layer 104. The composition of the present invention may be formed on the substrate 100 by direct patterning. Alternatively, the composition may be applied onto the substrate 100, baked, and then patterned. The patterning method is, for example, slot die coating, flexographic coating, inkjet printing, microcontact printing, and nanoimprinting. ), screen printing (screen p The coating method is, for example, a spin coating method, a dip coating method, or a spray method; and the patterning method is, for example, lithography, etching, or laser etching. (laserablation). The baking process can be first soft-baked at a lower temperature, then hard-baked at a higher temperature. Soft-baked and roasted/baked: degrees and types of solvents in the composition The temperature of the soft bake can be from 0 ° C to 150 ° C, preferably between room temperature and 1 ° C, and more preferably between 0 ° C and 80 ° C. Hard-baked The temperature may be 〇〇c to 3〇〇c>c, preferably room temperature to 200 〇C, more preferably room temperature to 15 〇τ. Thereafter, a patterned semiconductor layer 10 ό and a source are formed. 108. The eucalyptus element is formed into a top contact structure as shown in FIG. 1 or a bottom contact galvanic (5) (7) blood structure. The composition of the present invention can be used to fabricate a dielectric layer of a capacitor, or a high frequency component, in addition to the dielectric layer of the field effect transistor and the thin film dielectric of 1304620 18758 twf.doc/006. Example 1

請蒼照圖1，以40〇rpm/i〇秒及i〇〇〇rpm/30秒的速度， 將2〇眺％的Ta(〇C2H5)4、6wt·%的聚亞醯胺以及N-甲基-2-口比口各烧嗣或γ-丁内脂攪拌混合所形成的組成物旋塗在已形 成銦錫氧化物底電極的玻璃基板上，以形成—薄膜。然後， f攝氏80度的加熱板上軟烤，之後，再於攝氏150度的烘 =中進行硬烤，以完成閘介電層之製作。之後，再形成圖 =匕的半導體層以及源極、汲極，完成頂接觸結構之電晶 體。.之後，進行〗·ν以及c-v電性測量，其介電常數可達 遷矛夕¥μ為 〇.〇47cm2/Vs ;開/關比(0n/0ff ratio)為 1〇4 至 105。 實例2 ▲依據以上的方法形成頂接觸結構之電晶體，但紐成物 改變成30wt·%的五（乙酿丙酮)二组(Ta2(acac)5)、6破％的 亞«以及Nm対朗或γ_τ_所形成之混合 物。將形成頂接觸結構之電晶體進行π以及c_v電 常數可達6.7;遷移率_ 0.05W/Vs;開/關 以上組成物中的金屬烷氧化物是以鈕的烷氧化 來δ兄明之。本發明之其他的金屬烷氧化物，如A1、Ti、々、 ya Si、Ba、Ge或Hf的炫氧化物，亦可以採用類似上述實 和2之方絲形成組成物，進而雜烤卿成之組成物後形 11 成介電層。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示本發明之頂接觸結構之電晶體示意圖。 圖2繪示本發明之底接觸結構之電晶體示意圖。 ® 【主要it件符舰Μ】 100 :基板 102 :底電極 104 :閘介電層 ' 106 :半導體層 - 108 :源極 110 :汲極 • 12Please look at Figure 1, at 40 rpm / i 〇 及 and i 〇〇〇 rpm / 30 sec, 2%% Ta (〇C2H5) 4, 6wt·% polyimide and N- The composition formed by stirring and mixing the methyl-2-port ratio of each of the calcined or gamma-butyrolactone is spin-coated on the glass substrate on which the indium tin oxide bottom electrode has been formed to form a film. Then, f is soft baked on a hot plate at 80 degrees Celsius, and then hard baked in a baking degree of 150 degrees Celsius to complete the fabrication of the gate dielectric layer. Thereafter, a semiconductor layer of Fig. = 匕 and a source and a drain are formed to complete the electro-crystal of the top contact structure. After that, the dielectric constants of 〖·ν and c-v are measured, and the dielectric constant can reach 矛.〇47cm2/Vs; the on/off ratio (0n/0ff ratio) is from 1〇4 to 105. Example 2 ▲The crystal of the top contact structure was formed according to the above method, but the composition was changed to 30 wt.% of the five groups (Ta2(acac)5), 6%% of the sub-« and Nm対. A mixture of lang or γ_τ_. The crystal forming the top contact structure is subjected to π and c_v electric constants up to 6.7; mobility _ 0.05 W/Vs; on/off. The metal alkoxide in the above composition is alkoxylated by the knob. The other metal alkoxides of the present invention, such as the glazing oxides of A1, Ti, yttrium, ya Si, Ba, Ge or Hf, may also be formed by using a square wire similar to the above-mentioned solid and 2, and then baked into a mixture. The composition is formed into a dielectric layer. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a transistor of a top contact structure of the present invention. 2 is a schematic view of a transistor of a bottom contact structure of the present invention. ® [Main Integrity Ship] 100: Substrate 102: Bottom Electrode 104: Gate Dielectric Layer '106: Semiconductor Layer - 108: Source 110: Bungee • 12

Claims (1)

1304620 97-08-18 如年产月((f ΰ修(更}正本丨 L 十、申請專利範圍：ι ' ^ _— 1. 一種介電層的製造方法，包括： 將一組成物形成在一基底上，該組成物包括： 一金屬烧氧化物，做為高介電前驅物； 一感光型或非感光型高分子介質；以及 一溶劑；以及 進行一烘烤製程，以去除該溶劑，並使得該金屬烷氧 化物中的金屬形成金屬氧化物。 2. 如申請專利範圍第1項所述之介電層的製造方法’ 其中該金屬烧氧化物包括Al、Ti、Zr、Ta、Si、Ba、Ge 或Hf的金屬烷氧化物。 3. 如申請專利範圍第1項所述之介電層的製造方法， 其中該烘烤製程包括一軟烤步驟及一硬烤步驟。 4. 如申請專利範圍第1項所述之介電層的製造方法’ 其中該軟烤步驟是於〇°C至150°C的溫度下進行。 5. 如申請專利範圍第4項所述之介電層的製造方法’ 其中該軟烤步驟是於室溫至l〇〇°C的溫度下進行。 6. 如申請專利範圍第5項所述之介電層的製造方法， 其中該軟烤步驟是於室溫至80°C的溫度下進行。 7. 如申請專利範圍第1項所述之介電層的製造方法， 其中該硬烤步驟是於〇QC至300°C的溫度下進行。 8. 如申請專利範圍第7項所述之介電層的製造方法， 其中該硬烤步驟是於室溫至200°C的溫度下進行。 9. 如申請專利範圍第8項所述之介電層的製造方法， 13 97-08-18 j3〇462〇 - 其中該硬烤步驟是於室溫至150°C的溫度下進行。 10·如申請專利範圍第1項所述之介電層的製造方 法，其中該感^贱非感光型高分子介質包括^亞二胺、 聚醯胺、聚乙烯醇、聚乙烯酚、聚丙烯酸酯、環氧化物、 聚氨基甲酸酯、含氟高分子、聚矽氧烷、聚酯、聚丙烯腈、 聚苯乙烯或聚乙烯。 11· 一種用以製作介電層之組成物，包括： 一液態的金屬烷氧化物，用以做為高介電前驅物； •一感光型或非感光型高分子介質；以及 一溶劑。 • I2·如申請專利範圍第11項所述之用以製作介電層之 組成物，其中該液態的金屬烷氧化物包括Ai、Ti、Zr、Ta、 、 Si、Ba、Ge或Hf的金屬烷氧化物。 • 13·如申請專利範圍第11項所述之用以製作介電層之 組成物，其中該感光型或非感光型高分子介質包括聚亞醯 胺、聚醯胺、聚乙烯醇、聚乙烯酚、聚丙烯酸酯、環氧化 • 物、聚氨基曱酸酯、含氟高分子、聚矽氧烷、聚酯、聚丙 烯腈、聚苯乙烯或聚乙稀。 14· 一種介電層，包括： 一感光型或非感光型高分子介質；以及 非曰a相金屬氧化物，位於該感光型或非感光型高分 子介質中。 15·如申請專利範圍第14項所述之介電層，其中該非 晶相金屬氧化物包括A卜Ti、Zr、Ta、Si、Ba、Ge或Hf 14 1304620 97-08-18 的氧化物。 16. 如申請專利範圍第14項所述之介電層，其中該感 光型或非感光型高分子介質包括聚亞醯胺、聚醯胺、聚乙 烯醇、聚乙烯酚、聚丙烯酸酯、環氧化物、聚氨基曱酸酯、 含氟高分子、聚矽氧烷、聚酯、聚丙烯腈、聚苯乙烯或聚 乙烯。 17. 如申請專利範圍第14項所述之介電層，其中該介 電層為場效電晶體及薄膜電晶體之閘介電層或是電容器之 介電層，或是應用於高頻元件中。1304620 97-08-18 Such as the annual production month ((f ΰ修 (more} 正本丨 L X, patent application scope: ι ' ^ _ - 1. A method of manufacturing a dielectric layer, including: forming a composition in On a substrate, the composition comprises: a metal oxide oxide as a high dielectric precursor; a photosensitive or non-photosensitive polymer medium; and a solvent; and a baking process to remove the solvent, And the metal in the metal alkoxide is formed into a metal oxide. 2. The method for producing a dielectric layer according to claim 1, wherein the metal oxide oxide comprises Al, Ti, Zr, Ta, Si. 3. A metal alkoxide of Ba, Ge or Hf. 3. The method of fabricating a dielectric layer according to claim 1, wherein the baking process comprises a soft bake step and a hard bake step. The method for producing a dielectric layer according to claim 1, wherein the soft baking step is performed at a temperature of from 〇 ° C to 150 ° C. 5. The dielectric layer according to claim 4 Manufacturing method' wherein the soft baking step is a temperature from room temperature to l〇〇°C 6. The method of manufacturing a dielectric layer according to claim 5, wherein the soft baking step is performed at a temperature of from room temperature to 80 ° C. 7. The method for producing a dielectric layer, wherein the hard baking step is performed at a temperature of from 〇QC to 300 ° C. 8. The method for producing a dielectric layer according to claim 7, wherein the hard baking The step is carried out at a temperature of from room temperature to 200 ° C. 9. The method for producing a dielectric layer according to claim 8 of the patent application, 13 97-08-18 j3〇462〇 - wherein the hard baking step is The method for producing a dielectric layer according to claim 1, wherein the non-photosensitive polymer medium comprises a sub-diamine and a polyfluorene. Amine, polyvinyl alcohol, polyvinyl phenol, polyacrylate, epoxide, polyurethane, fluoropolymer, polyoxyalkylene, polyester, polyacrylonitrile, polystyrene or polyethylene. A composition for forming a dielectric layer, comprising: a liquid metal alkoxide for use as a high dielectric An electric precursor; a photosensitive or non-photosensitive polymeric medium; and a solvent. The composition of the dielectric layer as described in claim 11 wherein the liquid metal alkoxide is oxidized. The metal alkoxide of Ai, Ti, Zr, Ta, Si, Ba, Ge or Hf. The composition for forming a dielectric layer according to claim 11 of the patent application, wherein the photosensitive Type or non-photosensitive polymer medium includes polyamidamine, polyamine, polyvinyl alcohol, polyvinyl phenol, polyacrylate, epoxidized substance, polyamino phthalate, fluorine-containing polymer, polyoxyalkylene oxide , polyester, polyacrylonitrile, polystyrene or polyethylene. 14. A dielectric layer comprising: a photosensitive or non-photosensitive polymeric medium; and a non-曰a phase metal oxide in the photosensitive or non-photosensitive high molecular medium. The dielectric layer of claim 14, wherein the amorphous metal oxide comprises an oxide of A, Ti, Zr, Ta, Si, Ba, Ge or Hf 14 1304620 97-08-18. 16. The dielectric layer of claim 14, wherein the photosensitive or non-photosensitive polymeric medium comprises polyamidamine, polyamine, polyvinyl alcohol, polyvinyl phenol, polyacrylate, ring Oxide, polyaminophthalate, fluoropolymer, polyoxyalkylene, polyester, polyacrylonitrile, polystyrene or polyethylene. 17. The dielectric layer of claim 14, wherein the dielectric layer is a gate dielectric layer of a field effect transistor and a thin film transistor or a dielectric layer of a capacitor, or is applied to a high frequency component. in. 15 1304620 另7¾修说)秦皋15 1304620 Another 73⁄4 repaired) Qin Yu 97-0848 七、指定代表圖： (一) 本案指定代表圖為：圖1。 (二) 本代表圖之元件符號簡單說明: 100 :基板97-0848 VII. Designation of Representative Representatives: (1) The representative representative of the case is as shown in Figure 1. (2) A brief description of the symbol of the representative figure: 100: substrate 102 ··底電極 104 :閘介電層 106 :半導體層 108 :源極 110 :汲極 八、本案若有化學式時，請揭示最能顯示發明特徵 的化學式：102 ·· bottom electrode 104 : gate dielectric layer 106 : semiconductor layer 108 : source 110 : bungee VIII. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 44
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779415B2 (en) * 2012-11-08 2014-07-15 Eastman Kodak Company Devices containing organic polymeric multi-metallic composites
CN103871869B (en) * 2012-12-18 2016-11-16 上海华虹宏力半导体制造有限公司 The manufacture method of non-photosensitive polyimide passivation layer
TWI662709B (en) * 2014-04-07 2019-06-11 緯創資通股份有限公司 Electronic device and manufacturing method thereof
JP7356902B2 (en) * 2016-07-15 2023-10-05 ブルーワー サイエンス アイ エヌ シー． Dielectric materials for laser ablation
US10049869B2 (en) * 2016-09-30 2018-08-14 Lam Research Corporation Composite dielectric interface layers for interconnect structures
US10734505B2 (en) 2017-11-30 2020-08-04 International Business Machines Corporation Lateral bipolar junction transistor with dual base region
CN112909116B (en) * 2021-01-18 2023-08-04 华中科技大学 Field effect transistor photoelectric detector based on dielectric layer response

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170672A (en) * 1976-09-17 1979-10-09 The Japan Carlit Co., Ltd. Process for coating paper with a water soluble thermosetting resin
US4604303A (en) * 1983-05-11 1986-08-05 Nissan Chemical Industries, Ltd. Polymer composition containing an organic metal complex and method for producing a metallized polymer from the polymer composition
JPH0832304B2 (en) * 1989-08-18 1996-03-29 株式会社日立製作所 Method for forming inorganic polymer thin film
US5792592A (en) * 1996-05-24 1998-08-11 Symetrix Corporation Photosensitive liquid precursor solutions and use thereof in making thin films
WO1997006896A1 (en) * 1995-08-14 1997-02-27 Central Glass Company Limited Porous metal-oxide thin film and method of forming same on glass substrate
US6586791B1 (en) 2000-07-19 2003-07-01 3M Innovative Properties Company Transistor insulator layer incorporating superfine ceramic particles
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
US7371633B2 (en) * 2001-02-02 2008-05-13 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US6740900B2 (en) * 2002-02-27 2004-05-25 Konica Corporation Organic thin-film transistor and manufacturing method for the same
US6519136B1 (en) * 2002-03-29 2003-02-11 Intel Corporation Hybrid dielectric material and hybrid dielectric capacitor
JP2004304009A (en) * 2003-03-31 2004-10-28 Canon Inc Organic thin film transistor
US7170093B2 (en) * 2004-11-05 2007-01-30 Xerox Corporation Dielectric materials for electronic devices
US7696293B2 (en) * 2005-05-23 2010-04-13 Dow Corning Corporation Method of neutralizing polysiloxanes containing acidic residuals
US7691666B2 (en) * 2005-06-16 2010-04-06 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7465497B2 (en) * 2005-11-23 2008-12-16 General Electric Company High dielectric constant nanocomposites, methods of manufacture thereof, and articles comprising the same
US7324329B2 (en) * 2005-12-22 2008-01-29 Giner, Inc. Electrochemical-electrolytic capacitor and method of making the same
US20110006297A1 (en) * 2007-12-12 2011-01-13 Idemitsu Kosan Co., Ltd. Patterned crystalline semiconductor thin film, method for producing thin film transistor and field effect transistor

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