US20110001221A1 - Dielectric layer - Google Patents

Dielectric layer Download PDF

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US20110001221A1
US20110001221A1 US12/883,185 US88318510A US2011001221A1 US 20110001221 A1 US20110001221 A1 US 20110001221A1 US 88318510 A US88318510 A US 88318510A US 2011001221 A1 US2011001221 A1 US 2011001221A1
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dielectric layer
photo
transistor
sensitive polymer
metal oxide
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US12/883,185
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Wei-Ling Lin
Pang Lin
Tarng-Shiang Hu
Liang-Xiang Chen
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/478—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a layer of composite material comprising interpenetrating or embedded materials, e.g. TiO2 particles in a polymer matrix
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C24/00—Coating starting from inorganic powder
    • C23C24/08—Coating starting from inorganic powder by application of heat or pressure and heat
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Definitions

  • the present invention relates to a composition, material layer and method for forming the same used in field effect transistor (FET). More particularly, the present invention relates to a composition and a dielectric layer formed by the same and method for forming the dielectric layer.
  • FET field effect transistor
  • a voltage is applied to the gate, and sufficient induced charges are formed at the interface between the semiconductor and the gate dielectric layer so as to promote the carrier transmission.
  • capacitance is also involved in addition to the carrier mobility and the channel length between the source and drain electrodes. The thinner the thickness of the film of the dielectric layer is and the higher the dielectric constant is, and the higher the capacitance is.
  • 3M company provides a dielectric layer with high dielectric constant in U.S. Pat. No. 6,586,791, wherein the gate dielectric layer is formed by coating the suspended solution formed by mixing the nanometer ceramic powder into polymer material.
  • the gate dielectric layer is formed by coating the suspended solution formed by mixing the nanometer ceramic powder into polymer material.
  • stripes may be formed on the surface of the dielectric layer made by the method, and therefore, the roughness of the surface is worse, so that leakage path is easily formed to generate a high leakage current.
  • the present invention is to provide a dielectric layer having high dielectric constant, low leakage current, high uniformity, and high surface roughness.
  • the present invention provides a dielectric layer.
  • the dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide in the photo-sensitive polymer or the non-photo-sensitive polymer.
  • the amorphous metal oxide includes metal oxide, and the metal includes Al, Ti, Zr, Ta, Si, Ba, Ge or Hf.
  • the photo-sensitive polymer or non-photo-sensitive polymer includes polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene, or polyethylene.
  • the dielectric layer can be used as a gate dielectric layer of a field effect transistor and a thin film transistor or the dielectric layer of a capacitor, or the dielectric layer can be applied in high frequency devices.
  • the dielectric layer of the present invention comprises the photo-sensitive polymer or the non-photo-sensitive polymer and the amorphous metal oxide formed therein.
  • the metal oxide is at amorphous phase, rather than crystal phrase, and the dielectric constant is high, so that the metal oxide can improve the entire dielectric constant of the dielectric layer.
  • the metal oxide is formed by baking the homogeneous phase composition, compared to the dielectric layer made by the suspended solution formed by mixing the crystal metal oxide powder into polymer, the film uniformity of the composition of the present invention is better, and the metal oxide is arranged in the formed composition with better uniformity, and the composition also has better solvent resistance.
  • the dielectric layer of the present invention can be applied in the gate dielectric layers of a field effect transistors and a thin film transistor, the dielectric layer between the two electrodes in the capacitor, and even applied in the high frequency devices, and the formed device has features such as high breakdown voltage, high aperture rate and low power consumption.
  • the dielectric layer can be formed in low temperature, the dielectric layer can be applied in flexible substrate.
  • FIG. 1 is a schematic diagram of the transistor with top contact structure according to the present invention.
  • FIG. 2 is a schematic diagram of the transistor with bottom contact structure according to the present invention.
  • the dielectric layer of the present invention is formed by baking a liquid composition.
  • the liquid composition includes a photo-sensitive polymer or a non-photo-sensitive polymer, an organometallic compound and a solvent.
  • the photo-sensitive polymer or non-photo-sensitive polymer includes polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene, or polyethylene.
  • the organometallic compound is a liquid metal alkoxide, and the structure is:
  • M includes Al, Ti, Zr, Ta, Si, Ba, Ge and Hf;
  • OR is an alkoxy with 1-10 carbons, such as methoxy, ethoxy, propoxy, isopropoxy, butoxy, isobutoxy, pentyloxy, hexyloxy, heptyloxy, octyloxy, nonyloxy, decyloxy, 2-methyl-nonyloxy, 3-methyl-nonyloxy, 4-methyl-nonyloxy, 5-methyl-nonyloxy, 3-ethyl-octyloxy, 4-ethyl-octyloxy, 4-propyl-heptyloxy, 4-isopropyl-heptyloxy, 2-methyl-octyloxy, 3 -methyl-octyloxy, 4-methyl-octyloxy, 3 -ethyl-heptyloxy, 4-ethyl-heptyloxy, 2-methyl-heptyloxy, 3-
  • the embodiment thereof When the organometallic compound is an aluminum alkoxide, the embodiment thereof includes Al(OCH 2 CH 2 OCH 3 ) 3 .
  • the embodiment thereof When the organometallic compound is a titanium alkoxide, the embodiment thereof includes Ti(OC 4 H 9 ) 4 .
  • the embodiment thereof When the organometallic compound is a zirconium alkoxide, the embodiment thereof includes Zr(OC 8 H 17 ) 4 .
  • the organometallic compound When the organometallic compound is a tantalum alkoxide, the embodiment thereof includes Ta(OC 2 H 5 ) 5 .
  • the organometallic compound When the organometallic compound is a silicon alkoxide, the embodiment thereof includes Si(OCH 3 ) 4 .
  • the embodiment thereof When the organometallic compound is a barium alkoxide, the embodiment thereof includes Ba(OC 4 H 9 ) 2 . When the organometallic compound is a hafnium alkoxide, the embodiment thereof includes Hf(OC 8 H 17 ) 4 . When the organometallic compound is a germanium alkoxide, the embodiment thereof includes Ge(OC 2 H 5 ) 4 .
  • the solvent in the composition of the present invention is used to dissolve the photo-sensitive polymer or non-photo-sensitive polymer to form a homogeneous phase liquid with the organometallic compound.
  • the solvent includes, for example, water, methanol, ethanol, isopropanol, butanol, tetrahydrofuran, formamide, N-methylpyrrolidone (NMP), N,N-dimethylacetamide (DMAc), N,N-dimethylformamide (DMF), dimethyl sulfoxide (DMSO), r-butyrolactone, 1,3-dimethyl-2-imidazolidinone (DMI).
  • composition of the present invention can be used to form the gate dielectric layer of the transistor, and the following will describe the composition through the embodiment.
  • FIG. 1 is a schematic diagram of the transistor with top contact structure according to the present invention.
  • FIG. 2 is a schematic diagram of the transistor with bottom contact structure according to the present invention.
  • a gate 102 is formed on a substrate 100 .
  • the composition of the present invention is formed on the electrode 102 .
  • the substrate 100 is, for example, a rigid substrate such as glass substrate or silicon wafer, or a flexible substrate.
  • the material of the gate 102 is, for example, indium tin oxide (ITO).
  • ITO indium tin oxide
  • a hard baking process and a soft baking process are performed in sequence to remove the solvent in the composition, so that the metal in the organometallic compound convert to metal oxide so as to form the gate dielectric layer 104 .
  • the composition of the present invention can be formed on the substrate 100 using direct patterning.
  • the composition can be first coated on the substrate 100 , and a patterning process is performed after the baking process.
  • the method of direct patterning includes, for example, slot die coating, flexographic coating, inkjet printing, microcontact printing, nanoimprinting, and screen printing.
  • the method of coating includes, for example, spin coating, dip coating, and spray.
  • the method of patterning includes, for example, photolithography, etching, and laser ablation.
  • the baking process includes a soft baking process in low temperature and a hard baking process in higher temperature. The temperatures of the soft baking process and the hard baking process are related to the kind of the solvent in the composition.
  • the temperature of soft baking process may be 0° C.-150° C., and the preferred is room temperature—100° C., and the more preferred is room temperature—80° C.
  • the temperature of hard baking process may be 0° C.-300° C., and the preferred is room temperature—200° C., and the more preferred is room temperature—150° C.
  • a patterned semiconducting layer 106 , a source 108 and a drain 110 are formed, so as to complete the transistor with the top contact structure as shown in FIG. 1 , or the transistor with the bottom contact structure as shown in FIG. 2 .
  • composition of the present invention can be used to fabricate the gate dielectric layer of the field effect transistor and the thin film transistor and can also be used to fabricate the dielectric layer of a capacitor, or the composition of the present invention can also be applied in high frequency devices.
  • the composition formed by mixing the 20 wt. % Ta(OC 2 H 5 ) 4 , 6 wt. % polyimide and N-methylpyrrolidone (NMP) or r-butyrolactone, is spin coated on the glass substrate with bottom electrode of ITO thereon by speed of 400 rpm/10 s and 1000 rpm/30 s, so as to form a thin film.
  • the thin film is performed a soft baking process on the heart plate at 80° C., then, the thin film is performed a hard baking process in an oven at 150° C. to form a gate dielectric layer.
  • a patterned semiconducting layer, a source and a drain are formed, so as to complete a transistor with top contact structure.
  • I-V and C-V characteristics of the transistor are measured.
  • the dielectric constant is 5.7.
  • the mobility is 0.047 cm 2 /Vs.
  • the on/off ratio is 10 4 -10 5 .
  • the transistor with top contact structure is formed according to the aforementioned method, besides, the composition is changed to the compound formed by 30 wt. % Ta 2 (acac) 5 , 6 wt. % polyimide and N-methylpyrrolidone (NMP) or r-butyrolactone. I-V and C-V characteristics of the transistor are measured.
  • the dielectric constant is 6.7.
  • the mobility ⁇ is 0.059 cm 2 /Vs.
  • the on/off ratio is 10 4 .
  • the organometallic compound in the aforementioned composition is described by the example of tantalum alkoxide.
  • the other metal alkoxide of the present invention can also form the composition using the methods similar to the first or second embodiment, wherein the metal includes Al, Ti, Zr, Ta, Si, Ba, Ge or Hf, and, after baking the formed composition, the dielectric layer can be formed.

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  • Organic Chemistry (AREA)
  • Composite Materials (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Inorganic Insulating Materials (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)

Abstract

A dielectric layer is provided. The dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide disposed in the photo-sensitive polymer or a non-photo-sensitive polymer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional application of and claims the priority benefit of an application Ser. No. 11/308,387, filed on Mar. 21, 2006, which claims the priority benefit of Taiwan application serial no. 95102236, filed on Jan. 20, 2006. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a composition, material layer and method for forming the same used in field effect transistor (FET). More particularly, the present invention relates to a composition and a dielectric layer formed by the same and method for forming the dielectric layer.
  • 2. Description of Related Art
  • For the semiconductor carrier transmission of the field effect transistor, a voltage is applied to the gate, and sufficient induced charges are formed at the interface between the semiconductor and the gate dielectric layer so as to promote the carrier transmission. In order to that the FET has a high current ID in low voltage operation, capacitance is also involved in addition to the carrier mobility and the channel length between the source and drain electrodes. The thinner the thickness of the film of the dielectric layer is and the higher the dielectric constant is, and the higher the capacitance is.
  • 3M company provides a dielectric layer with high dielectric constant in U.S. Pat. No. 6,586,791, wherein the gate dielectric layer is formed by coating the suspended solution formed by mixing the nanometer ceramic powder into polymer material. However, stripes may be formed on the surface of the dielectric layer made by the method, and therefore, the roughness of the surface is worse, so that leakage path is easily formed to generate a high leakage current.
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention is to provide a dielectric layer having high dielectric constant, low leakage current, high uniformity, and high surface roughness.
  • The present invention provides a dielectric layer. The dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide in the photo-sensitive polymer or the non-photo-sensitive polymer.
  • According to the embodiment of the present invention, the amorphous metal oxide includes metal oxide, and the metal includes Al, Ti, Zr, Ta, Si, Ba, Ge or Hf. The photo-sensitive polymer or non-photo-sensitive polymer includes polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene, or polyethylene. The dielectric layer can be used as a gate dielectric layer of a field effect transistor and a thin film transistor or the dielectric layer of a capacitor, or the dielectric layer can be applied in high frequency devices.
  • The dielectric layer of the present invention comprises the photo-sensitive polymer or the non-photo-sensitive polymer and the amorphous metal oxide formed therein. The metal oxide is at amorphous phase, rather than crystal phrase, and the dielectric constant is high, so that the metal oxide can improve the entire dielectric constant of the dielectric layer. In addition, as the metal oxide is formed by baking the homogeneous phase composition, compared to the dielectric layer made by the suspended solution formed by mixing the crystal metal oxide powder into polymer, the film uniformity of the composition of the present invention is better, and the metal oxide is arranged in the formed composition with better uniformity, and the composition also has better solvent resistance. Therefore, the dielectric layer of the present invention can be applied in the gate dielectric layers of a field effect transistors and a thin film transistor, the dielectric layer between the two electrodes in the capacitor, and even applied in the high frequency devices, and the formed device has features such as high breakdown voltage, high aperture rate and low power consumption.
  • In addition, since the dielectric layer can be formed in low temperature, the dielectric layer can be applied in flexible substrate.
  • In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a schematic diagram of the transistor with top contact structure according to the present invention.
  • FIG. 2 is a schematic diagram of the transistor with bottom contact structure according to the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • The dielectric layer of the present invention is formed by baking a liquid composition. The liquid composition includes a photo-sensitive polymer or a non-photo-sensitive polymer, an organometallic compound and a solvent. The photo-sensitive polymer or non-photo-sensitive polymer includes polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene, or polyethylene.
  • The organometallic compound is a liquid metal alkoxide, and the structure is:

  • M(OR)n
  • wherein, M includes Al, Ti, Zr, Ta, Si, Ba, Ge and Hf; OR is an alkoxy with 1-10 carbons, such as methoxy, ethoxy, propoxy, isopropoxy, butoxy, isobutoxy, pentyloxy, hexyloxy, heptyloxy, octyloxy, nonyloxy, decyloxy, 2-methyl-nonyloxy, 3-methyl-nonyloxy, 4-methyl-nonyloxy, 5-methyl-nonyloxy, 3-ethyl-octyloxy, 4-ethyl-octyloxy, 4-propyl-heptyloxy, 4-isopropyl-heptyloxy, 2-methyl-octyloxy, 3 -methyl-octyloxy, 4-methyl-octyloxy, 3 -ethyl-heptyloxy, 4-ethyl-heptyloxy, 2-methyl-heptyloxy, 3-methyl-heptyloxy, 4-methyl-heptyloxy, 3-ethyl-hexyloxy, 2-methyl-hexyloxy, 3-methyl-hexyloxy, 3-ethyl-pentyloxy, 2-methyl-pentyloxy, 3-methyl-pentyloxy, 2-methyl-propoxy, 2-methoxy-3-ethoxy, etc.; and n is 1-5.
  • When the organometallic compound is an aluminum alkoxide, the embodiment thereof includes Al(OCH2CH2OCH3)3. When the organometallic compound is a titanium alkoxide, the embodiment thereof includes Ti(OC4H9)4. When the organometallic compound is a zirconium alkoxide, the embodiment thereof includes Zr(OC8H17)4. When the organometallic compound is a tantalum alkoxide, the embodiment thereof includes Ta(OC2H5)5. When the organometallic compound is a silicon alkoxide, the embodiment thereof includes Si(OCH3)4. When the organometallic compound is a barium alkoxide, the embodiment thereof includes Ba(OC4H9)2. When the organometallic compound is a hafnium alkoxide, the embodiment thereof includes Hf(OC8H17)4. When the organometallic compound is a germanium alkoxide, the embodiment thereof includes Ge(OC2H5)4.
  • The solvent in the composition of the present invention is used to dissolve the photo-sensitive polymer or non-photo-sensitive polymer to form a homogeneous phase liquid with the organometallic compound. The solvent includes, for example, water, methanol, ethanol, isopropanol, butanol, tetrahydrofuran, formamide, N-methylpyrrolidone (NMP), N,N-dimethylacetamide (DMAc), N,N-dimethylformamide (DMF), dimethyl sulfoxide (DMSO), r-butyrolactone, 1,3-dimethyl-2-imidazolidinone (DMI).
  • The composition of the present invention can be used to form the gate dielectric layer of the transistor, and the following will describe the composition through the embodiment.
  • FIG. 1 is a schematic diagram of the transistor with top contact structure according to the present invention. FIG. 2 is a schematic diagram of the transistor with bottom contact structure according to the present invention.
  • Referring to FIG. 1 and FIG. 2, a gate 102 is formed on a substrate 100. Then, the composition of the present invention is formed on the electrode 102. The substrate 100 is, for example, a rigid substrate such as glass substrate or silicon wafer, or a flexible substrate. The material of the gate 102 is, for example, indium tin oxide (ITO). Then, a hard baking process and a soft baking process are performed in sequence to remove the solvent in the composition, so that the metal in the organometallic compound convert to metal oxide so as to form the gate dielectric layer 104.
  • The composition of the present invention can be formed on the substrate 100 using direct patterning. Alternatively, the composition can be first coated on the substrate 100, and a patterning process is performed after the baking process. The method of direct patterning includes, for example, slot die coating, flexographic coating, inkjet printing, microcontact printing, nanoimprinting, and screen printing. The method of coating includes, for example, spin coating, dip coating, and spray. The method of patterning includes, for example, photolithography, etching, and laser ablation. The baking process includes a soft baking process in low temperature and a hard baking process in higher temperature. The temperatures of the soft baking process and the hard baking process are related to the kind of the solvent in the composition. The temperature of soft baking process may be 0° C.-150° C., and the preferred is room temperature—100° C., and the more preferred is room temperature—80° C. The temperature of hard baking process may be 0° C.-300° C., and the preferred is room temperature—200° C., and the more preferred is room temperature—150° C.
  • Next, a patterned semiconducting layer 106, a source 108 and a drain 110 are formed, so as to complete the transistor with the top contact structure as shown in FIG. 1, or the transistor with the bottom contact structure as shown in FIG. 2.
  • The composition of the present invention can be used to fabricate the gate dielectric layer of the field effect transistor and the thin film transistor and can also be used to fabricate the dielectric layer of a capacitor, or the composition of the present invention can also be applied in high frequency devices.
    • The First Embodiment
  • Referring to FIG. 1, the composition, formed by mixing the 20 wt. % Ta(OC2H5)4, 6 wt. % polyimide and N-methylpyrrolidone (NMP) or r-butyrolactone, is spin coated on the glass substrate with bottom electrode of ITO thereon by speed of 400 rpm/10 s and 1000 rpm/30 s, so as to form a thin film. Next, the thin film is performed a soft baking process on the hart plate at 80° C., then, the thin film is performed a hard baking process in an oven at 150° C. to form a gate dielectric layer. Thereafter, a patterned semiconducting layer, a source and a drain are formed, so as to complete a transistor with top contact structure. Thereafter, I-V and C-V characteristics of the transistor are measured. The dielectric constant is 5.7. The mobility is 0.047 cm2/Vs. The on/off ratio is 104-105.
    • The Second Embodiment
  • The transistor with top contact structure is formed according to the aforementioned method, besides, the composition is changed to the compound formed by 30 wt. % Ta2(acac)5, 6 wt. % polyimide and N-methylpyrrolidone (NMP) or r-butyrolactone. I-V and C-V characteristics of the transistor are measured. The dielectric constant is 6.7. The mobility μ is 0.059 cm2/Vs. The on/off ratio is 104.
  • The organometallic compound in the aforementioned composition is described by the example of tantalum alkoxide. The other metal alkoxide of the present invention can also form the composition using the methods similar to the first or second embodiment, wherein the metal includes Al, Ti, Zr, Ta, Si, Ba, Ge or Hf, and, after baking the formed composition, the dielectric layer can be formed.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (12)

1. A dielectric layer, comprising:
a photo-sensitive polymer or a non-photo-sensitive polymer; and
an amorphous metal oxide, disposed in the photo-sensitive polymer or a non-photo-sensitive polymer.
2. The dielectric layer of claim 1, wherein the amorphous metal oxide comprises metal oxide, and the metal of the metal oxide includes Al, Ti, Zr, Ta, Si, Ba, Ge or Hf.
3. The dielectric layer of claim 1, wherein the photo-sensitive polymer or the non-photo-sensitive polymer comprising polyimide, polyamide, polyvinylalcohol, polyvinylphenol, polyacrylate, epoxy, polyurethane, fluoropolymer, polysiloxane, polyester, polyacrylonitrile, polystyrene, or polyethylene.
4. The dielectric layer of claim 1, wherein a dielectric constant of the dielectric layer is about 5.7.
5. The dielectric layer of claim 1, wherein a dielectric constant of the dielectric layer is about 6.7.
6. The dielectric layer of claim 1, wherein the dielectric layer is a gate dielectric layer of a transistor.
7. The dielectric layer of claim 6, wherein a mobility μ and an on/off ratio of the transistor are 0.047 cm2/Vs and 104-105 respectively.
8. The dielectric layer of claim 6, wherein a mobility μ and an on/off ratio of the transistor are 0.059 cm2/Vs and 104 respectively.
9. The dielectric layer of claim 6, wherein the transistor is a field effect transistor.
10. The dielectric layer of claim 6, wherein the transistor is a thin film transistor.
11. The dielectric layer of claim 1, wherein the dielectric layer is a dielectric layer of a capacitor.
12. The dielectric layer of claim 1, wherein the dielectric layer is applied in high frequency devices.
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