1302652 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種監測系統，特別是關於一種監測晶 片與記憶體之傳輸狀態之監測系統。 【先前技術】 • 一般而言，當對於積體電路(integrated circuit, 1C)產品 ⑩要求功能性越高時，則相對的所設計的晶片其複雜度及所 花的人力、時間也就更多，故當已設計完成的晶片出現無 法正常運作的情形時，則必會造成公司或產業的時間、金 錢、信譽重大損失，因此系統驗證工作，可說是IC設計 過程中非常重要的一環。 晶片通常是使用電路模擬器（in-circuit emulation, ICE) 來進行驗證。在習知技術中，如圖1所示，電路模擬器12 為一塊設計複雜的電路板，用來代替晶片11上的所有功 麕當電路模擬|| 12與晶片u相電連接時，可即時監視 •曰曰片11執行所產生的結果，亦能於結果錯誤時，配合硬 ‘體中斷，強迫晶片11暫停，並檢查所有暫存器值，立即 t改任-§己憶體及暫存器内容。因此，不同晶片皆會有自 已所屬的電路模擬器來進行模擬驗證。一般來說，電路模 擬=之腳位數與晶片之腳位數會設計為相同，亦即電路模 擬裔的腳位與晶片的腳位是一對一地連結在一起。 ;、、i而為因應產品需求及開發成本之考量，同一晶片 1302652 通常會整合許多功能，晶片腳位數亦相對的減少以縮小晶 片體積。因此，當進行晶片模擬驗證時，只好再重新設計 另一套電路模擬器以搭配新開發的晶片，使得電路模擬器 的腳位與晶片的腳位也是一對一地連結在一起。如此一 來，原來的電路模擬器就没有用處，且更花費開發之金 $、時間與人力。又電路模擬器僅能澉試晶片之執行狀 I其功旎性並不高，如此更顯得重新設計電路模擬器的 浪費。 承上所述，如何提供一種能夠解決上述問題之監測系 、與方法，正是當前的重要課題之一。 【發明内容】 ^於上述課題，本發明之目的為提供—種監測系統 憶叙二同腳位數之晶片，更可監測晶片與記 監測::片依本發明之監測系統’係用於 及一暫在的 ^ 八中該晶片包含複數個第一腳位 等第-腳二儲存一暫存資料，該晶片係透過該 含-轉換模組以乂取該記憶嫌，該藍測系統包 透過該等第1位以序列傳;；模$=::，該轉換模組 試模組包含複數他 式接收該暫存資料，該測 傳輸模式自'腳位，並透過該等第二腳位以並列 據該暫存資料接收該暫存㈣，該測試模組更依 科來皿測該晶片與該記憶體間之資料傳輸，盆 Ι3Ό2652 中这=第二腳位之數量大於該等第—腳位之數量。 測一^ ’為達上述目的’依本發明之監測方法，係用於監 -每Γ二與—記㈣’其中該晶片包含複數個第一腳位及 第一el窃’該暫存器儲存一暫存資料，該晶片係透過該等 :以下舟位以序列傳輸模式存取該記憶體，該監測方法包含 :該暫力^首先’透過該等第一腳位以序列傳輸模式接收 接收：：料接者’透過複數個第二腳位以並列傳輸模式 ，記怜^存資料；以及依據該暫存資料來監測該晶片與該 己隐：間之資料傳輸’其中該等第二腳位之數量 第一腳位之數量。 承上所述’因依本發明之監測系統及方法係利用轉換 心以序列傳輸模式接收自晶片或記憶體所輸出之暫存 推然後將所接收到的暫存資料以並列傳輸模式從轉換 送至測試模組，故當需要監測之晶狀腳位數與測 腳位數不同時，即第—腳位數與第二腳位數不同 次粗:然能夠透過轉換模組正常地將於晶片所輸出之暫存 Ϊ料、^至測試模組，所以測試模組可對晶片之執行狀態 用^進行監測與除錯，因此不論任何腳位數之晶片皆可利 監測系統進行監測，以節省開發之金錢、時間與人 =提升m统之利用價值。另外，依本發明之監測 二’、可用以監測晶片與記憶體之間存取狀態之資料，並 十貧料進行監測與除錯，藉以提升監㈣統之功能性。 【實施方式】 9 1302652 以下將參照相關圖式，說明依本發明較佳實施例之監 測系統與方法，其中相同的元件將以相同的參照符號加以 說明。 請參照圖2所示，依本發明較佳實施例之監測系統2 •係用於監測一晶片23與一記憶體24,其中監測系統2則 .包含一轉換模組21以及一測試模組22。於本實施例中， :監/則系統2除了具有監測晶片23與記憶體24之間之傳輸 狀態的功能外，亦具有同時監測晶片23執行狀態的功能。 在本實施例中，記憶體24可以為一序列快閃記憶體 或一唯讀記憶體。 於本實施例中，晶片23包含複數個第一腳位232 ,並 透過該等第一腳位232以序列傳輸模式存取一記憶體24 中之> 料。測試模組22則包含複數個第二腳位221。在本 實施例中，該等第二練221之數量係大於該等第一腳位 232之數量。另外，晶片23更包含一暫存器23ι，其係用 -·以儲存一暫存資料。舉例而言，此暫存資料係為晶片23 之一執行狀態資料。 籲 j f例而言，請參照圖2所示，在本實施例中，晶片23 之該等第一腳位232可以用以傳輸序列輸入訊號幻、序列 輸出訊號SO、時脈訊號SCK以及致能訊號‘，利用這些 訊號以相傳輸模絲提供晶;i 23與記憶體24及監測系 統2之間傳輸資料使用。另外，轉換模組21係以序列傳 輸模式接收之序列輸入訊號SI、序列輸出訊號s〇、時脈 濃號SCK以及致能訊號Sen並轉換成複數個訊號，如位址 1302652 資料訊號AD0-AD7、位址訊號As-Ai9、寫入控制亂號WR、 讀取控制訊號RD、位址閂鎖致能訊號ALE以及傳輸致能 訊號PSEN，之後再以並列傳輸模式透過該等第二腳位221 輸出至測試模組22。接著，測試模組22係透過該等第二 腳位221接收位址資料訊號AD〇-AD7、位址訊號A8-A19、 : 寫入控制訊號WR、讀取控制訊號RD、位址問鎖致能訊號 :aLE以及傳输致能訊號PSEN。最後，測試模組22可以利 鲁用這些訊號進行監測、並進一步提供除錯修復的功能。 請再參照圖2所示，於本實施例中，晶片23通常會 產生一致能訊號Sen用以控制晶片23與記憶體24間之資 料傳輸。於此，致能訊號Sen同時可以經由第一腳位232 以序列傳輸模式傳送至轉換模組21，轉換模組21再以並 列傳輸模式透過該等第二腳位221傳輸至測試模組22,所 以測試模組22能夠藉此致能訊號Sen來監測晶片23之執 ' 订狀態資料，進一步地對晶片23與記憶體24來進行除錯 _ 功能。 • 請參照圖3所示，當致能訊號sen為一第一準位時， •此時記憶體24為正常模式(n〇rmal m〇de)， 亦即晶片23可 對。己憶體24做存取資料的動作。此時晶片23透過該等第 腳位232以序列傳輸模式存取記憶體24中之資料，其 中曰片 q q g 曰曰 主要是透過序列輸入訊號SI以及序列輸出訊號 S0 ^存取記憶體24中之資料，其中存取的方法說明如 下。^晶片23透過序列輸入訊號SI存取記憶體24某一位 置之貝料時，此時序列輸出訊號SO並無任何訊號。接著， 11 13 02652 =憶體24會透過序列輸出訊號so將該某一位置之資料傳 =回晶片23，此時序列輸入訊號SI並無任何訊號。藉由 =樣的特性，暫存器231中之暫存資料可透過間置的序列 ]入汛號si或是閒置的序列輸出訊號s〇傳送至轉換模組 、轉換模組21則透過該等第一腳位232以序列傳輸模 •式接收暫存資料，之後再以並列傳輸模式透過該等第二腳 _位221輸出暫存資料至測試模組22。接著，測試模組22 φ則針對暫存資料來檢測晶片23之執行狀態資料是否有錯 為。右發現暫存資料有錯時，則測試模組22會中斷晶片 23之執行動作，並對晶片23進行除錯。 _ )另外，又請再參照圖3所示，當致能訊號s如為一第 —^位時，此時記憶體24為待命模式(standby m〇de),亦 即曰曰片23不會對記憶體24做存取資料的動作。晶片23 、k該4第一腳位232以序列傳輸模式傳送暫存器中 *暫存資料至轉換模組21。而轉換模組21再以並列傳輸 屬Γ式透?該等第二腳位221將暫存資料輸出至測試模組 -2。接著測試模組22接收暫存資料並檢測暫存資料是否 :有錯。若發現暫存資料有錯時，則測試模組22會中斷晶 二，23之，行動作，並對晶片23進行除錯。在此一實施例 ’暫存器231中之暫存資料是透過序列輸入訊號SI以及 序列輸出訊號so傳送至轉換模組21。 承上所述，由於監測系統2於該等第一腳位M2與該 專第二腳位221之間設置轉換模組21，以便 模式接收驗數較少的該等第_腳位232所傳輪 12 Ι3Ό2652 . ;斗之後再利用並列傳輸模式透過腳位數較多的該等第二 ^位22輸出暫存資料至至測試模組22，因此即使於晶片 、,3腳位數增加或減少的情形時，還是可以正確地將暫存資 料提供給測試模組22以進行檢測除錯。 、”之外明參照圖4所示，本發明亦揭露一種應用 f上述監測系統2的監測方法，其制於監測-晶片與- 己，體，其中晶片包含複數個第一腳位及一暫存器，該暫 器儲存-暫存資料，並透過該等第一腳位以序列傳輸模 、存取該€憶體。依本發明較佳實施例之監測方法包含以 下步驟Stepl至步驟Step3。 接二存;:stepl透過該等第-聊位以序列傳輪模式 式接t暫透過複數個第二聊位以並列傳輪模 最後’步驟step3依據該 _記憶體間之資料傳輸 “曰片與該 第一腳位之數量。中料第一腳位之數量大於該等 之監實施例之監測方法可應用於前述 之皿測系統2’而且上述監測方法之可能實 模組以序列傳輸模式利用轉換 至測試模組，故當需列傳輸模式從轉換模組傳送 田而要Μ之晶片之腳位數—試模組腳 13 l3〇2652 夠^不同時，即第一聊位數與第二腳仅數不同時，仍然妒 換:組二常地將晶片所輪出之暫存資料傳送至匕 列與除錯，因此不論任何腳位數之 仃现 統進行監測，以節省開發之金錢、時間 》測與除錯，藉以提升此監測系統之功能性/資科進灯監 本“^料關性者°任何未脫離 #神與h ’㈣其進行之等效修改或變更，均 應匕3於後附之申請專利範圍中。 【圖式簡單說明】 圖1係顯示習知電路模擬器與晶片相連接之示意圖·, 圖2係顯示依本發明較佳實施例之監測系統之示意 圖； μ 、圖3係顯示依本發明較佳實施例之資料傳輪波形圖； 以及 圖4係顯示依本發明較佳實施例之監測方法之流程 片 元件符號說明： 11 電路模擬器 12 13026521302652 IX. Description of the Invention: [Technical Field] The present invention relates to a monitoring system, and more particularly to a monitoring system for monitoring the transmission state of a wafer and a memory. [Prior Art] • In general, when the functionality of the integrated circuit (1C) product 10 is required to be higher, the relative design of the wafer is more complicated and the manpower and time spent. Therefore, when the designed wafer fails to operate normally, it will cause significant loss of time, money and reputation of the company or industry. Therefore, the system verification work can be said to be a very important part in the IC design process. Wafers are typically verified using an in-circuit emulation (ICE). In the prior art, as shown in FIG. 1, the circuit simulator 12 is a complicated design circuit board for replacing all the functions on the wafer 11. When the circuit simulation || 12 is electrically connected to the wafer u, it can be instantly Monitoring the results of the execution of the cymbal 11 can also be used to force the chip 11 to pause when the result is wrong, to force the wafer 11 to pause, and to check all the register values, and immediately change the sufficiency - § recall and temporary storage Content. Therefore, different chips will have their own circuit simulator for simulation verification. In general, the number of bits of the circuit simulation = the number of bits of the chip will be designed to be the same, that is, the pin of the circuit analog is connected to the pin of the wafer one to one. In order to meet product requirements and development costs, the same chip 1302652 usually integrates many functions, and the number of wafer pins is relatively reduced to reduce the wafer volume. Therefore, when performing wafer simulation verification, another circuit simulator has to be redesigned to match the newly developed wafer, so that the circuit simulator's pin and the wafer's pin are also connected one-to-one. As a result, the original circuit simulator is useless, and it costs more money, time and manpower. In addition, the circuit simulator can only test the execution of the chip. The power of the chip is not high, which makes it even more wasteful to redesign the circuit simulator. As mentioned above, how to provide a monitoring system and method that can solve the above problems is one of the important issues at present. SUMMARY OF THE INVENTION In view of the above problems, the object of the present invention is to provide a monitoring system that recalls the same number of bits of the wafer, and can monitor the wafer and record monitoring:: The monitoring system according to the present invention is used for In the case of the first eight, the chip contains a plurality of first feet, and the second leg stores a temporary storage data. The chip passes through the inclusion-conversion module to capture the memory. The blue test system package transmits The first bit is transmitted in sequence;; modulo $=::, the conversion module test module includes a plurality of forms to receive the temporary data, the measurement transmission mode is from the 'foot position, and through the second position Receiving the temporary storage (4) according to the temporary storage data, the test module further measures the data transmission between the wafer and the memory according to the essay, and the number of the second foot in the basin Ι2Ό2652 is greater than the first- The number of feet. Measure a 'for the above purpose' according to the monitoring method of the present invention, which is used for monitoring - each Γ 与 and - (4) 'where the wafer contains a plurality of first feet and the first el thief' a temporary storage data, the chip accessing the memory in the sequence transmission mode by the following: the temporary method ^ firstly 'receiving and receiving in the sequence transmission mode through the first pin: : The picker's in parallel transmission mode through a plurality of second feet, remembers the data stored in the memory; and monitors the data transfer between the wafer and the hidden data according to the temporary data: wherein the second feet The number of first foot positions. According to the above description, the monitoring system and method according to the present invention uses the conversion heart to receive the temporary memory pushed from the chip or the memory in the sequence transmission mode, and then transfers the received temporary data in the parallel transmission mode. To the test module, when the number of crystal pins to be monitored is different from the number of pins, the number of bits in the first leg and the number of pins in the second pin are different: but the chip can be normally passed through the conversion module. The output of the temporary storage data, to the test module, so the test module can monitor and debug the execution status of the chip, so regardless of the number of bits of the chip can be monitored by the monitoring system to save The money, time and people of development = the value of using m. In addition, according to the monitoring of the present invention, it is possible to monitor the access status between the wafer and the memory, and to monitor and debug the poor material, thereby improving the functionality of the supervisor. [Embodiment] 9 1302652 Hereinafter, a monitoring system and a method according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals. Referring to FIG. 2, a monitoring system 2 according to a preferred embodiment of the present invention is used to monitor a chip 23 and a memory 24, wherein the monitoring system 2 includes a conversion module 21 and a test module 22. . In the present embodiment, in addition to the function of monitoring the transmission state between the wafer 23 and the memory 24, the system 2 has a function of simultaneously monitoring the execution state of the wafer 23. In this embodiment, the memory 24 can be a sequence of flash memory or a read only memory. In this embodiment, the wafer 23 includes a plurality of first pins 232, and the material in a memory 24 is accessed in a sequential transmission mode through the first pins 232. The test module 22 includes a plurality of second pins 221. In the present embodiment, the number of the second exercises 221 is greater than the number of the first feet 232. In addition, the chip 23 further includes a register 23ι, which uses -· to store a temporary data. For example, the temporary data is one of the execution status data of the wafer 23. For example, as shown in FIG. 2, in the embodiment, the first pin 232 of the chip 23 can be used to transmit a sequence input signal, a sequence output signal SO, a clock signal SCK, and an enablement. The signal ', using these signals to provide crystals by the phase transfer mode; i 23 is used to transfer data between the memory 24 and the monitoring system 2. In addition, the conversion module 21 is configured to receive the sequence input signal SI, the sequence output signal s〇, the clock pulse number SCK, and the enable signal Sen in a sequence transmission mode and convert the signal into a plurality of signals, such as the address 1302652 data signal AD0-AD7. The address signal As-Ai9, the write control WR, the read control signal RD, the address latch enable signal ALE, and the transmission enable signal PSEN, and then pass through the second pin 221 in the parallel transmission mode. Output to the test module 22. Then, the test module 22 receives the address data signal AD〇-AD7, the address signal A8-A19, the write control signal WR, the read control signal RD, the address lock lock through the second pin 221 Signal: aLE and transmission enable signal PSEN. Finally, the test module 22 can be used to monitor these signals and further provide debug repair functions. Referring to FIG. 2 again, in the embodiment, the wafer 23 generally generates a uniform energy signal Sen for controlling the data transfer between the wafer 23 and the memory 24. The enable signal Sen can be transmitted to the conversion module 21 in the serial transmission mode via the first pin 232, and the conversion module 21 is transmitted to the test module 22 through the second pin 221 in the parallel transmission mode. Therefore, the test module 22 can monitor the data of the wafer 23 by the enable signal Sen, and further debug the function of the chip 23 and the memory 24. • Referring to Figure 3, when the enable signal sen is at a first level, • the memory 24 is in the normal mode (n〇rmal m〇de), that is, the wafer 23 is correct. The memory 24 is used to access the data. At this time, the chip 23 accesses the data in the memory 24 through the first bit position 232 in a sequence transmission mode, wherein the picture qqg 曰曰 is mainly accessed in the memory 24 through the sequence input signal SI and the sequence output signal S0 ^. The data, in which the method of access is described below. When the chip 23 accesses the material of a certain position of the memory 24 through the serial input signal SI, the sequence output signal SO does not have any signal at this time. Then, 11 13 02652 = the memory 24 transmits the data of a certain position to the chip 23 through the sequence output signal so, and the sequence input signal SI does not have any signal. The temporary storage data in the temporary storage unit 231 can be transmitted to the conversion module through the intervening sequence] or the idle serial output signal s, and the conversion module 21 transmits the data through the intervening sequence. The first pin 232 receives the temporary data in a sequence transmission mode, and then outputs the temporary data to the test module 22 through the second pin_bit 221 in the parallel transmission mode. Next, the test module 22 φ detects whether the execution state data of the wafer 23 is faulty for the temporary data. When it is found that the temporary storage data is wrong, the test module 22 interrupts the execution of the wafer 23 and debugs the wafer 23. _) In addition, please refer to FIG. 3 again. When the enable signal s is a first position, the memory 24 is in standby mode (standby m〇de), that is, the cymbal 23 will not The operation of accessing data to the memory 24 is performed. The chip 23, k the first pin 232 of the 4 transfers the temporary storage data to the conversion module 21 in the serial transfer mode. The conversion module 21 outputs the temporary data to the test module -2 by parallel transmission. Next, the test module 22 receives the temporary data and detects whether the temporary data is incorrect: If it is found that the temporary data is wrong, the test module 22 interrupts the crystal two, 23, and acts to debug the wafer 23. The temporary data stored in the register 231 in this embodiment is transmitted to the conversion module 21 through the sequence input signal SI and the sequence output signal so. As described above, the monitoring system 2 sets the conversion module 21 between the first pin M2 and the second pin 221 so that the mode receives the number of the first leg 232. After the wheel 12 Ι 3 Ό 2652 . , the parallel transmission mode is used to output the temporary data to the test module 22 through the second bits 22 having a larger number of bits, so that even on the wafer, the number of 3 feet increases or decreases. In the case of the case, the temporary data can be correctly provided to the test module 22 for detecting the debug. Referring to FIG. 4, the present invention also discloses a monitoring method for the above monitoring system 2, which is applied to a monitoring-wafer and a body, wherein the wafer includes a plurality of first positions and a temporary And storing, by the temporary storage, temporary data, and transmitting the module through the first pin, and accessing the memory. The monitoring method according to the preferred embodiment of the present invention comprises the following steps Step1 to Step3. The second step is: the stepl through the first-chat bit in the sequence pass mode, t temporarily through the plurality of second chats to parallel the wheel mode last step 'step3 according to the data between the memory_" With the number of the first foot. The monitoring method of the first position of the intermediate material is larger than that of the monitoring method of the above embodiments, and the monitoring method can be applied to the above-mentioned dish testing system 2', and the possible real module of the above monitoring method is converted into the test module by using the serial transmission mode, so The number of bits of the chip to be transferred from the conversion module is required to be transmitted from the conversion module. The test module foot 13 l3〇2652 is enough. When the difference between the first chat digit and the second leg is different, it is still 妒Change: Group 2 frequently transmits the temporary data that the wafers rotate out to the queue and debug. Therefore, regardless of the number of feet, the data is monitored to save development money and time. Enhance the functionality of this monitoring system / the qualification of the lighting into the light of the "the material of the person who is not removed from the #神和h ' (4) its equivalent modification or change, should be 于3 in the attached patent application scope BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional circuit simulator connected to a wafer. FIG. 2 is a schematic view showing a monitoring system according to a preferred embodiment of the present invention; μ and FIG. a data transmission waveform diagram of a preferred embodiment of the invention; And Figure 4 shows the flow of the monitoring method in accordance with a preferred embodiment of the present invention. The components of the symbol are: 11 Circuit Simulator 12 1302652
2 監測系統 21 轉換模組 22 測試模組 221 第二腳位 23 晶片 231 暫存器 232 第一腳位 24 記憶體 Ag-Ai9 位址訊號 AD〇-AD7 位址資料訊號 ALE 位址閂鎖致能訊號 PSEN 傳輸致能訊號 RD 讀取控制訊號 SCK 時脈訊號 Sen 致能訊號 SI 序列輸入訊號 so 序列輸出訊號 Stepl 〜Step3 測方法之步驟 WR 寫入控制訊號 152 Monitoring system 21 Conversion module 22 Test module 221 Second pin 23 Chip 231 Register 232 First pin 24 Memory Ag-Ai9 Address signal AD〇-AD7 Address data signal ALE Address latch The signal signal PSEN transmission enable signal RD read control signal SCK clock signal Sen enable signal SI sequence input signal so sequence output signal Step1 ~ Step3 step WR write control signal 15