1317470 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種偵錯裝置，特別是一種應用於主機板上之 偵錯裝置。 【先前技術】 主機板為電腦最重要的元件’其中中央處理器（Central φ Processing Unit ; CPU)、記憶體、晶片組和介面卡，都安置在主 機板上的插座和插槽上。主機板上密密麻麻的線路，負責各個元 件之間的訊息傳輸’在主機板和磁碟機之間，則是透過排線來連 接，並傳送資料。在主機板上，另設置有用以連接螢幕與鍵盤等 周邊裝置的連接埠。 其中’儲存在唯讀記憶體（reacj only memory ; R〇M)中的勒 體，所謂的基本輸入輸出系統（Basic Input/〇utput; bi〇s )， 為正常啟動電腦所必須的條件。啟動電腦時，中央處理器首先根 據在主機板、齡卡等賴±祕本輸續m緒來核對每 個基礎設備是否正常，然後再進行下—步料。基本輸入輸出系 統管理最基本㈣腦I/O設傷，包括系統日期、顯示模式、軟碟 驅動裝置、硬碟_、周邊設施(如軌埠、列印埠等）、以及一些1317470 IX. Description of the Invention: [Technical Field] The present invention relates to a debug device, and more particularly to a debug device applied to a motherboard. [Prior Art] The motherboard is the most important component of the computer. The central processing unit (CPU), memory, chipset and interface card are placed on the sockets and slots on the main board. The dense line on the motherboard is responsible for the transmission of information between the components. Between the motherboard and the drive, the cable is connected and the data is transmitted. On the motherboard, another connection is provided to connect the peripherals such as the screen to the keyboard. Among them, the so-called basic input/output system (Basic Input/〇utput; bi〇s) stored in the read-only memory (RacM) is a necessary condition for starting the computer normally. When starting the computer, the CPU first checks whether each basic device is normal according to the motherboard, age card, etc., and then proceeds to the next step. The basic input and output system management is the most basic (4) brain I / O injury, including system date, display mode, floppy drive, hard disk _, peripheral facilities (such as rails, printing 埠, etc.), and some
Uancbm_Aeeess ； _ 秘取記憶體Uancbm_Aeeess ; _ Secret memory
Memoly)的設置。如果這些數據設定 無法開機或造成不轉定。A太舲Λ私山/ 系、，死有了月匕 峨疋基本輪入輸出系統為開機時重要的啟動 1317470 程式，所以-旦基本輸人輪出系/ 機。 、曰誤，系統則可能無法開 基本輸入輸出系統具體有三個 剛接通電源時對硬體部分的檢測，即所^1卩分是用於電腦 Sdf Test ’· P0ST) ’ 其功能是檢查電腦二 (Power 0n 以及對-些外部設備進行初始化和檢夠等。:、设置寄存器 數’當電腦啟動時基本輪八_== 參數，並和實際硬體裝置進行比較 會先㈤取这些 啟動。最後-個部分是引導程序，功能是^条會影響系統的 S_ ; 〇S)载人，基本輸入輸出系統先從軟碑H(〇Perating 區讀取開機記錄，如果沒細 2 ^的開始磁 如果糊機記錄會把電腦的機 系統即完成電腦系統之啟動程^ 後，基本輪入輸出 因可以清楚的知錢腦開機程序中， 本輸入輪出系統’以執行硬體的初始設定和測試，並 ΪΓΓΓ作正常後，才_取硬射有_作業系統的 硬體、_及軟體_流程後，紐異常， 並無/去確切知道三者之運作是否正常。 因此’為了解決這樣的技術問題，習知判斷電腦系統開機是 1317470 否正常’必㈣仰顯輯分析儀或是除錯卡如朗 ΓΗ卡）縣做鱗理11衫正常雜之細；使用邏= 口 貝格p貝且不易才呆作；而除錯卡的缺點是當中麥 乃至第—個錯誤碼出現後，其動體無法立即判斷 1員ί、/ ί易造成硬體與軟體問題之_錯麵淆，使得設計 人員無法明確得知系統錯誤的發生點！ =的技術進行偵錯動作時，會增加了許多額外的成本、必 =夕加其它的树以及繁_操作方法，有改進的必要。因 對主機偵錯農置來古穿，兩 十 機板出㈣，τ 開機狀態的裝置，以偵測主 曰時可以明確地判斷為軟體或是硬體的問題。 【發明内容】 有鑑於此’树供—種倾裝置及其彳貞财法，俾 === 謝央處简椒，齡該位址資料 由此·《錯裝置,即刊斷此中央處理器係正常運作。藉 、、 使"又5十人員明確地瞭解系統錯誤之發生點。 因此，本發明所揭露之偵錯裝置 較單 係執行開機程序時，擷取中㈣m <止比&早70 ’ 斷，此翻继恶 达出之位址資料作比較判 元，接收::#利用位址比較單元達織之目的。位址比較單 《中央處理器所送出之位址資料，此位 :者疋否_，即可觸主機板職是否正常。 藉由本發日骑如之倾裝置，能正確且迅速地觸中央處 1317470 理器之運作是否正常’使研發人員或制者能财楚地辨認系統 錯誤之發生點。在實錯裝置時，只要位址峨單元作 為判斷的_電路，賴要胸加額相電子藉。此外，應用 在不同系統之處理n架構上，亦可_倾之功效。 、下在實⑭方式中3杨敘述本發明之詳細特徵以及優點，其 内容足以使任何熟習侧技藝者了解本發明之技術内容並據以實 施，且根據本綱書所揭露之内容、申請補綱及圖式，任何 熟習相關技藝者可輕易地理解本發明相關之目的及優點。 【實施方式】 為使對本發明的目的、構造、特徵、及其功能有進一步的瞭 解、，兹配合實施例詳細說明如下。以上之關於本發明内容之說明 及以下之實施方式之說嗎肋示範與解釋本發明之原理，並且 提供本發明之專利申請範圍更進一步之解釋。 睛參照「第1圖」，縣本發明之祕雜圖，其細在電腦 系統的主機板，於_程序中_電腦纽之基礎設備（包含硬 體與軟體）是否正常開機運作，其中主機板包含有中央處理器 刚、晶片組(ChiPset)120、資料匯流排13〇、基本輸出輸入系統 140以及位址比較單元15〇等。 中央處理器100 ’可以是—單核心或是雙核心之處理器十 制整個電腦運作，其内部包括控制單元、算術及邏輯單元、健 器或記憶單元。當電腦系統開始運作時，中央處理器100從記憶 體内’讀取操作它的軟體之指令與資料，透過運算邏輯單^ 1317470 LGgie Unit;⑽）運算出結果後存回記憶體，同時 由主機板與外界的輸出入周邊裝置溝通，以進行資料處理。 ，行下—步程序，因此，執行開機程序 :、,、处理益100會項取儲存在程式指標暫存器⑽内之位址資 '会亚且經由晶片、组120再透過資料匯流排130傳向基本輸出輸 入系統140，此位址_係細基礎設備之紐。於本發明之一 具體實施财，此晶版12〇料南橋晶丨。 基本輸入輸出系統H0，與晶片組12〇她接，用以與中央 處理器1〇〇相溝通。此基本輸入輸出系統14〇管理最基本的電腦 糸統輸出輸人設備，包㈣統日期、顯賴式、軟碟鷄裝置、 硬碟類型、周邊設備、以及一些記憶體和快取記憶體的設置；當 電腦系統職後’基本輸人輪出纽14G最先被啟動，絲它會 對電腦系統的基礎設備進行檢驗和測試，並回應中央處理器^ 所送出的位址雜，雜址資料相絲基本輸人輸料統⑽中 的系統管理程式之初始紐，當基本輸人輸㈣統14()接收到此 位址資料時，利用儲存於基本輸入輸出系統140中的系統管理程 式’開始執行對基礎設備的參數設定。 -位址比較單元150 ’可運用主機板上現成的複雜可程式邏輯 几件（Complex Programmable Logic Device ; CPLD)、場效可程式 化間陣列（Field ProSrammable Gate Array ; FPGA)、或膠合邏輯 1317470 (Gluelogic)等具有可編輯程式的元件，不需要增加額外的電子 元件即可實現本發明，且當要對其它各種主機板之中央處理器1〇〇 作測試時，只須賤有LPC/FWH之資龍_ 13G介面即可作 連接測試。位址比較單元150可以透過超高規模積體電路硬體描 述浯“ VHSIC Hardware Description Language; VHDL ；) % Veribg 等硬體描述語言，將關（ANDGate)、綱（QRGate)及電阻 器（Register)以陣列模組化成具功能之元件，因此，位址比較單 π 150可擷取中央處理器1〇〇所送出之位址資料與基本輸入輸出 系統HG之預定紐17〇，再進行兩者相互比較，若相符合即 可判斷中央處理器100係為正常。 根據本發明之-具體實施例，於電腦系統之主機板上，當主 機板被下達開機或重置（reset)指令時，經由電源觸發使得主機 板開始工作，中央處理器100首先根據主機板、顯示卡等設備上 的設定參數來核對每個基礎設備是否正f，然後再進行下一步程 Φ序，依據執行開機程序會送出儲存於指標暫存器110中之位= 料，而此位址資料係指向一基礎設備之位址。 中央處理器透過晶片組120如南橋晶片，用以與周邊硬 體相溝通，而基本輸出輸入系統14G於電腦系統開機後， 啟動，然後它會對電麻_設備進行檢驗助m，並回 =了 100所达出的位址資料，此位址資料相應至基本輸出輸二 =統⑽中的預定位址削，此趣錄m係為_理 之初始紐，糊儲存於基本輪出輸4統⑽中的純管理程 1317470 • 式，開始執行對基礎設備參數的設定。 晶片組12〇藉由資料匯流排130分別將基本輸出輪入系統14〇 與位址比較單元150相麵接’其中此資料匯流排係為'低腳位 數(LowPin Count;LPC)匯流排或是韌體控制中樞單元(Memoly) settings. If these data settings cannot be turned on or cause no conversion. A is too private mountain / system, and there is a month of death. The basic wheel-in output system is the important start-up 1317470 program, so the basic input is out of the system. The system may not be able to open the basic input and output system. There are three tests for the hardware part when the power is first turned on, that is, the ^1 is used for the computer Sdf Test '· P0ST) ' Its function is to check the computer Second (Power 0n and some external devices are initialized and checked, etc.: Set the number of registers' When the computer starts up, the basic round eight _== parameters, and compare with the actual hardware device will first (5) take these start. The last part is the boot program. The function is that the ^ will affect the system's S_; 〇S) manned, the basic input and output system first reads the boot record from the soft monument H (〇Perating area, if there is no fine 2 ^ start magnetic If the paste machine record will complete the computer system's startup process ^, the basic wheel input and output can be clearly known in the brain start program, this input rounds out the system 'to perform the initial setup and test of the hardware After the normal operation, the _ take hard shot has _ operating system hardware, _ and software _ process, the button is abnormal, there is no / to know exactly whether the three are operating normally. So 'to solve this technology The problem, the conventional judgment computer system boot is 1317470 whether it is normal 'must (four) Yang Xian series analyzer or debug card such as Langka) county to do the scales 11 shirts are normal and fine; use the logic = mouth Beige p shell and It is not easy to stay; the shortcoming of the debug card is that after the emergence of the first error code, the dynamic body can not immediately judge the 1 member ί, / ί is easy to cause the problem of hardware and software confusing, making the design People can't clearly know where the system error occurred! When the technology is debugging, it will add a lot of extra cost, must be added to other trees, and the traditional method of operation, there is a need for improvement. Because the host debugs the farmer's equipment, the two machines are out (four), and the device with the τ power-on state can clearly determine the problem of software or hardware when detecting the master. [Summary of the Invention] In view of this 'tree supply-type tilting device and its wealth management method, 俾=== Xie Yang is a simple pepper, the age of the address data from this "wrong device, that is, the central processor is published It works normally. Borrow, and let the "50" personnel clearly understand the point of occurrence of system errors. Therefore, when the debugging device disclosed in the present invention performs the booting process in a single system, the middle (4) m < the ratio is > the early 70' break, and the address data of the surviving evil is compared and judged, and receives: : #Using the address comparison unit to achieve the purpose of weaving. Address comparison list "Address data sent by the central processor, this bit: If you do not _, you can touch the host board is normal. With this launching device, it is possible to correctly and quickly touch the center of the 1317470. The operation of the processor is normal. This allows the developer or the manufacturer to identify the occurrence of the system error. In the case of a real-time device, as long as the address 峨 unit is used as the _ circuit of the judgment, it is necessary to add the electrons to the chest. In addition, the application can be used in the processing of different systems. The detailed features and advantages of the present invention are described in the following. The content of the present invention is sufficient for any skilled person to understand the technical contents of the present invention and implement it according to the contents disclosed in the present application. The objects and advantages of the present invention are readily understood by those skilled in the art. [Embodiment] In order to further understand the objects, structures, features, and functions of the present invention, the embodiments will be described in detail below. The above description of the present invention and the following embodiments are intended to illustrate and explain the principles of the invention, and to provide further explanation of the scope of the invention. Eyes refer to "1st picture", the secret map of the invention of the county, which is detailed on the motherboard of the computer system, in the program _ computer _ basic equipment (including hardware and software) is normal boot operation, which motherboard It includes a central processing unit, a chipset (ChiPset) 120, a data bus 13 〇, a basic output input system 140, and an address comparison unit 15A. The central processing unit 100' can be a single-core or dual-core processor that operates throughout the computer and includes a control unit, an arithmetic and logic unit, a health or a memory unit. When the computer system starts to operate, the central processing unit 100 reads the instructions and data of the software that operates the memory from the memory, and calculates the result through the arithmetic logic unit 13 13470 LGgie Unit; (10)) and stores the result back to the memory, and at the same time, the host The board communicates with the outside world's output into the peripheral device for data processing. Step-by-step procedure, therefore, the boot process is executed:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, It is passed to the basic output input system 140, which is the link of the fine basic equipment. In one embodiment of the present invention, the crystal plate 12 is made of Nanqiao Jingyu. The basic input/output system H0 is connected to the chipset 12 for communication with the central processing unit. The basic input/output system 14〇 manages the most basic computer system output and input devices, including (4) date, explicit, floppy device, hard disk type, peripheral device, and some memory and cache memory. Setting; when the computer system is in charge, the basic input wheel 14G is first started, it will check and test the basic equipment of the computer system, and respond to the address and miscellaneous data sent by the central processor ^ The initial link of the system management program in the phase input system (10) is used as the system management program stored in the basic input/output system 140 when the basic input (4) system 14 () receives the address data. Start the parameter setting of the base device. The address comparison unit 150' can utilize a complex Programmable Logic Device (CPLD), a Field ProSrammable Gate Array (FPGA), or a glue logic 1317470 (on the motherboard). Gluelogic) and other components with editable programs, the invention can be implemented without adding additional electronic components, and when testing the central processor 1 of various other motherboards, only LPC/FWH is required. The Zilong _ 13G interface can be used for connection testing. The address comparison unit 150 can describe the hardware description language such as "VHSIC Hardware Description Language; VHDL;) % Veribg through the ultra-high-scale integrated circuit hardware, and the ANDGate, QRGate, and Resistors are registered. The array is modularized into functional components. Therefore, the address comparison single π 150 can capture the address data sent by the central processing unit 1 and the predetermined threshold of the basic input/output system HG, and then perform mutual In comparison, if the content is consistent, it can be judged that the central processing unit 100 is normal. According to the embodiment of the present invention, on the motherboard of the computer system, when the motherboard is powered on or reset, the power is passed through the power supply. The triggering causes the motherboard to start working. The central processing unit 100 first checks whether each basic device is positive according to the setting parameters on the device such as the motherboard and the display card, and then proceeds to the next step, and sends the storage according to the execution booting procedure. The bit in the indicator register 110 = material, and the address data is directed to the address of a basic device. The central processor uses the chip set 120, such as a south bridge chip, In order to communicate with the surrounding hardware, the basic output input system 14G is started after the computer system is turned on, and then it will check the electric _ equipment, and return = 100 address information, this bit The address data is corresponding to the predetermined address in the basic output input==(10). This interesting record m is the initial value of the _ rationality, and the paste is stored in the pure management process 1317470 in the basic round output system (10). The setting of the basic device parameters is performed. The chipset 12 分别 the basic output wheeling system 14 〇 is connected to the address comparing unit 150 by the data bus 130, wherein the data bus is ranked as the low pin number ( LowPin Count; LPC) bus or firmware control hub unit (
Hub ; FWH)，此lpc/fwh之資料匯流排13〇介面一般應用於儲 存與傳送個人電腦、筆記型電腦、硬碟和光碟儲存應用中的基本 輸入輸出系統程式碼，並且具有低耗電量、高效能、高穩定^的 • 特性以及線路簡單於設計上容易實現之優點。 請參照「第2圖」’係為資料串之時序圖，依據Lpc/FwH之 協定規格，於資料匯流排130傳送中央處理器1〇〇所送出之資料 串中包含位址資料，此資料串係由二十一個時脈（d〇ck)而構成 多個攔位，並從起始攔位算起之第三個攔位係用來存放位址資 料’此位址攔位可在八個時脈間讀取，於此，位址比較單元15〇 可透過傳輸協定將此資料串中之位址資料擷取出來，並相互比較 •此位址資料與預定位址170二者是否相同，而後將其比對結果利 用七段_||、蜂鳴H或是發光二極料不同表示方式之指示器 〇輸出其比對結果若相符合，則表示中央處理器觸為正常 …請參m圖」，絲本發日州貞錯綠技糊，應用於 之主機板上，對域板之基礎設備（包含賴與軟體） 進行偵錯，偵錯步驟如下。 服電㈣、統之電源觸發，主機板·執行賴動作， 1317470 IS:::，要根據在主機板、顯示卡等設備上的基本輸 料來核對每個基礎設備是否正常，然後再 二’並送出位址資料，此位址資料係指向—基礎設備之 址-^本輸入輪4系統140即接收此中央處理器謂送出之位 址資料（步驟300)。 1 著^本輸入輪出系統刚於電腦開機後，它會對電腦的 =仃檢，和測試，並回應中央處理器ι〇〇所送出的位址資 二〜位址貝料相應至基本輸人輸出系統⑽的預雜址⑺， /預疋位址170係麵統管理程式之初始位址，當基本輸 =14!接收到此位址資料時，利用儲存於基本輸入輸出系統MO 、…統官理程式’開域行雌礎設備的參數設定。而後，位址 比較單元150藉由資料匯流排13〇分別擷取中央處理器鹰之位 =資料與基本輸續“統_之默位址m，並比較此位址 貝，與預定位址m是否相符合（步驟⑽）。最後，當位址比較 符合時，判定中央處理器1⑻為正常運作（步驟320)，i中更 可利用指示器輸出此比對結果。 本發明另—實施例係將此位址比較單元15G以製作為擴充卡 的方式裝設於主機板之預設插槽，並透過指示器⑽顯示傭結 果’亦可以達成本發明之功效。 雖然本發似前述之較佳實施·露如上，然其並非用以限 定本^明，任何熟習相像技藝者’在不脫離本發明之精神和範圍 内田可作些許之更動與潤飾，因此本發明之專利保護範圍須視 12 1317470 本說明書所附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係為本發明之一具體實施例示意圖； 第2圖係為資料串之時序圖；及 第3圖係為本發明之偵錯方法之流程圖。 【主要元件符號說明】Hub; FWH), this lpc/fwh data bus 13 interface is generally used to store and transfer basic input and output system code in PC, notebook, hard disk and CD storage applications, and has low power consumption High performance, high stability, and features are simple to design and easy to implement. Please refer to "2nd figure" as the timing chart of the data string. According to the protocol specification of Lpc/FwH, the data stream sent by the central processing unit 1 in the data bus 130 is included in the data string, which is included in the data string. It is composed of twenty-one clocks (d〇ck) to form multiple interceptions, and the third interceptor from the initial intercept is used to store the address data. Inter-clock reading, where the address comparison unit 15 can extract the address data in the data string through the transmission protocol and compare with each other. • Whether the address data and the predetermined address 170 are the same. Then, the comparison result uses the seven-segment _||, buzzer H or the indicator of the different representation of the illuminating diode, and if the result of the comparison is consistent, it means that the central processor touches the normal... m map", the silk is issued by the Japanese state of the wrong green technology paste, applied to the motherboard, the basic equipment of the domain board (including Lai and software) to debug, the debugging steps are as follows. Service power (four), system power supply trigger, motherboard board implementation, 1317470 IS:::, according to the basic material on the motherboard, display card and other equipment to check whether each basic equipment is normal, and then two And sending the address data, the address data is directed to the address of the base device - the input wheel 4 system 140 receives the address data sent by the central processor (step 300). 1 ^ This input wheeling system just after the computer is turned on, it will check the computer's = check, and test, and respond to the address sent by the central processor ι〇〇2 to address the material to the basic input The pre-mesh address (7) of the human output system (10), / the pre-existing address 170, the initial address of the system management program, when the basic input = 14! When receiving the address data, the use is stored in the basic input and output system MO, ... The official program is to set the parameters of the female equipment in the domain. Then, the address comparison unit 150 obtains the position of the central processor eagle = data and the basic transmission contiguous address m by means of the data bus 13 and compares the address with the predetermined address m. Whether it is consistent (step (10)). Finally, when the address comparison is met, it is determined that the central processing unit 1 (8) is in normal operation (step 320), and the comparison result is outputted by the indicator in i. The other embodiment of the present invention The address comparison unit 15G is installed in the preset slot of the motherboard in the manner of being made into an expansion card, and the commission result is displayed through the indicator (10). The effect of the present invention can also be achieved. The above disclosure is not intended to limit the scope of the invention, and any skilled person can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention is subject to 12 1317470. BRIEF DESCRIPTION OF THE DRAWINGS The following is a schematic diagram of one embodiment of the present invention; FIG. 2 is a timing diagram of a data string; and FIG. for The method of debugging a flowchart of the invention. The main element REFERENCE NUMERALS
100 中央處理器 110 指標暫存器 120 晶片組 130 資料匯流排 140 基本輸出輸入系統 150 位址比較單元 160 指示器 170 預定位址 13100 Central Processing Unit 110 Indicator Register 120 Chipset 130 Data Bus 140 Basic Output Input System 150 Address Comparison Unit 160 Indicator 170 Pre-Positioned Address 13