TWI301043B - - Google Patents

Description

</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; [Prior Art] Referring to Fig. 1 ''a conventional multilayer circuit board includes a conductive layer unit 5 and an insulating layer unit 6. The conductive layer unit 5 is made of (d) and is used for transmitting signals, grounding, and supplying power, and has a conductive layer of at least three-phase stacked layers. The insulating layer unit 6 has at least a de-suppressed &amp; ^ male main less one clasping layer 61, respectively sandwiched between the two conductive guide layers of the conductive layer, two adjacent guides #q 卜, 4 states, etc. between. Each of the insulating layers is semi-transparent and is used to prevent the short-circuit or only interference between the conductive layers of the conductive layer unit and the conductive layer 51. Generally, the conductive is used to become π &lt; The number of conductive layers 51 of 兀5 is called to the multi-layer circuit board. For example, when the electric layer of Lei Zhanshi Qiao has five conductors, the layer 51 is called a six-layer circuit board. When the lithography of the multi-layer circuit board conductive layer unit 5 is in the wrong order, the coil that transmits the signal will cause the old screen to change. The relationship of the u layer changes, and the characteristic impedance (enstic lmpedance) shifts. It is the electromagnetic thousand-photograph between the main circuit, the production cost and time. Self-made, butterfly destroyed, waste a lot of raw see Figure 2, the Republic of China patent announcement number to test the structure of the unstacked circuit board stacking sequence. 5, the layer circuit board as an example, the dry) has /, from the top to the bottom of the mask unit 6 is formed with five eight ^ + # $ $ ¥ 黾 layer 51. The insulation layer /, there are five respectively The insulating layer 61 between the leads 51. 9 early 70 5 or two adjacent conductive layers, the structure comprises The two rectangular viewing holes 10 and the two verification structures 3 are respectively formed at the same relative position of the two outermost conductive layers 51. Each of the viewing angles 10 includes a second-area viewing area. The two verification structures 30 are respectively disposed at the same relative position of the inner conductive layer Η and the two viewing areas 12 and 14, and the recording order is shifted downward-the conductive layer 51. Each-verification structure 3α includes- ± shaded block Η, two

The 1301043 indicator mark 33 and the lower masking block 35 are sequentially disposed from top to bottom on any of the three continuous conductive layers 51 located on the inner side. The upper and lower shielding blocks η, 35 respectively shield half of the viewing area 12, 14 and are arranged in a misalignment. When the stacking order of the six-layer circuit board conductive layer unit 5 is correct; the indication mark 33 appearing from the upper or lower (four) view hole ίο is partially obscured by the upper and lower concealing areas 3 1 and 3 5 , such as 1 ^ as shown in Figure 3. When the stacking order is wrong, at least one of the indicator marks 33 appearing from the upper or lower viewing aperture 10 may not be obscured or completely obscured. Since the method is such that the insulating layer 61 is translucent to be transparent, the stacking order of the multilayer circuit board conductive layer 5 can be judged to be erroneous in the illumination 忖' by manually checking the index marks. When the number of layers of the board is continuously increased, the transmittance is getting worse and worse, which causes difficulty in manual inspection. In addition, the United States Patent Publication No. 5651/4 discloses a superimposed detecting device for a multi-layer circuit board. The protective layer (4) conductive layer single A 5 conductive layer 51 of the identification number Η and the edge layer unit 6 insulation layer "thickness difference" in the stacking process, while monitoring the current stack of identification marks and: If the thickness f does not match the preset value, it is judged whether there is an error in the stacking order of the multilayer circuit board. 1301043 The progress of the layer sequence will cause the device to check whether there is an error, and the purchase will cause an increase in cost. With the 尺寸;, the size and thickness of the multilayer circuit board are getting smaller and smaller, and the requirements for the detection are getting higher and higher. When the accuracy of the detecting device is: Undetectable. [Invention] Therefore, the object of the present invention , that is, in the order of stacking you catch 1, a verifiable stack ^

The board 's can directly measure the characteristic impedance of the Thunder &amp; Private board itself to check if the order is wrong. In the present invention, the circuit board for verifying the lamination sequence of the present invention comprises a conductive acoustic unit, an insulating layer unit and a measuring unit.曰 The conductive layer unit has a conductive layer of at least three phases stacked. The insulating layer unit has at least -Sauer s v , another 芏 / an insulating layer respectively sandwiched between any two adjacent conductive layers of the conductive layer unit. The measuring unit comprises an equal width measuring line, a complete continuous reference surface and a gap 'the measuring line, the reference surface and the gap are respectively arranged in sequence on any three consecutive conductive layers of the conductive layer unit The same relative position, and the wire frame is limited to a projection area of the gap. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Before the present invention is described in detail, it is to be noted that the same elements in the following description are denoted by the same reference numerals. 7) 43. Referring to Figure 4, the present invention verifies the lamination sequence - an example of the direct resistance of the measuring plate itself and at least the measuring unit 4 (α dry: 绝缘 insulating layer unit 6 is described). (The picture is only taken out - the measuring unit 4, so that the conductive layer 715 is used for transmitting signals, grounding and supplying power, and 'having at least two-phase stacked conductive layer 51. The insulating layer unit 6 having at least two insulating layers 61 respectively sandwiched between any two adjacent conductive layers 51 of the h-layer unit 5. Each of the insulating layers ... is a short-circuit or short-circuit or signal interference between adjacent conductive layers 51. The Δ measuring unit 4 includes a measuring line 41 of equal width, a complete continuous, a test surface 42 - a gap 43 and two measuring points, 45 respectively connected to the measuring line 41 and the reference surface 42. The measuring line 41, the reference surface π and the gap 43 are respectively disposed at any three consecutive conductive and opposite positions of the conductive layer unit $, and the measuring line 41 is limited to the gap 43 and the area. Two measuring points 44, 45 are disposed on one of the two outermost conductive layers 51. Each of the inner conductive layers is at least placed with the signal line 41, the reference surface 42 and the gap. One of the 43 〇 _ "The line 41 can be a line for testing, and the guide layer 70 can also be utilized. 5 original line for transmitting signals to save the area occupied by the measuring unit 4 on the circuit board. The gap 43 may also be the same shape and relative position as the measuring line 41, but The width of the measurement line 41 is not less than the width of the measurement line 41. 1301043 ^ The equal-points 44, 45 can directly measure the measurement unit 4, and if the measured characteristic impedance shifts to a normal value (ie, the electricity: The impedance value can be calculated when the board is designed. (4) "The stacking order of the conductive layer of the circuit board is 5, and the stacking order of the circuit board is wrong. It must be (4) travel _ step (4) check processing. The following shows the stacking order of the conductive layer unit 5 of the board is wrong. How to cause the characteristic impedance of the measurement unit to shift to a normal value. Referring to Figures 5 to 7, the measurement line 41 of the measurement unit 4 and the reference surface 42 constitute a transmission line (Transmissi〇n Line), which is located in the measurement. The layer, one side or the side, the ba, the 彖 layer 61 constitutes a dielectric film 49, and a characteristic impedance can be measured between the measuring line 41 and the reference surface 42. "&gt; The characteristic line 41 is disposed when the two are located in the outermost conductive layer 51, and the characteristic impedance uses the surface. The Surface Microstrip model is estimated to be affected by the width w and the thickness T of the measuring line 4i and the thickness η of the dielectric 臈49 and the dielectric constant (7) 心 ( (5) (10) 咖 sr. 7. When the measuring line 41 is placed on the inner side of the pen layer 51, the singular characteristic impedance is used by the embedded microstrip (Embedded)

The Microstrip model or the offset strip line model estimates the width w and thickness T of the line 41 in FIG. 3, the thickness H of the dielectric film 49, and the dielectric constant ^ and the measurement. The distance H1 of the line 41 from the reference surface 42 is affected. The difference between the two models is that the offset stripline model has more reference planes 42 of the other measurement unit 4 than the embedded microstrip model. When the stacking order of the circuit board conductive layer unit 5 is wrong, the thickness 该 of the dielectric film 49 or the distance hi of the measuring line 41 from the reference surface 42 may increase by 1301043, or a model for estimating the characteristic impedance. Will change, causing the characteristic impedance to shift to a normal value. The characteristic impedance of the transmission line of the board can be adjusted to match the impedance inside the terminal component (such as the central processing unit or memory) to reduce the reflected noise to reduce noise interference and avoid malfunction. Since the matching of the transmission line and the terminal component affects the transmission quality, the measurement of the characteristic impedance of the transmission line is a necessary procedure after the board is completed, and the time domain is used.

Time Domain Reflectometer (TDR) is used for measurement. In order to present the preferred embodiment more clearly, three examples are illustrated below. Referring to Figure 4, the first example is a four-layer circuit board comprising a conductive layer 兀5, an insulating layer unit 6, and a measuring unit 4. The conductive layer unit 5 has a four-phase stacked conductive layer 51, which is a -first conductive layer 511, a second conductive layer 512, a first: a conductive layer 5U and a fourth conductive layer 514, respectively. The insulating layer unit 6 has three insulating layers respectively sandwiched between any two adjacent conductive layers 51 of the conductive layer.

The measuring line 41 of the measuring unit 4 is disposed on the first conductive layer 511. The reference surface 42 is disposed on the second conductive layer 512, and the gap Μ is disposed on the third conductive layer 513. The two measuring points 44, 45 are disposed on the first conductive layer 511. Referring to Figures 4 and 5', the characteristic impedance of the measuring unit 4 can be estimated using a surface microstrip model. When the second conductive layer 512 is interchanged with the third conductive layer 513, the measuring line 41 passes through the gap 43 and the reference surface 42' causes the thickness Η of the dielectric film 49 to increase, and the characteristic impedance becomes large. 10 1301043 Referring to FIG. 8, the second example is a six-layer circuit board comprising a conductive layer unit 5, an insulating layer unit 6, and two measuring units 4. The conductive layer unit 5 has a six-phase stacked conductive layer 51, which is a first conductive layer 511, a second conductive layer 512, a third conductive layer 513, and a fourth conductive layer along the stacking side β direction. 514, a fifth conductive layer 515 and a sixth conductive layer 516. The insulating layer unit 6 has five insulating layers 61 interposed between the two adjacent conductive layers 51 of the conductive layer unit 5, respectively. The two measuring units 4 are respectively a first measuring unit 46 and a second quantity &gt; measuring unit 47. The measuring line 41 of the first measuring unit 46 is disposed on the first conductive layer 511. The reference surface 42 is disposed on the second conductive layer 512. The gap 43 is disposed on the third conductive layer 513. The two measuring points 44, 45 are disposed on the first conductive layer 51. The measuring line 41 of the second measuring unit 47 is disposed on the fifth conductive layer 515. The reference surface 42 is disposed on the fourth conductive layer 514. The gap 43 is disposed on the third conductive layer 513. The two measuring points 44, 45 are disposed on the sixth conductive layer 516. The first and second measuring units 46, 47 are arranged in a wrong position. Referring to Figures 6 and 8, the characteristic impedance of the second measuring unit 47 can be estimated using the embedded microstrip model. When the third conductive layer 513 is interchanged with the fourth conductive layer 514, the measuring line 41 of the second measuring unit 47 passes through the gap 43 of the second measuring unit 47 to see the second measuring unit 47. The reference plane 42 causes the distance Η1 of the measuring line 41 of the second measuring unit 47 and the reference surface 42 of the second measuring unit 47 to increase, and the characteristic impedance of the second measuring unit 47 becomes large. Referring to FIG. 8, the measuring lines 41, 11 1301043, the reference surface 42 and the gap 43 of the first and second measuring units 46, 47 are arranged in opposite directions, and the gaps 43 of the first and second measuring units 46, 47 are set. On the third conductive layer 513. Referring to FIG. 9, if at least one of the measurement lines β 41 of the first and second measurement units 46, 47 is a line for testing only, the first and second measurement units 46, 47 are used to save area. The gaps 43 of the first and second measuring units 46, 47 are overlapped, and the measuring lines 41 of the first and second measuring units 46, 47 are limited to the two overlapping gaps. 43 in one of the projection areas. &gt; Referring to Fig. 10, the third example is an eight-layer circuit board comprising a conductive layer unit 5, an insulating layer unit 6, and three measuring units 4. The conductive layer unit 5 has an eight-phase stacked conductive layer 51, which is a first conductive layer 511, a second conductive layer 512, a third conductive layer 513, a fourth conductive layer 514, and a fifth in the stacking direction. The conductive layer 515, a sixth conductive layer 516, a seventh conductive layer 517 and an eighth conductive layer 518. The insulating layer unit 6 has seven insulating layers 61 interposed between two adjacent conductive layers 51 of the conductive layer unit 5, respectively.

The three measuring units 4 are a first measuring unit 46, a second measuring unit 47 and a third measuring unit 48, respectively. The measuring line 41 of the first measuring unit 46 is disposed on the second conductive layer 512. The reference surface 42 is disposed on the third conductive layer 513. The gap 43 is disposed on the fourth conductive layer 514. The two measuring points 44, 45 are disposed on the first conductive layer 511. The measuring line 41 of the second measuring unit 47 is disposed on the sixth conductive layer 516. The reference surface 42 is disposed on the fifth conductive layer 515, and the gap 43 is disposed on the fourth conductive layer 514. The two measuring points 44, 45 are disposed on the 12 1301043 layer 518. The measuring line 41 of the third measuring unit 48 is disposed on the seventh conductive layer 517. The reference surface 42 is disposed on the sixth conductive layer, and the gap 43 is disposed on the fifth conductive layer 515. Measurement points 44, 45 are located on the eighth conductive layer 518. The first, second and third measuring units 46, 47, 48 are arranged in a wrong position. And the door 4: the measuring line 41 of the 4th, 2nd measuring unit 46, 47, the sacred surface 42 2 3 are arranged in opposite directions, and the gaps 43 of the first and second measuring..., ο are set in the On the four conductive layers 514. Referring to Figure 11, if the first, once σ-41 to small---------------------------------------------------------------------------------------------------------------------- The second = ί46, 47 can be set at the same-relative position, so that the gap 43 of the early detection 46, 47 overlaps, and the measuring unit 46, the 一#, the second and the second projection area have a built-in line 41 frame. Limited to the two overlapping gaps - see Figures 6, 7, and 11, the first measurement single-shot immunity can be estimated using the embedded microstrip model. When (4) the third conductive layer is interchanged, the first measuring unit layer 512 is estimated by using an offset strip line model, and the characteristic impedance line 41 is heavy through the first and second measuring units 46, 47. ^ The reference surface 42 seen by the second measuring unit 47 and the gap 43 causes the thickness Η of the first dielectric film 49 to increase, and the first measurement is 46. ^The characteristics of the earlier 46 are inductively described in the 'the invention can verify the characteristic impedance of the stacked instrument can judge the '% way board' by using the pre-existing 5 stacking order is 13 j3〇1〇43 no There is a mistake 祆' so there is no difficulty in manual inspection, and the instrument used is an instrument already in the circuit board manufacturer, so there is no additional cost increase 0, but the above # is only the preferred embodiment of the present invention. The scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the present invention in accordance with the present invention: the contents of the invention and the description of the invention are still within the scope of the invention. [Simple diagram of the diagram] #图1疋A cross-sectional view of a six-layer circuit board; (5) (Stereo-knife solution, showing a structure of a six-layer circuit (4) (4) that can be verified by a conventionally verified electrical sequence; Figure 3 is a top view illustrating It is known that the structure of the stacking sequence of the circuit board is used for the "layer" circuit board and the stacking of the front handle case; FIG. 4疋iL body exploded view 'illustrating that the present invention can verify the stacking order of the circuit board The embodiment is a four-layer circuit board. FIG. 5 is a cross-sectional view of a surface microstrip model; FIG. 6 is a cross-sectional view of an embedded microstrip model; and FIG. 7 is a cross-sectional view of an offset strip line model; L8 two-dimensional exploded view 'illustrated that the preferred embodiment is a six-layer circuit L9: - perspective exploded view, illustrating that the preferred embodiment is a six-layer circuit L1: an exploded view ' illustrates the preferred embodiment Yes - eight layers 14 1301043 Figure 11 is an exploded perspective view showing the preferred embodiment of an eight-layer circuit board.

15 1301043 [Explanation of main component symbols] 4......... *Measurement unit 5n... First conductive layer 41 ·...·... i Line 512... ....Second conductive layer 42.······· Reference surface 513 ... ... third conductive layer 43 ... &quot; * gap 514 ... ... fourth conductive layer 44, 45 * • measuring point 515... • ... fifth conductive layer yj 6 ******* * • First measuring unit 516... •... Sixth conductive layer 47.······· Second measuring unit 517... •... Seventh conductive layer 48·....... * Third measuring unit 518 ... • 8th conductive layer 49........ • Dielectric film 6... •...Insulation layer unit 5 *........ • Conductive layer unit 61... • Insulation layer 51 ··... • Conductive layer

16

Claims (1)

1301043 X. Patent application scope: 1 · A circuit board capable of verifying the lamination sequence, comprising: · a conductive layer unit having at least three-phase stacked conductive layers; ', an insulating layer unit having at least two insulating layers, respectively Sandwiched between the two adjacent conductive layers of the conductive layer unit; and the detecting unit 'including a measuring line of equal width, a complete continuous reference surface and a gap> the measuring line, the reference surface and The gap is further divided into: _ is not placed at the same relative position of any three consecutive conductive layers of the conductive layer unit, and the measuring wire frame is limited to a projection area of the gap. 2. According to the scope of the patent application, the calibratable layered Chuanbei sequence of the board of directors and the medium-sized unit also includes a measurement respectively connected to the measuring line and the spring test surface. point. 3. An electrowinning board according to the verifiable lamination sequence of claim 2, wherein the two measuring points are disposed on one of the two outermost conductive crucibles. ^ The electric board of the verifiable lamination sequence according to the scope of the claims of the patent application, wherein the measuring line is a line for transmitting signals. The circuit board of the verifiable stacking sequence described in claim 1 of the patent application is in which the measuring line is a line for testing. The verifiable stacking sequence board according to the scope of the application of the patent application, wherein the shape and relative position of the gap are the same as the measuring line but the width is not less than the width of the measuring line. According to the provable stacking board of the scope of the patent application, wherein the number of conductive layers of the conductive layer unit is greater than four, 17 1301043 includes another measuring unit. 8 · According to the scope of the patent application, the provable stacking board of the fifth paragraph, (5) brother/item, wherein the two measuring units are arranged in a wrong position. , the road 9 _ according to the scope of the patent application 筮 7 ... 士 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可—饭于10· According to the patentable scope item 7, the verifiable laminated white plate, wherein the circuit is arranged in the opposite direction. Lines, reference planes and gaps are in phase 7:: patent scope]. The verifyable stack described in the item is located on the same conductive bank as the gap of the early 兀 ° 一 一 一 , , , , , , , , , , , 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少The units are arranged at the same-relative position such that the two quantities: : 'the gap overlaps' and the measuring line of the two measuring units are limited to... the overlapping gaps - within the projected area. - - According to the circuit of the verifiable stacking sequence described in claim 1, wherein when the number of conductive layers of the conductive layer unit is greater than five, more than 3 at least one I unit, and each is located The inner conductive layer is provided with at least one of the signal line, the reference surface, and the gap. 18