1298404 v 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種晶片壓合結構，特別有關於一種可提高 導電粒子捕捉率的晶片壓合結構。 问 ， 【先前技術】 玻璃覆晶壓合（chip on glass，C0G)是一種積體電路電性 連接的先進技術，具有量輕、型小、成本低、耗電少等優點， 已應用於各種壓合製作上。驅動1C與玻璃基板之電性連^會影 響其品質及可靠度’目前廣泛用來將晶片連接至液晶顯示ϋ 玻璃基板上的材料為異向性導電薄膜（anis〇tr〇picc〇nductive film，ACF) ’是由厚度15-35/zm的絕緣膠及以及直徑約為3一π ”的導電粒子所構成，其中絕緣勝可為熱塑性材料、敎固性材 料或熱塑性及熱固性材料之混合。其中導電粒子可為碳纖維、 金屬或表面塗佈金屬之塑膠球。目前大多採用一種雙層結構的 異向性導電薄膜，其中-層具有導電粒子，另一層薄膜不具有 導電粒子，利用具導電粒子之一層產生電性連接效果。 • — f 1圖顯示習知晶片壓合結構壓合前之示意圖，第2圖顯 不習知々晶片麼合結構中晶片上之金屬凸塊接合面接合面的正視 圖，如第1圖所示，晶片塵合結構包括：晶#1〇1，具有複數個 金屬凸塊103 ;基板105，其上具有複數個接合塾ι〇7，用以與 金屬凸塊1G3相連接，·異向性導電薄膜⑽，具有複數個導電粒 子113,設置於晶片1〇1及複數個接合墊1〇7之間，用以電性連 接金屬凸塊103及接合塾107。當晶片m與基板ι〇5進行壓人 時，異向性導電薄臈109之絕緣膠受金屬凸塊1〇3的賴㈣ 曰曰片103外側抓動’ ‘電粒子113 f隨異向性導電薄膜之 〇632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 5 1298404 絕緣膠之流動而被帶走，且平坦的金屬凸塊1〇3底部不易捉住 導電粒子，因此金屬凸塊103對於導電粒子113的捕捉率相當 低，造成金屬凸塊103與接合墊1〇7捕捉之導電粒子數不足: 而降低元件效能。 【發明内容】 有鑑於此，本發明的目的就在於提升金屬凸塊對導電粒子 的捕捉率。 為達成上述目的，本發明提供一種晶片壓合結構，包括： 一基板，具有複數個接合墊於該基板表面上；一晶片，與該基 板對向設置，具有複數個金屬凸塊，用以與該複數個接合塾接 合，其中該金屬凸塊的接合面接合面具有一凹槽，且該凹槽的 侧壁上具有至少-個缺口；以及一異向性導電薄膜，置於該基 板與該晶片之間，用以電性連接該晶片及該接合墊。 、為達成上述目的，本發明提供一種形成晶片壓合結構的方 法，包括··提供-基板，形成複數個接合墊於該基板表面上，· 於該基板與該複數健合墊之上形成_異向性導電薄膜；提供 日日片，相對設置於該基板，形成複數個金屬凸塊於該晶片上， :以與該複數個接合墊接合，其中該金屬凸塊接合面具有一凹 基板接^ 有广個缺"；以及將該晶片與該 =達上述目的，本發明提供一種電子裝置，係用來與一且 個接合墊之電路板接合，包括··_電子 數 =屬凸塊與該電子元件主體電性連接，該複數個金屬凸塊各 ^凹型接合面，形成該凹型接合面之周圍側壁上至少 一 口。 η 〇632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 6 1298404 【實施方式】 液曰本發明比較例之電子元件晶片M合結構，在此以 曰曰,,„、不态中驅動Ic之晶片壓合結構為例，顯示 晶跡具有複數個金屬一 303為一柱狀物並垂直晶片3〇1表面，其材料可以為一般之導電 材料，較佳為包含金、銅、銘或其合金，金屬凸塊3〇3的接人 =有—、凹槽311，· -基板305，可為例如半導體基板、有機材 料土板、透明基板或玻璃基板，具有複數個接合墊如7，盆中接 合墊為-導電材料，用來與金屬凸塊咖電性連接；一異向性 導電薄膜3G9,具有複數個導電粒子313，形成在基板3()5 合墊307之間，用來黏結基板3〇5與晶片3〇1。 ”接 第4圖顯示第3圖中金屬凸塊接合面正視圖，在晶片上且 有兩組尺寸不同的複數個金屬凸塊，圖式中，較大的金屬凸塊 置於晶片301的上半部，尺寸較小的金屬凸塊置於晶片的下半 部。金屬凸塊可為各種形狀，例如：四方形，五邊形、六邊形， 也可為圓形，為簡化說明，在本實施例中為一正四邊形。當晶 片301與基板305進行壓合製程時，凹槽311可用來捕捉異= 性導電薄膜309中的導電粒子313。異向性導電薄膜3〇9在壓合 製程時，内含絕緣膠的流動方向如第4圖之箭頭所示，壓合時 異向性導電薄膜309之絕緣膠受熱壓頭傳導的熱及晶片3〇1的 擠壓而產生流動，因此而帶走導電粒子313,降低金屬凸塊3〇3 接合面凹槽311對導電粒子的捕捉率，造成接合墊3〇7與金屬 〇632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 7 1298404 凸塊：:的接觸不良，而降低元件效能。 人^: Ϊ ^ 5圖’顯不本發明較佳實施例之晶片壓合結構壓 合刖之不意圖，在此尔丨、,、六η θ — 再& 例，第6㈣… 曰曰顯示器之驅動IC晶片壓合結構為 _不弟5圖金屬凸塊503接合面之正視圖，而第7 圖顯示壓合後的結構。如第R 口而弟7 圖所示，晶片壓合結構，包括： : ϋ :、例如半導體基板、有機材料基板、透明基板或玻 5 土板，基板505表面具有複數個接合墊5〇7，接合墊$叮BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer press-fit structure, and more particularly to a wafer press-fit structure capable of improving the capture rate of conductive particles. Q, [Prior Art] Chip on glass (C0G) is an advanced technology for electrical connection of integrated circuits. It has the advantages of light weight, small size, low cost, low power consumption, etc. Pressing on the production. The electrical connection between the driver 1C and the glass substrate will affect its quality and reliability. The material widely used to connect the wafer to the liquid crystal display ϋ glass substrate is an anisotropic conductive film (anis〇tr〇picc〇nductive film, ACF) 'is composed of an insulating paste having a thickness of 15-35/zm and conductive particles having a diameter of about 3 to π", wherein the insulating material may be a thermoplastic material, a tamping material or a mixture of a thermoplastic and a thermosetting material. The conductive particles may be carbon fiber, metal or metal coated metal balls. At present, most of the two-layered anisotropic conductive film is used, wherein the layer has conductive particles and the other film does not have conductive particles, and the conductive particles are used. One layer produces an electrical connection effect. • — f 1 shows a schematic view of a conventional wafer press-fit structure before press-fitting, and FIG. 2 shows a front view of a joint surface of a metal bump joint on a wafer in a wafer-like structure. As shown in FIG. 1, the wafer dusting structure includes: crystal #1〇1 having a plurality of metal bumps 103; and a substrate 105 having a plurality of bonding electrodes ,7 for supporting gold The bumps 1G3 are connected to each other, and the anisotropic conductive film (10) has a plurality of conductive particles 113 disposed between the wafer 1〇1 and the plurality of bonding pads 1〇7 for electrically connecting the metal bumps 103 and the bonding pads. 107. When the wafer m and the substrate ι 5 are pressed, the insulating paste of the anisotropic conductive thin layer 109 is pressed by the metal bump 1 〇 3 (4) the outer side of the cymbal 103 is gripped ' 'Electroparticle 113 f varies The conductive film is 〇632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 5 1298404 The flow of the insulating glue is taken away, and the flat metal bump 1〇3 bottom is not easy to catch conductive particles, so the metal The capture rate of the bumps 103 for the conductive particles 113 is relatively low, resulting in insufficient number of conductive particles captured by the metal bumps 103 and the bonding pads 1〇7: reducing the device performance. [In view of the above], the object of the present invention is To improve the capture rate of the metal bumps to the conductive particles. To achieve the above object, the present invention provides a wafer press-fit structure comprising: a substrate having a plurality of bond pads on the surface of the substrate; and a wafer disposed opposite the substrate With multiple metal bumps a block for engaging the plurality of joints, wherein the joint surface of the metal bumps has a recess in the mask, and the sidewall has at least one notch on the sidewall; and an anisotropic conductive film is disposed Between the substrate and the wafer, the wafer and the bonding pad are electrically connected. To achieve the above object, the present invention provides a method for forming a wafer pressing structure, comprising: providing a substrate to form a plurality of bonding Padded on the surface of the substrate, forming an _ anisotropic conductive film on the substrate and the plurality of pads; providing a day-to-day film, oppositely disposed on the substrate, forming a plurality of metal bumps on the wafer, The present invention provides an electronic device for use in conjunction with the plurality of bonding pads, wherein the metal bump bonding mask has a concave substrate and a plurality of defects; and the wafer is used for the above purpose. Engaging with a circuit board of a bonding pad, including: ···electronic number=the bump is electrically connected to the electronic component body, and the plurality of metal bumps each of the concave bonding surfaces form a sidewall of the concave bonding surface on At least one. η 〇 632-A5 〇 526 TWf / AU 〇 5 〇 4 〇 26 / Kingandchen 6 1298404 [Embodiment] Liquid raft The electronic component wafer M-combination structure of the comparative example of the present invention is driven here by 曰曰, „, 不For example, the wafer press-bonding structure of Ic shows that the crystal trace has a plurality of metals 303 as a pillar and is perpendicular to the surface of the wafer 〇1, and the material thereof may be a general conductive material, preferably containing gold, copper, or The alloy, the metal bump 3〇3 is connected to the substrate 305, and the substrate 305 can be, for example, a semiconductor substrate, an organic material earth plate, a transparent substrate or a glass substrate, and has a plurality of bonding pads such as 7, The bonding pad in the basin is a conductive material for electrically connecting with the metal bump; an anisotropic conductive film 3G9 having a plurality of conductive particles 313 formed between the substrate 3 () 5 pad 307, Bonding the substrate 3〇5 to the wafer 3〇1.” Figure 4 shows a front view of the metal bump bonding surface in Fig. 3, and there are two sets of metal bumps of different sizes on the wafer, in the figure, Large metal bumps are placed in the upper half of the wafer 301, and smaller metal bumps are placed The lower half portion of the sheet. The metal bumps may have various shapes such as a square, a pentagon, a hexagon, or a circle, and in the present embodiment, a regular quadrilateral for simplicity of explanation. When the wafer 301 is pressed against the substrate 305, the recess 311 can be used to capture the conductive particles 313 in the conductive film 309. When the anisotropic conductive film 3〇9 is pressed, the flow direction of the insulating rubber is as indicated by the arrow in FIG. 4, and the insulating rubber of the anisotropic conductive film 309 is heated by the thermal head during pressing. The wafer 3〇1 is squeezed to generate a flow, thereby carrying away the conductive particles 313, reducing the capture rate of the conductive particles by the metal bump 3〇3 joint surface groove 311, resulting in the bonding pad 3〇7 and the metal 〇632-A5. 〇526TWf/AU〇5〇4〇26/Kingandchen 7 1298404 Bumps:: Poor contact and reduced component performance. Person ^: Ϊ ^ 5 Figure ' does not show the preferred embodiment of the wafer compression structure of the preferred embodiment of the invention, in this case, 丨,, 六 η θ - again & example, the sixth (four) ... 曰曰 display The drive IC wafer press-fit structure is a front view of the joint surface of the metal bump 503, and the seventh figure shows the structure after the press-fit. As shown in the figure R, the wafer pressing structure includes: ϋ : , for example, a semiconductor substrate, an organic material substrate, a transparent substrate or a glass 5 earth plate, and the surface of the substrate 505 has a plurality of bonding pads 5〇7, Mating pad $叮
導“才料’其材質可以為一般之導電材料。較佳可配合實際之 ^程條^而調整使用之材質，以簡化製程。例如在-平面:示 益之製’中，其可以配合製程，而使用例如氧化銦錫薄膜包覆 金屬薄膜在基板505及複數個接合墊5()7上設置一異向性導 電薄膜 509(anisotropic c〇nductive film，ACF)，其厚度一般 約15-35/zm，一晶片50卜置於基板5〇5之上，晶片5〇ι表面 具有複數個金屬凸塊503,其中金屬凸塊5〇3的材料可以為一般 之導電材料，較佳為金、銅、鋁或其合金，用來在壓合製程時 連接基板505與晶片501。於此圖式中，金屬凸塊5〇3為一柱狀 體亚垂直於晶片501表面，然於實際實施上亦可以配合實際設The material of the material can be a general conductive material. It is better to adjust the material used to match the actual process, so as to simplify the process. For example, in the - plane: the system of demonstration, it can be combined with the process. An anisotropic conductive film 509 (ACF) is disposed on the substrate 505 and the plurality of bonding pads 5 (7) using a film of a film such as an indium tin oxide film, and the thickness is generally about 15-35. /zm, a wafer 50 is placed on the substrate 5〇5, and the surface of the wafer 5〇1 has a plurality of metal bumps 503, wherein the material of the metal bumps 5〇3 may be a general conductive material, preferably gold, Copper, aluminum or an alloy thereof for connecting the substrate 505 and the wafer 501 during the pressing process. In the figure, the metal bumps 5〇3 are a columnar body sub-surface perpendicular to the surface of the wafer 501, but in practice Can also be combined with actual settings
計需求，使用例如錐狀等之非柱狀體，因此並不以此圖式為限。 金屬凸塊503的接合面具有一凹槽5Π，用來在壓合製程中捕捉 異向性導電薄膜509中的導電粒子513,捕捉至凹槽511中的導 電粒子513用來電性連接接合墊507與晶片501，其中導電粒子 尺寸一般約2至6// m。 第6圖為第5圖中金屬凸塊503接合面的正視圖，顯示晶 片501上金屬凸塊503接合面之凹槽511。於此圖式中列示之晶 片5 01上具有複數個金屬凸塊5 01，分為大小不同的兩種尺寸， 尺寸較大之金屬凸塊置於晶片5 01的上半部，尺寸較小的金屬 〇632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 8 1298404 =::片=:部’其中金屬凸塊5。3可為各種形狀，例 正四邊形。在开邊形’也可為圓形，在本實施例中為 少且有 V金屬凸塊503接合面凹槽511的側壁上至 :Γ 13’各缺口613尺寸皆大於導電粒子513，且ϊ 5=二1與金屬凸請外側，容許導電二^ 屬凸塊咖接合面凹槽511之形狀，可 弟5圖所不之具有側壁，而内 ： 槽等之設計。㈣曰或疋具有側壁但是内部為不平坦之凹 塊，=尺2:2金屬凸塊其缺口 613朝向小尺寸之金屬凸 也就是將缺σ613==朝向大尺寸之金屬凸塊， 向性導電薄膜509内之絕緣t^5G1進=合製程時異 異向性導電薄膜5〇9絕緣^ 向。進行壓合製程時， 擠壓，而自曰W 頭傳導的熱及晶片3〇1 “圖之=:;==r 動，—^ 動方向，使得里向柯道朝向異向性導電薄膜5〇9的流 塊503接人面導电薄膜5〇9中的導電粒子能進入金屬凸 …U ::Γ槽511中，提升接合時金屬凸塊503接合面 凹V511對導電粒子的捕 曲 的導電率，壓合後之結構如第7圖進所"^金屬凸塊與接合塾間 在;；=如:斷，… 缺口設計成 設計成較側壁内側缺口為大:如、將靠外側之缺口 電粒叫異向性導電薄膜由扇形缺口仙進入金屬凸塊 〇632>A5〇526TWf/AU〇5〇4〇26/Kingandchen 9 1298404 =面：槽m後，但不易由凹請中流出。 =個金屬凸塊具有_個缺口為例，但是，在其他實施例中， 個^以此為限。-個金屬凸塊具有之缺口數目亦可以為例如二 :或：：以上’只要其缺口之大小可以容許導電粒子進入即 ㈣丙曰凸塊接合面之缺口之位置，於本實施例中，較佳為位 膠於壓合時one u朝向異向性導㈣μ含絕緣 川,$之一方向，以方便導電粒子進入凹槽511或凹槽 。於此圖式中’係以兩排大體上平行且具有不同大小之金 2塊為說明。在其他實施例中，亦可以為兩排大體上平行且 二單小之金屬凸塊。在另-實施例中，亦可以為非兩排 =早排或疋三排或是多排之具有相同大小或不同大小之金屬凸 龙。於具有多排之金屬凸塊之情況下，其側壁上之缺口，則以 朝=異向性導電薄膜内含絕緣膠於麼合時之流動方向為佳。位 於曰曰片接合面外側之金屬凸塊之缺口較佳為朝向晶片内側；位 於晶片接合面中央内側之金屬凸塊之缺口較佳為朝向 侧。 本發明之晶0合結構可應用於各種電子裝置，例如電腦 邊幕、平面電視及監控螢幕、行動電話、掌上型遊戲裝置、數 位相機（digital camera，DC).、數位攝錄影機⑷^加vi仏， DV)、數位撥放裝f、個人數位助理（pers〇nai d如如 assistant，PDA)、筆記型電腦（noteb〇〇k)或平板式電腦（加^ 代）’雖'然上述實施例係以液晶顯示器驅動ic之麼合 作說明。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内， 〇632-A5〇526TWi/AU〇5〇4〇26/Kingandchen 10 1298404 當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。For example, a non-columnar body such as a cone is used, and therefore it is not limited to this figure. The bonding mask of the metal bump 503 has a recess 5 捕捉 for capturing the conductive particles 513 in the anisotropic conductive film 509 in the pressing process, and the conductive particles 513 trapped in the recess 511 are used to electrically connect the bonding pad 507. And wafer 501, wherein the conductive particles are generally about 2 to 6 // m in size. Fig. 6 is a front elevational view showing the joint surface of the metal bump 503 in Fig. 5, showing the groove 511 of the joint surface of the metal bump 503 on the wafer 501. The wafer 5 01 listed in the figure has a plurality of metal bumps 511, which are divided into two sizes of different sizes. The larger metal bumps are placed in the upper half of the wafer 501, and the size is smaller. Metal 〇 632-A5 〇 526TWf / AU 〇 5 〇 4 〇 26 / Kingandchen 8 1298404 =:: piece =: part 'where the metal bumps 5. 3 can be various shapes, such as regular quadrilateral. The open-sided shape 'may also be circular, in the embodiment, there are few V-metal bumps 503 joining the surface of the groove 511 to the side wall: Γ 13' each notch 613 is larger in size than the conductive particles 513, and ϊ 5=2 and the metal convex outer side allow the shape of the conductive embossed joint groove 511, but the design of the groove is not included in the figure. (4) 曰 or 凹 凹 疋 疋 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Insulation t^5G1 in the film 509 enters the combined process of the isotropic conductive film 5〇9 insulation. During the pressing process, the heat is transmitted from the head of the W and the wafer 3〇1 “Fig.=:===r, the direction of the movement, so that the inner direction of the Kodo direction is toward the anisotropic conductive film 5 The conductive particles in the conductive film 5〇9 of the flow block 503 of the 〇9 can enter the metal convex...U::Γ 511, and the metal bump 503 is bonded to the surface concave V511 for the deflection of the conductive particles when the bonding is lifted. Conductivity, the structure after pressing is as shown in Figure 7. The metal bumps and the joints are in the middle;; = such as: broken,... The notches are designed to be larger than the inner side of the side walls: The notched electric particles are called anisotropic conductive film from the fan-shaped notch into the metal bump 〇 632> A5 〇 526TWf / AU 〇 5 〇 4 〇 26 / Kingandchen 9 1298404 = face: after the groove m, but not easy to flow out of the recess For example, in the embodiment, the number of the notches may be, for example, two: The size of the notch can allow the conductive particles to enter the position of the gap of the bonding surface of the (c) bump, which is preferred in this embodiment. When the glue is pressed, one u is oriented toward the anisotropic guide (four) μ contains the insulated Sichuan, one direction of the direction, to facilitate the conductive particles to enter the groove 511 or the groove. In this figure, the two rows are substantially parallel and have Two different sizes of gold are illustrated. In other embodiments, two rows of substantially parallel and two small metal bumps may be used. In another embodiment, it may be two rows instead of two rows or early rows or 疋. Three or more rows of metal lobes of the same size or different size. In the case of a plurality of rows of metal bumps, the notch on the side wall is made of an insulating rubber in the anisotropic conductive film. Preferably, the flow direction of the metal bump is preferably toward the inner side of the wafer; the notch of the metal bump located inside the center of the wafer bonding surface is preferably toward the side. The crystal 0 structure can be applied to various electronic devices, such as computer side curtains, flat screen TVs and monitor screens, mobile phones, handheld game devices, digital cameras (DC), digital video cameras (4) ^ plus vi仏, DV), digital display, f, Personal digital assistant (pers〇nai d such as assistant, PDA), notebook computer (noteb〇〇k) or tablet computer (plus generation) 'though' the above embodiment is based on the liquid crystal display driver ic cooperation instructions Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art, without departing from the spirit and scope of the invention, 〇632-A5〇526TWi/AU〇5〇 4〇26/Kingandchen 10 1298404 When a few changes and refinements are made, the scope of protection of the invention is defined by the scope of the appended claims.
o632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 11 1298404 【圖式簡單說明】 第1圖為習知晶片壓合結構壓合前之示意圖； 第2圖為習知晶片壓合結構中金屬凸塊接合面之正視圖； 第3圖為本發明比較例之晶片壓合結構壓合前之示意圖； 第4圖為本發明比較例晶片壓合結構中金屬凸塊接合面之 正視圖； 第5圖為本發明較佳實施例之晶片壓合結構壓合前之示意 圖， 第6圖為本發明較佳實施例之晶片壓合結構中金屬凸塊接 | 合面之正視圖； 第7圖為本發明較佳實施例之晶片壓合結構壓合後之示意 圖， 第8圖為本發明較佳實施例之金屬凸塊接合面之正視圖。 【主要元件符號說明】 晶片〜101 ;金屬凸塊〜103 ;基板〜105 ;接合墊〜107 ;異向性導電 薄膜〜109 ;導電粒子〜113 ;晶片〜301 ;金屬凸塊〜303 ;基板〜305 ;接 合墊〜307 ;異向性導電薄膜〜309 ;凹槽〜311 ;導電粒子〜313 ;晶片〜 > 501 ;金屬凸塊〜503 ;基板〜505 ;接合墊〜507 ;異向性導電薄膜〜509 ; 凹槽〜511 ;導電粒子〜513 ;缺口〜613 ;缺口〜813 ;凹槽〜811。 o632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 12o632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 11 1298404 [Simplified Schematic] Figure 1 is a schematic view of a conventional wafer press-fit structure before pressing; Figure 2 is a conventional wafer press-fit structure. 3 is a front view of a die bonding structure of a comparative example of the present invention; FIG. 4 is a front view of a metal bump bonding face of a wafer bonding structure of a comparative example of the present invention; 5 is a schematic view of a wafer press-fit structure before being pressed in a preferred embodiment of the present invention, and FIG. 6 is a front view of a metal bump joint in a wafer press-fit structure according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 8 is a front view of a metal bump bonding surface according to a preferred embodiment of the present invention. FIG. [Major component symbol description] Wafer ~ 101; Metal bump ~ 103; Substrate ~ 105; Bond pad ~ 107; Anisotropic conductive film ~ 109; Conductive particles ~ 113; Wafer ~ 301; Metal bump ~ 303; Substrate ~ 305; bonding pad ~ 307; anisotropic conductive film ~ 309; groove ~ 311; conductive particles ~ 313; wafer ~ >501; metal bumps ~ 503; substrate ~ 505; bonding pad ~ 507; anisotropic conduction Film ~ 509; groove ~ 511; conductive particles ~ 513; notch ~ 613; notch ~ 813; groove ~ 811. o632-A5〇526TWf/AU〇5〇4〇26/Kingandchen 12