TWI296829B - Method of preventing dishing during chemical mechanical polishing and manufacturing semiconductor device - Google Patents

Method of preventing dishing during chemical mechanical polishing and manufacturing semiconductor device Download PDF

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TWI296829B
TWI296829B TW95101702A TW95101702A TWI296829B TW I296829 B TWI296829 B TW I296829B TW 95101702 A TW95101702 A TW 95101702A TW 95101702 A TW95101702 A TW 95101702A TW I296829 B TWI296829 B TW I296829B
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Taiwan
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gap
protective layer
layer
chemical mechanical
manufacturing
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TW95101702A
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Chinese (zh)
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TW200729314A (en
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Tu Hao Yu
Pai Hsuan Sun
Yu Chia Chen
Te Kan Liao
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Winbond Electronics Corp
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Description

1296829 九、發明說明: 【發明所屬之技術領域】 _ 本發明係有關於一種半導體元件的製造方法,特別有 關於一種預防化學機械研磨凹陷的製造方法。 【先前技術】 隨著半導體製造技術的快速發展,在超大型積體電 路的開發與設計中,為了符合高密度積體電路之設計趨 勢,各式元件之尺寸皆降至次微米以下。在進入線寬小 ® 於0.18微米之世代後,各種製程之條件較以往更為嚴 格,也導致製程之複雜程度亦不斷地提高。 化學機械研磨製程 (Chemical Mechanical Polishing ; CMP )為目前半導體製程中一種典型可以達 到全面性平坦化的方法,化學機械研磨製程通常是利用 在一圓形研磨平台上鋪上一研磨墊,藉晶圓和研磨墊之 間的相對運動來達到化學機械研磨。但由於所使用的研 磨墊具有相當的彈性,在進行化學機械研磨時,晶圓之 • 被研磨層的研磨後平坦性會受到被研磨膜層表面形狀的 影響,此表面產生凹陷形狀,而導致凹陷效應的發生。 隨晶片表面膜層之高低起伏之介電沈積層因沈積 表面不平坦,使得後續沈積膜層之微影、曝光聚焦困難 而影響蝕刻或沈積之品質,因此平坦化於半導體製程中 格外重要。 快閃記憶體(flash memory),其記憶胞的電荷儲存方 式之一是浮動閘(floating gate ),隨著線寬的縮小,以 0492-A40541TWF 5 !296829 更加嚴苛下’利用主動區光罩定義出主動區 a^eT)構的同時’並將胞體陣列區域(celi array 為、孚動區同時定義為浮動閉,淺溝槽隔離結構 丁义称的口丨彳为。但有虺區域 即浮動間過大,在化离心—^紅的見度過大, 閘材料遺失。在予枝械研磨時因為凹陷而造成浮動 據此,本發明之目的在於 凹陷的製程方法,且!^備^、一舌種預防化予枝械研磨 ㈣象而影響後續製程,轉決上述課題。Μ日產生凹 【發明内容】 本發明的一主要目的 陷的製造方法,包括描徂入^r預防化子祛械研磨凹 構、第二淺溝心ί盖】;1 旻數個第-淺溝槽隔離結 汽、盖揭結構間具有第一間隙且兩相鄰之第-:ίί;=?間具有第二間隙,接著全面性形成 圖案化保護層於導電声上,之主動區表面定義- 小於第-間隙_ θ ,、中此圖案化保護層之寬度 R弟一間隙,移除此導電層 二: 面上得到一實質平扫夕笛_、=+隹罘一間隙之主動區表 保護層之移除。、一 —V电層,最後進行此圖案化 本發明的另—φ i θ AA & 凹陷的製造方法,包括一人:弋防化學機械研磨 構、第二淺溝# p 有碰個第-淺溝槽隔離結 ^ 日^離結構及主動區之某庙,立士斤 溝槽隔離結構寬於第_土底其中弟二淺 苒見於弟淺溝槽隔離結構’接著全面性地1296829 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method for preventing a chemical mechanical polishing recess. [Prior Art] With the rapid development of semiconductor manufacturing technology, in the development and design of ultra-large integrated circuits, in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. After entering the line width of the small ® ® 0.18 micron generation, the conditions of various processes are more stringent than before, and the complexity of the process is also constantly increasing. Chemical Mechanical Polishing (CMP) is a typical method for achieving comprehensive planarization in semiconductor manufacturing. The chemical mechanical polishing process usually uses a polishing pad on a circular grinding platform. The relative motion between the polishing pad and the polishing pad is used to achieve chemical mechanical polishing. However, since the polishing pad used has considerable elasticity, the flatness of the polished layer of the wafer during the chemical mechanical polishing is affected by the shape of the surface of the layer to be polished, and the surface has a concave shape, resulting in The occurrence of the depression effect. The dielectric deposition layer with the high and low undulations of the surface layer of the wafer is uneven in the deposition process, which makes the lithography and exposure focusing of the subsequent deposited film layer difficult to affect the quality of etching or deposition, so flattening is particularly important in the semiconductor process. Flash memory, one of the memory storage methods of the memory cell is a floating gate. As the line width is reduced, the 0492-A40541TWF 5 !296829 is more severe. Define the active area a^eT) at the same time 'and the cell array area (celi array, the moving area is also defined as floating closed, shallow groove isolation structure is called the mouth of the mouth. But there are areas That is, the floating space is too large, and the visibility of the centrifugal-^ red is too large, and the brake material is lost. The floating of the brake material is caused by the depression. Therefore, the object of the present invention is the manufacturing method of the depression, and ^^ The prevention of the lingering of the lingering machine affects the subsequent process, and the subsequent problems are reversed. The next day, the concave body is produced. [Inventive content] A main purpose of the present invention is a manufacturing method including tracing prevention. The mechanical grinding concave structure and the second shallow groove heart 盖 cover; 1 旻 a number of first-shallow groove isolation steam, the cover structure has a first gap and the two adjacent ones -: ίί;=? Two gaps, followed by comprehensive formation of a patterned protective layer for conducting Above, the active area surface definition - less than the - gap _ θ, the width of the patterned protective layer R, a gap, remove the conductive layer 2: the surface gets a substantially flat whistle _, = + 隹The removal of the active area surface protection layer of the first gap, the first-V electrical layer, and finally the patterning method of the invention, the manufacturing method of the other φ i θ AA & recess, including one person: 弋 chemical mechanical polishing The second shallow ditch # p has a first-shallow trench isolation knot ^ day ^ away from the structure and the active area of a temple, Lishi Jin trench isolation structure is wider than the first _ soil bottom where the brother two shallow 苒 see the younger brother Trench isolation structure' then comprehensively

0492-A40541TWF 1296829 於第一及第二淺溝槽隔離 此基底進行化學機械研磨 後,對主動區進行回韻刻 隔離結構間形成第一間隙 離結構間形成第二間隙, 將其填充於第一間隙及第 之主動區表面定義一圖案 化保護層之寬度小於第二 坦化,並藉由此圖案化保 間隙的主動區表面上之第 行圖案化保護層之移除。 結構上方沈積一氧化層,再對 製程以移除多餘之氧化層,其 ‘私以於兩相鄰之第一淺溝槽 ,且於兩相鄰之第二淺溝槽^ 形成一第一導電層於基底上並 二間隙中,接著,於第二間隙 化保護層於導電層上,此圖案 f隙,再對第一導電層進行^ 護層以避免平坦後所得之第二 二導電層產生凹陷,最後,進 本發明的又一主要目的為一種半 :包括提供-局部沈積墊氧化層及氮切 底内形成複數個第一淺溝槽隔“構4 ’其中以此淺溝槽定義半導體元件之 離結::著構寬於第一淺溝槽隔 第一及第二淺溝槽隔離;構 ::磨,以移除多餘之氧化層,進行氮化㈣丁 、兩相鄰之第一淺溝槽隔離結構間形成第—= =兩相鄰之第二淺溝槽隔離結構間形' 弟二間隙寬於第一間隙,接著形成 中 主=面’沈積一保護層於 产,2先罩了進行量測第—間隙及第二間隙之i ί第一門寬度與圖案化保護層大小的關聯性’盆 中弟-間隙覓度係大於第一間隙寬度,再以此關連性“0492-A40541TWF 1296829 After the first and second shallow trenches are isolated from the substrate for chemical mechanical polishing, a positive gap is formed between the active regions to form a first gap, and a second gap is formed between the structures to fill the first gap. The gap and the surface of the active region define a patterned protective layer having a width smaller than the second cannization, and thereby removing the first patterned patterned protective layer on the surface of the active region of the gap. An oxide layer is deposited over the structure, and the process is further performed to remove excess oxide layer, which is private to the adjacent first shallow trenches and forms a first conductive layer between the two adjacent second shallow trenches Layered on the substrate and in the two gaps, and then on the second gap of the protective layer on the conductive layer, the pattern f gap, and then the first conductive layer is protected to avoid flattening the resulting second conductive layer Indentation, finally, another main object of the present invention is a half: including providing a localized deposition pad oxide layer and forming a plurality of first shallow trench spacers in the nitrogen-cutting substrate, wherein the semiconductor is defined by the shallow trench The junction of the component: the structure is wider than the first shallow trench isolation first and the second shallow trench isolation; structure: grinding, to remove excess oxide layer, for nitriding (four), two adjacent A shallow trench isolation structure forms a first -= = two adjacent second shallow trench isolation structures. The second gap is wider than the first gap, and then the middle main surface is formed to deposit a protective layer. 2 First cover the measurement of the first gap and the second gap i ί first door width and pattern protection The correlation of the layer size 'the basin - the gap is greater than the width of the first gap, and then the correlation"

0492-A40541TWF 7 1296829 算得一收縮調整值 光罩同相之主動區 層上,以此主動區 圖案化光阻層,以 圖案化保護層,此 再平坦化導電層, 之主動區表面上之 保護層之移除。 【實施方式】 ,依據此收縮調整值製作一與主動區 收縮光罩,其後,形成一光阻於保^ 收縮光罩對該光阻進行曝光顯影得到 其作為罩幕對保護層進行蝕刻以得到 圖案化保護層之寬度小於第二間隙, 並藉由此圖案化保護層避免第二間隙 導電層產生凹陷,最後,進行圖案化 二本發明將藉由以下的較佳具體實施例而作更進一 步地詳細說明,但這些具體實施例僅是作為舉例 而非用以限定本發明之範疇。 請參考第1圖’·其料可㈣半導體積體電路之 Γ10&基底_係包括複數個第―淺溝槽隔離結^ 第、、C籌槽隔離結構120及主動區,其中兩相鄰之 離結構110間具有第一間隙一^ 况溝槽隔離結構120間具有第二間隙:14〇, 遺溝槽隔離結構可A 〃 r 中,第…兽: 4緣材料。在部分實施例 :;他=例中,於第-及第二淺溝槽ί ==二 m藉由對該主動區進行回靖程之二 此第-導第層15Q於基底100上, 體材料。 括早日日矽、夕晶矽、或磊晶矽等半導 接者,於第二間隙140之主動區160表面180,定0492-A40541TWF 7 1296829 Calculate a contraction adjustment value mask on the active layer of the same phase, and pattern the photoresist layer with the active region to pattern the protective layer, and then planarize the conductive layer, the protective layer on the active region surface Removed. [Embodiment], a shrink mask is formed according to the shrinkage adjustment value, and then a photoresist is formed on the shrink mask to expose the photoresist to obtain a mask to etch the protective layer to obtain a protective layer. The width of the patterned protective layer is smaller than the second gap, and the second gap conductive layer is prevented from being recessed by patterning the protective layer. Finally, the patterning is performed. The present invention will be further advanced by the following preferred embodiments. The detailed description is to be considered as illustrative and not restrictive. Please refer to FIG. 1 ' 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 There is a first gap between the structures 110. The trench isolation structure 120 has a second gap: 14 〇, the trench isolation structure can be A 〃 r, the first... beast: 4 edge material. In some embodiments:; in his case, in the first and second shallow trenches ί == two m by the active region of the second phase of the first layer 15Q on the substrate 100, the bulk material . A semi-conductor such as an early day, an eclipse, or an epitaxy, is disposed on the surface 180 of the active region 160 of the second gap 140.

0492-A40541TWF 12968290492-A40541TWF 1296829

義一圖案化保護層1Q 190之宫庚W1 於導電層150上,圖案化保護層 化保轉tcT 第二間隙之寬度W2。其中定義圖案 先^ 之貫施例係如下所述,請參考第1圖,首 由護層170於第一導電層150上,例如藉 形成,其中此保護層之沈積厚度約為 上。、 弟導電層相對保護層的選擇性高於100以 上,i接著’請參考第2及3圖,先形成光阻於保護層170 得到3以動區收縮光罩2 〇對該光阻進行曝光顯影 圖案化光阻層2〇〇 ;以此圖案化 幕,對保護層Π。進行_以得到一圖案化保 15〇ϋ考第丄圖’在定義圖案化保護層19G於導電層 人旦ζΐ / ’ 別以主動區光罩1G為基準,且配 。里測弟一間隙之寬度W3及第二間隙之寬度W4,以 立間隙寬度與圖案化保護層19G大小 二間隙寬度W4係大於第一間隙官斧…㈠生其中弟 管-收維、弟㈣見度W3’以此關連性估 且依據此收縮調整值製作—與主動區 先罩10同相之主動區收縮光罩2〇 ’以 200為罩幕,對保護声 α茶化尤阻層 護層刻以得到一圖案化保 一般而言,如第2圖所示,就圖案化保護層190盥 主動區160間之侧壁220的距離範圍約為〇3_〜^、 Γ而/ΐ化▲保護層190寬度W1至少大於〇.5㈣,此 外,弟二間隙140之寬度W2至少大於〗1//m。 本發明所使用之主動區收縮光罩2〇係與主動區光The first protective patterned layer 1Q 190 of the palace Geng W1 is on the conductive layer 150, and the patterned protective layer ensures the width W2 of the second gap of the tcT. The definition of the pattern is as follows. Referring to FIG. 1, the first layer 170 is formed on the first conductive layer 150, for example, wherein the protective layer is deposited to a thickness of about 10,000 Å. The selectivity of the conductive layer relative to the protective layer is higher than 100, i then 'Please refer to Figures 2 and 3, first form a photoresist in the protective layer 170 to obtain 3 to the movable region shrink mask 2 曝光 expose the photoresist The patterned photoresist layer 2 is developed; the screen is patterned to lick the protective layer. Performing _ to obtain a patterning 〇ϋ 丄 丄 ’ 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Measure the width W3 of the gap and the width W4 of the second gap, and the gap width and the patterned protective layer 19G size and the gap width W4 are larger than the first gap official axe... (1) The younger brother--------------------- Visibility W3' is estimated based on this correlation and is based on the shrinkage adjustment value. The active area shrink mask 2〇' in the same phase as the active area first cover 10 is covered by 200, and the protective sound α-tea is especially resistant. In general, as shown in FIG. 2, the distance between the sidewalls 220 of the patterned protective layer 190 and the active region 160 is about _3_~^, Γ和/ΐ化▲ The width W1 of the layer 190 is at least greater than 〇.5 (four), and further, the width W2 of the gap 140 is at least greater than =1/m. Active region shrink mask 2 and active area light used in the present invention

0492-A40541TWF 9 1296829 ^為同相’其較原主動區光罩為每邊縮小Q加〜^ 移除’進行第一導電層150之部分移除, 間以ΓΓ:學機械研磨法或赚,以在第二 二導電層21〇 ί上60表面⑽上得到-實質平坦之第 來避φ Φ # 、σ之,亦可藉由此圖案化保護層190 】^ ί16!表面18〇上之第二導電層2Κ)產生凹 19〇。、"以乾式或濕式蝕刻法等移除圖案化保護層 造方:參包考括第提提供—種半導體 溝底細,於基底3〇0内形成複數個第一淺 第二咖 久#钆疋義+ V體元件之主動區範 今 離結構320寬於第一淺溝 弟一'成溝槽隔 t 乳化矽層530於部分氮化矽層520、第一及^ 淺溝槽隔離結構310、320上方。 弟及弟二 明參考第6圖,接著對基底300進行化學樯矜讲府 ==,530,再進行氮化 ::隙:兩二鄰第之第 ,▲ r罘一間隙340寬於箆一 ρη姐、”n 35〇^μ±μ^^33〇π 隙330及第二間隙34”,且於第二間隙3真 ί:區:ί—保護層於導電層350上,接下來,提供-動-先罩,亚進行量測第一間隙及第二間隙之寬度,0492-A40541TWF 9 1296829 ^ is in phase 'its smaller than the original active area mask for each side to reduce Q plus ~ ^ remove 'to remove part of the first conductive layer 150, between the two: learn mechanical grinding or earn, to On the surface (10) of the second and second conductive layers 21, the surface of the surface is substantially flattened to avoid φ Φ # and σ, and the protective layer 190 can be patterned thereby to form a second surface 18 The conductive layer 2) produces a recess 19〇. , " remove the patterned protective layer by dry or wet etching, etc.: the package includes the first to provide a semiconductor groove bottom, forming a plurality of first shallow second coffee in the substrate 3〇0# The active area of the 钆疋义+ V body element is wider than the structure of the first shallow groove 一 ' 成 沟槽 沟槽 emulsified 矽 layer 530 in part of the tantalum nitride layer 520, the first and ^ shallow trench isolation structure Above 310, 320. The younger brother and the younger brother refer to Figure 6, and then carry out the chemical test on the substrate 300 ==, 530, and then nitriding:: Gap: two or two adjacent, ▲ r罘 a gap 340 is wider than the first one Ρη sister, "n 35〇^μ±μ^^33〇π gap 330 and the second gap 34", and in the second gap 3 true: region: ί - protective layer on the conductive layer 350, then, provide - a moving-first cover, sub-measures the width of the first gap and the second gap,

0492-A40541TWF 10 1296829 以建立間隙寬度與圖案化保護層大小的關聯性,直> 二間隙寬度係大於第-間隙寬度,再以此關連性估= 一收縮調整值,依據此收縮調整值製作—盥主了于 同相之主動區收縮光罩,其後,形成—光阻於保罩 區=光罩對該光阻進行曝光顯影得“案化 ^以"作為罩幕對保護層進行蝕刻以得到間宏' J護層·’此圖案化保護層之寬度小於第j;案 ,坦化導電層350,並藉由此圖案化保護層細避步I 一間隙之主動區表面上之導電層產生凹。往& ^ =在如快閃記憶體元件之製作,其中此平坦‘導7 最後,進行圖案化保護層之移除二 :隹然本發明已以較佳實施例揭露如 以限定本發明,因此本發 ς〜、亚非用 專利範圍所衫者為準 保心圍當視後附之申請 【圖式簡單說明】 第1圖為繪示依據本發明一每 於具有間隙的淺溝槽隔離結構上方導電層 第2圖為繪示依據本二二 保護,於導電層上方之示意圖月之貝施例之疋義圖案化 導電層以得到實質平坦之‘ Λ, — λ域之平坦化第-第4圖為繪示依據:=電1之示意圖。 收縮光罩之示意圖。么月之一貫施例之形成主動區 第5圖為本發明之— 第6圖為本發明之造方法示意圖。 肢凡件製造方法示意圖。0492-A40541TWF 10 1296829 to establish the correlation between the gap width and the size of the patterned protective layer, straight> the width of the gap is greater than the width of the first gap, and then the correlation value = a contraction adjustment value, based on the shrinkage adjustment value盥 盥 盥 盥 同 同 同 收缩 收缩 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The width of the patterned protective layer is smaller than that of the first layer, and the conductive layer 350 is formed, and the protective layer is patterned to avoid the conductive layer on the surface of the active region. Producing a concave. To & ^ = in the fabrication of a flash memory component, where this flat 'guide 7 finally, the removal of the patterned protective layer is performed. 2: The present invention has been disclosed by the preferred embodiment as defined According to the present invention, the application of the present invention is based on the application of the patent scope of the present invention. [Appropriate Description of the Drawings] FIG. 1 is a diagram showing the shallowness of the gap according to the present invention. The conductive layer above the trench isolation structure is shown in Figure 2. According to the second protection, the schematic layer of the conductive layer on the top of the conductive layer is patterned to obtain a substantially flat 'Λ, — the flattening of the λ domain - the fourth figure is based on: = electricity 1 is a schematic diagram of a shrink mask. The formation of the active area of the month is the fifth embodiment of the present invention - Fig. 6 is a schematic view of the manufacturing method of the present invention.

0492-A40541TWF 1296829 第7圖為本發明之一半導體元件製造方法示意圖。 【主要元件符號說明】 10〜主動區光罩;20〜主動區收縮光罩;100, 300〜基底; 110,310〜第一淺溝槽隔離結構;120,320〜第二淺溝槽隔 離結構;130,330〜第一間隙;140,340〜第二間隙;150〜 第一導電層;160〜主動區;170〜保護層;180〜表面;190, 360〜圖案化保護層;200〜圖案化光阻層;210〜第二導電層; 220〜側壁;350〜導電層;510〜墊氧化層;520〜氮化矽層; 530〜氧化石夕層。 0492-A40541TWF 120492-A40541TWF 1296829 Fig. 7 is a schematic view showing a method of manufacturing a semiconductor device of the present invention. [Main component symbol description] 10~ active area mask; 20~ active area shrink mask; 100, 300~ substrate; 110, 310~ first shallow trench isolation structure; 120, 320~ second shallow trench isolation structure ; 130, 330~ first gap; 140, 340~ second gap; 150~ first conductive layer; 160~ active area; 170~ protective layer; 180~ surface; 190, 360~ patterned protective layer; Photoresist layer; 210~ second conductive layer; 220~ sidewall; 350~ conductive layer; 510~ pad oxide layer; 520~ tantalum nitride layer; 530~ oxidized stone layer. 0492-A40541TWF 12

Claims (1)

1296829 十、申請專利範圍: 丨·—種預防化學機械研磨凹陷(Dishi )的製造方 冼,包括: -、& 一基底,包括複數個第一淺溝槽隔離結構及第 巧離結構,兩相鄰之該第—淺溝槽隔離結構間 2 »弟一間隙且兩相鄰之該第二淺溝槽隔離結構間具 有一弟二間隙; 全面,形成一第一導電層於該基底上; 雷展表面’定義—圖案化保護層於該導 曰,該圖案化保護層之寬度小於該第二間隙; 質平導電層’以在該第二間隙之表面上得到-實 貝千坦之第二導電層;及 移除該圖案化保護層。 凹陷二ttt利1圍第1項所述之預防化學機械研磨 I曰的衣造方法,並中轉證一 P目 /、甲忑弟—間隙之表面為一主動區。 凹陷3的專:1!圍項所述之預防化學機械㈣ 導電層二ί係:定義該圖案化保護層於該第- 沈積一保護層於該第一導電層上; 形成一光阻於該保護層上· 得到層為罩幕’對該保護層㈣ 4·如申請專㈣_ 3韻述之髓化學機械研磨 0492-A40541TWF 13 1296829 凹陷的製造方法,其更包括: 提供一主動區光罩; 里測該弟一間隙及該第二命 與該圖案化保護層大:聯見:中:㈡隙 覓度係大於該第一間隙寬度;,、中遠弟二間隙 以該關連性估算一收縮調整值· 動區縮:整值製作-與該主動區光罩同相之主 凹陷的製造方法述之預防化學機械研磨 侧壁的距離範圍约為‘二5 層與第二間隙間之 7·如申印專利範圍第1 ^ ^ ^ ® lilm ill4^ M ^ ^ 縮光罩係較原主動區光罩每邊 9·如申請專利範 > 凹陷的製造方法靜^^防化學機械研磨 曼層之沈積厚度約為數百埃。 0492-A40541TWF 14 1296829 10.如申請專利範圍第1項所述之預防化學機械研磨 凹陷的製造方法,其中該導電層係包括單晶矽、多晶矽、 或蠢晶梦。 • 11.如申請專利範圍第1項所述之預防化學機械研磨 . 凹陷的製造方法,其中該保護層係包括氮化矽。 12.如申請專利範圍第1項所述之預防化學機械研磨 凹陷的製造方法,其中該淺溝槽隔離結構係包括氧化矽 等絕緣材料。 W 13.如申請專利範圍第1項所述之預防化學機械研磨 凹陷的製造方法,其中該移除該圖案化保護層步驟係包 括乾式或濕式蝕刻法。 14.一種預防化學機械研磨凹陷的製造方法,包括: 提供一基底,包括複數個第一淺溝槽隔離結構及第 二淺溝槽隔離結構,該第二淺溝槽隔離結構寬於該第一 淺溝槽隔離結構; 全面性形成一氧化層於該第一及第二淺溝槽隔離結 鲁構上方; 對該基底進行一化學機械研磨製程以移除多餘之該 .氧化層; 對該基底進行回蝕刻製程以於兩相鄰之該第一淺溝 槽隔離結構間形成一第一間隙,且於兩相鄰之該第二淺 溝槽隔離結構間形成一第二間隙; 形成一第一導電層於該基底上並填充於該第一間隙 及該第二間隙中; 於該第二間隙之表面,定義一圖案化保護層於該導 0492-A40541TWF 15 1296829 電層ΐ坦=;=:之寬心、於該第二間隙; 平坦後所得之該第二二;的該圖案化保護層避免 陷;及 間隙的表面上之第二導電層產生凹 矛夕除邊圖案化保護層。 !5·如申請專利範圍第ι4 磨凹陷的製造方法,其中該第二間^之表面學 磨凹陷的製造預防化學機械研 電層上之步驟係包括Γ中抓成料大小之保護層於導 沈積一保護層於該第一導電層上; 形成一光阻於該保護層上;θ 以一主動區收縮光罩對該光阻曝顯 圖案化光阻層;及 ㊉仃曝尤頰衫侍到一 以該圖案化光阻層為罩幕,對該保護層 仔到一圖案化保護層。 丁蝕刻以 I7·如申請專利範圍第16項所述之預防化學 磨凹陷㈣造方法,其更包括·· 械研 提供一主動區光罩; ^該第—間隙及該第二間隙之寬度,以建立間隙 是又〃、k圖案化保護層大小的關聯性, 寬度係大於該第一間隙寬度; ^弟一間隙 以該關連性估算一收縮調整值; 依據該收縮調整值製作一與該主動區光罩主 動區收縮光罩;及 J祁之主 以該圖案化光阻層為罩幕,對該保護層進行蝕刻以 0492-A40541TWF 16 1296829 得到一圖案化保護層。 磨二二、ί古專Γ範圍第17項所述之預防化學機械研 其中該主動區光罩可為該第二間隙 間的主動區之光罩。 1糸 19. 如申請專利範圍第14項所述之預防化學機 ::的製造方法’其中該圖案化保護層與該間:: 壁間的距離範圍約為〇.3#m〜5/zm。 側 20. 如申睛專利範圍第14項所述之 I:的製造方法,其中該圖案化保護層寬度至it 21·如申請專利範圍第14項所述之預防化學機 磨凹陷的製造方法,其中該第二間隙之寬度至少大成械= // m。 、上·! .如申明專利範圍第〗7項所述之預防化學機械 磨=陷的製造方法’其中該與主動區光罩同相之主動區 收縮光罩係較原主動以罩每邊縮小G.3A m〜5/zm。 23.如申請專利範圍第14項所述之預防化學機械研 的製造方法’其中該保護層之沈積厚度約為數百 =·如申請專利範圍第14項所述之預防化學機械研 f凹H製造方法,其中該導電層係包括單晶梦、多晶 發、或遙晶碎。 25.如申請專利範圍第14項所述之預防化學機械研 0492-A40541TWF 17 1296829 磨凹陷的棄j 士 衣k方法,其尹該保護層係包括氮化矽。 磨凹方專f範圍第14項所述之預防化學機械研 材料。化方法,其中該淺溝槽係包括氧化矽等絕緣 磨凹專,f第17項所述之預防化學機械研 包括乾式或=刻ί”移除咖 刻製程』Γ 其中該淺溝槽離結構係由微影及: 29·如申請專利範圍第μ 磨凹陷的製造方法,其中該氧化:::預=學機械研 氣相沈積製程形成。 9係由尚岔度電漿化學1296829 X. Patent application scope: 制造·—The manufacturing method for preventing chemical mechanical grinding recesses (Dishi), including: -, & a substrate, including a plurality of first shallow trench isolation structures and a detached structure, two Adjacent to the first shallow trench isolation structure 2 » brother a gap and two adjacent shallow trench isolation structures have a second gap; comprehensively, forming a first conductive layer on the substrate; The surface of the lightning spread is defined as: a patterned protective layer on the guide, the width of the patterned protective layer is smaller than the second gap; and the flat conductive layer is obtained on the surface of the second gap - the first a second conductive layer; and removing the patterned protective layer. The second method of preventing chemical mechanical grinding according to the first item of the ttt 2, the first method of the manufacturing method, and the transfer certificate, the surface of the gap, and the surface of the gap is an active area. The prevention of chemistry 3 (4) The conductive layer is defined by: the patterned protective layer on the first deposition a protective layer on the first conductive layer; forming a photoresist On the protective layer, the layer is obtained as a mask. The protective layer (4) is as follows: (4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Measure the gap between the brother and the second life and the patterned protective layer: see: middle: (2) the gap is greater than the width of the first gap; and the gap between the two is determined by the correlation. Value · Dynamic zone shrinkage: Whole value production - The manufacturing method of the main recess in phase with the active area mask is described as the distance between the prevention of chemical mechanical polishing sidewalls is about 'two 5 layers and the second gap. Printing patent range 1 ^ ^ ^ ® lilm ill4^ M ^ ^ Shrinking hood is more than the original active area reticle 9 · as in the patent application > The manufacturing method of the depression static ^ ^ chemical mechanical grinding of the German layer deposition The thickness is about several hundred angstroms. The method of manufacturing a chemical mechanical polishing recess according to claim 1, wherein the conductive layer comprises a single crystal germanium, a polycrystalline germanium, or a silly crystal. 11. The method of preventing chemical mechanical polishing as described in claim 1, wherein the protective layer comprises tantalum nitride. 12. The method of manufacturing a chemical mechanical polishing recess according to claim 1, wherein the shallow trench isolation structure comprises an insulating material such as ruthenium oxide. The method of manufacturing a chemical mechanical polishing recess according to claim 1, wherein the step of removing the patterned protective layer comprises a dry or wet etching. 14. A method of fabricating a chemical mechanical polishing recess, comprising: providing a substrate comprising a plurality of first shallow trench isolation structures and a second shallow trench isolation structure, the second shallow trench isolation structure being wider than the first a shallow trench isolation structure; forming an oxide layer over the first and second shallow trench isolation structures; performing a chemical mechanical polishing process on the substrate to remove the excess oxide layer; An etchback process is performed to form a first gap between the two adjacent shallow trench isolation structures, and a second gap is formed between the two adjacent shallow trench isolation structures; Conductive layer on the substrate and filling in the first gap and the second gap; on the surface of the second gap, defining a patterned protective layer on the conductive layer 0942-A40541TWF 15 1296829 electrical layer ; = ===: a wide center of the second gap; the patterned second protective layer obtained after flattening avoids sinking; and the second conductive layer on the surface of the gap creates a recessed patterned protective layer. 5) The manufacturing method of the iv4 grinding recess of the patent application scope, wherein the step of manufacturing the second chemical surface of the second surface is to prevent the chemical mechanical layer from being formed by the protective layer of the size of the smashing material. Depositing a protective layer on the first conductive layer; forming a photoresist on the protective layer; θ exposing the patterned photoresist layer to the photoresist by an active region shrink mask; and a ten-inch exposure cheek shirt To the mask with a patterned photoresist layer, the protective layer is patterned to a protective layer. The method for preventing chemical cracking (four) according to claim 16 of the patent application scope, which further comprises: providing an active area mask; ^ the first gap and the width of the second gap, To establish the gap is the correlation of the size of the protective layer of the 〃, k, and the width is greater than the width of the first gap; ^ a gap is used to estimate a shrinkage adjustment value according to the correlation; and the initiative is made according to the shrinkage adjustment value The reticle active area shrinks the reticle; and the master of the enamel uses the patterned photoresist layer as a mask, and the protective layer is etched to obtain a patterned protective layer at 0492-A40541TWF 16 1296829. The chemistry of the active zone described in item 17 of the diagnosing range can be the reticle of the active zone between the second gaps. 1糸19. The method of manufacturing a prophylactic chemical machine as described in claim 14 wherein the distance between the patterned protective layer and the wall: is about 3.3#m~5/zm . The method of manufacturing the I: according to claim 14, wherein the patterned protective layer has a width to the manufacturing method of preventing chemical grind pits as described in claim 14 of the patent application scope, Wherein the width of the second gap is at least as large as /= m. ,on·! For example, the method for manufacturing a chemical mechanical grinding method according to the seventh paragraph of the patent scope is as follows: wherein the active area shrinking reticle in phase with the active area mask is smaller than the original active cover by the cover G. 3A m~ 5/zm. 23. The method of manufacturing a prophylactic chemical mechanical method as described in claim 14, wherein the protective layer has a deposition thickness of about several hundred = a prophylactic chemical mechanical research described in claim 14 A manufacturing method, wherein the conductive layer comprises a single crystal dream, a polycrystalline hair, or a crystallite. 25. The method of preventing chemical mechanical research 0492-A40541TWF 17 1296829 according to claim 14 of the patent application, wherein the protective layer comprises tantalum nitride. The preventive chemical mechanical research materials mentioned in Item 14 of the F. The method, wherein the shallow trench system comprises an insulating etched surface such as yttrium oxide, and the preventive chemical mechanical research described in item 17 includes a dry or etched process, wherein the shallow trench is separated from the structure By lithography and: 29· The manufacturing method of the patented range μ μ sag, wherein the oxidation:::Pre-study mechanical vapor deposition process is formed. 0492-A40541TWF 180492-A40541TWF 18
TW95101702A 2006-01-17 2006-01-17 Method of preventing dishing during chemical mechanical polishing and manufacturing semiconductor device TWI296829B (en)

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