TWI293200B - Method of forming flash cell array having reduced word line pitch - Google Patents

Description

1293200 18424twf.d〇c/y IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a flash memory device and a method of fabricating the same. [Prior Art] # NAND (reverse) type · R〇M (paper erasable programmable memory) or (4) memory has been developed for portable music players, mobile phones, digital cameras Solid state mass storage applications, etc., and have been considered as replacements for hard disk drives (HDDs). Therefore, it is desirable for these devices to have greater capacity, lower cost, and reduced cell size for miniaturization and increased processing speed.

The NAND device structure is typically designed such that: (1) each memory cell utilizes a transistor having a floating gate and a control gate; and (2) a memory cell array disposed on a substrate and corresponding A single-contact is provided between the bit lines. Therefore, as compared with the conventional EEpR 〇 M, although the cell spacing is usually limited by the selected photolithography process, the area occupied by the memory cell is reduced, and the accumulation density can be increased. U.S. Patent No. 5,050,125, the entire disclosure of which is incorporated herein by reference in its entirety the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all The cell size or area is defined by the width of the floating interpole and the adjacent insulating region (X direction in Figure 4) and the width of the control gate of the phase and the adjacent insulating region (Y direction). , that is, by the floating gate and the control pole 1293200 18424twf.doc / y; ΐ overlap area? Defined. '125 patent per unit cell below the unit cell size, where "f" is the most optical imaging ', the minimum feature size obtained by the technology used in the manufacturing process of the '125 patent, or the wire rabbit. The minimum feature size is currently known to be about 9 〇 nm. Conclusion false =, the minimum width of the gate (four) is Approximately 1F, and adjacent in the floating-pole array: the minimum width of the most spaced is also (four) 'simultaneous control' = two and the minimum spacing between adjacent control gates is eight-year-old. The x direction occupies at least a minimum of 2F and at least a minimum of 2F to 2.5F in the direction.

U.S. Patent No. 6,58,12, to Hasssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss Accelerating Flash Memory Therefore, it is desirable to use an easily accumulable process to increase the density of the array. BRIEF SUMMARY OF THE INVENTION A method of forming a NAND flash memory device includes: forming a gate polycrystalline 7 layer on a substrate; and forming a gate layer on the control gate polysilicon layer The mask layer includes a mask pattern defining two or more spaced word lines of the flash memory device, the word lines being spaced apart from each other by a distance less than a minimum feature size, the minimum feature size being at least 2 - part of the mask layer pattern - selected by the photolithography process - and controlling the gate polysilicon layer by mask layer etching. The above and other objects, features and advantages of the present invention are set forth in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 〜 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Lang, figure = circuit diagram of the - part of the flash memory array. For example, the row and column solutions == the various components of the circuit and other control circuits are not displayed, and the display becomes blurred. However, the technical personnel of these components are well known. , meaning, body _ New Wei _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Parallel words = 2, 0, WU, ..., WLn are formed on the substrate, and the flash memory cell formed at the mother-cell position is formed as a gate. The transistors SLG, SL1, etc. and gslq, gsu, etc. are selected at the respective ends of the bit line BL. - Divide an exemplary memory array into a number of memory "tiles". A block has a number of "pages". The page has a lot of memory "crystal two." For example, a 1 Gb memory has a Cong block and a zone with 64 pages. Each page has 2K bytes (ie 16 kbits). — The sub-line contains a page. A cell string or two cell strings are provided per block in the bit (10) direction. A cell string has 16 bits, U bit 1293200 18424twf.doc/y Ϊ(4)?;. For example, in the case of the _ in the case of the New Zealand cell, the 'storage-bits' or two bits are stored. In this example, the conditions for private, erase, and read operations are as follows: Erase _ Stylized Read ον

Selected WL Unselected WL 0 V 20 V&lt; 0V 4.5 V

Stylized 1) Floating body [bulk] 20 V VCC ον Ν/Α Ν/Α In this stylization/erasing method, Fowler-Nordheim (FN) is tunneled for NMOS NAND flash memory cells. Stylized and erased. During the stylization, a higher positive voltage is applied to the word line of the selected unit cell. A medium voltage is applied to the unselected word lines to turn on these cells. Apply a ground voltage or 0 V to the bit line to write the data "〇", and apply VCC to write the data "Γ. Transfer 0V to the channel of the selected cell, perform FN pass to inject electrons from the channel Floating gate. When the data is “Γ, the word line voltage couples the channel and there is a negligible FN tunneling current, so the unit cell is not programmed. For erasing, the P-well of the unit cell is biased at a high voltage and all of the word lines in a 1293200 18424 twf.doc/y block are grounded. Electrons tunnel from the floating gate FN to the p-type well substrate. Figure 2 depicts a side cross-sectional view of a cell string. The cell string includes select transistors 20a, 20b, wherein a plurality of NM 〇s floating gate flash cell transistors 18 are formed between the select transistors 2A, 2B. Although the selected transistors 20a, 20b are shown as double-gate transistors, the load can be as shown in Figure 1 = using a single-gate transistor. In the embodiment, the substrate 10 comprises a p-type yttrium substrate, and the doped yttrium substrate is formed in a three (Wdl) region 12 in the cell array region. The three wells include a well surrounding a p-type well: an n-type well. For example, the 'alternative embodiment' can be used in a silky and alternate configuration. This article has been described in connection with the NMQS flash memory cell, but the cell can also include a PMOS cell formed on a P-type substrate. The gate dielectric layer 16 is thermally grown on the substrate 1() and is between about 70 and about 〇A. Source _ Ϊ = + implant region 14, formed between unit cells 18 and formed between unit cell 18 and selective transistor application, N+ implant region 14 comprising a concentration of about ω atoms /cm3 arsenic or phosphorus dopant. Each of the unit cells 18 includes a gate dielectric, 22, preferably comprising - a polycrystalline material having a thickness of about 3 (ΚΜ_Γ =, and more preferably about Α The gate 22 includes a tantalum oxide layer 24 to form 110 to 140 Å (10) ^ mesh, for example, formed to a thickness of about (10), or has an effective oxidation between about 110 and gangue 1293200 18424 twf. doc / y thickness An ONO (oxide/nitride/oxide) layer. The ruthenium layer can be deposited using an lpcvD (low pressure chemical vapor deposition) process having a top oxide layer deposited from a Sil^CLVO2 gas of about 20 Å thick. A bottom oxide layer having a thickness of about 40 A is deposited from the SiHeh/O2 gas, and has a SiN layer deposited from a Sil^CIVN2 gas to a thickness of about 80 A. The control gate 26 is formed from a word line common to a plurality of parallel unit strings. The control gate 26 is formed on the dielectric layer 24, and preferably comprises a polycrystalline layer 28 having a thickness between about 700 and 1000 A. The lithiation layer 28 preferably comprises a tungsten (W) A layer of germanium, optionally formed on the control gate/word line 26. Flattening the insulating layer 32 On the cell string, it may comprise one or more individual dielectric layers. The connection hole is formed through the dielectric layer 32 and filled with the polysilicon plug 3〇 to select the transistor 2 The conductive bit line 36, for example comprising tungsten, is formed over the second insulating layer 34 and coupled to the polysilicon plug 30 via a conductive via 38. It will be apparent to those skilled in the art that when controlling Gate 26 and germanide layer 28 (when present) form a word line across several cell events as shown in @i, floating gate 22 and dielectric layer of each cell by - The insulating layer surrounds the insulating layer to separate the unit cells in the individual cell strings; this separates and separates from the unit cells of adjacent cell strings. As shown in Figure 2, each transistor cell 18 has a channel length f, which is defined by the minimum size that can be imaged by the photolithography process used to form the pattern of the syllabic body array. Each-selective transistor 2〇a has a length of 1293200 18424twf.doc/y degrees 2F with the survey vehicle. (to avoid breakdown problems, minimize source-to-drain leakage current, etc.), and with their respective interposers 30 Separation distance; p. Each plug has a pitch of 2F. It is important that 'every-floating gate cell 18 is spaced from adjacent floating gate cell 18--the distance "x" is less than F, and phase The adjacent selection transistor 20 (for the terminal cell 18) is spaced apart by this distance. The total cell string length is equal to, 8F + mF + (m + l) X, and the towel "m" is the unit cell_medium cell The total number is usually 16, 32 or 64. In one embodiment, χ is equal to 〇〇3μπ1 and F is equal to 〇·〇9 μιη and there are 16 unit cells, so the total unit string length is only 24F+ (17/3) ) F^7F. As in the prior art, if χ is equal to F, then the total a cell string length will be 41F. In addition, assuming that χ is equal to i/sf, the unit cell size is approximately (F + X) 2F (or approximately (2.66 F2)) instead of 4-5F2. 3A to 3F describe an exemplary method of forming the closely spaced word lines of Fig. 2. 3A to 3F illustrate a process step for creating a front-end-of-lme ' FEOL process for a memory structure. The process steps for forming the interconnect circuitry required to address the individual memory cells are not discussed herein, i.e., forming the back segments such as contact windows, vias, metal lines, and corresponding insulating layers (back&gt;end_of-line, BE0L) Process. Referring to Figure 3A, a stack of materials for forming individual memory cell transistors is first formed on gate dielectric layer 16. Specifically, a floating, very polycrystalline layer m is deposited to a thickness of between about 30 Å and 1000 Å. Next, a tantalum dielectric layer 124 is formed over the polysilicon layer 122. Next, the controlled, interpolar polycrystalline layer 126 is deposited to a thickness between about 7 GG and 10 () () Α. Finally, "or a tungsten-lithium layer 128 is formed on the control gate 126" to a thickness of about 300 A. 曰 1293200 18424 twf.doc/y Referring to Figure 3B, a first oxide layer is deposited or formed The telluride memory cell stacks (i.e., layers 122, 124, 126, 128) are patterned and etched to form a first set of oxide masks that are spaced apart to define a first set of spaced font cells. 13G. In the implementation of two, such as oxygen = f ^ 130 thickness between about _ ~ 1 A, and more preferably about. Oxide fresh 13G by - using the light micro-material imaging of the photoresist, To form a patterned oxide layer, where "F" #imageable =, size. Each mask m has a width F. Next, a leg is deposited on the structure, ie deposited on the oxide material (10) And on the 2nd layer 128 of the Shixi. For example, 3:0 AS ΪΪ!3 2 is deposited by low pressure chemical vapor deposition (LPCVD) to a thickness less than F, and in one embodiment is about F+2X. 'Oxide material 13G area is separated from each other - segment distance

F is the distance from the line of the γΓ x Gu 2 shown in 2. The distance is defined by the U-wire (four) process, and the size of the ship is as small as the remaining process. The in-experimental endpoint detection can be used to detect the oxygen in the anisotropy of the reaction gas for the etching of the SiN layer 132. 1 thicker than the formation; Because of the s ii of the oxide portion of the scheme, the spacer 132 is detected to have a thickness equal to "γ 2 and only a portion of the Si." spacer, and the deposition thickness of the layer 132 is: Between the lines of the word lines &amp; 12 1293200 18424twf.doc / y Referring to Figure 3D, a second oxide layer (not shown) is deposited on the structure of Figure 3C to fill the gap 132, the opening between Spaced and etched back to retain a second set of spaced oxide masks 134. Oxide mask 13 〇 continues to exist, but is designated 13 〇 ' because during the exposure of the spacers 132 ′ through the second oxide layer It may be slightly etched. Each oxide portion 130, 134 has a width equal to F and is spaced apart from an adjacent oxide portion by a spacer 132 having a width equal to χ, where X is less than F. 13〇, and &gt; 134 together form an oxide mask for forming spaced word lines and memory cells. Although only U oxide mask portions are shown, it should be understood that 16, 32 may be provided. Or 64 parts to form the number of word lines in the cell string' and provide additional oxidation Partially used to form the selective transistor (not shown in the alternative embodiment, the masks 130, 134 are formed of SiN, and the layer 132 (and thus the spacers 132,) is formed of an oxide. 曰 See Figure 3E, shift In addition to the SiN spacers 132, the oxide mask layer of FIG. 3D is used to etch the transmissive layers 122, 124, 126, and 128 to form the spacer memory cells i8 of FIG. 2 having a width f and spaced apart from each other. A distance X. A dry etching process using an Ar/CF4 reaction solution can be used to remove the SiN spacer 132'. A dry etching process using a Cb/HBr solution can be used to etch the gate polysilicon layer 126, and The same solution can be used to etch the vaporized layer 128. A dry etching process using a CHFVCHFVHe solution can be used to etch the germanium dielectric layer 124. Finally, one can be used

The dry etching process of the Ch/HBr solution is used to etch the floating gate polysilicon layer 122 〇 θ 13 1293200 18424 twf.doc / y as shown in FIG. 3F 'as an etching process 134 , and the implanted region 14 is formed in the US Scythe 1 state and individual cell unit 18. Adjacent and interposed in the substrate 1G, a cell array can also be used instead of the stylization/erasing method, which utilizes a thermoelectric hole through the BTBT (food 匕) U body day Q 匕 匕 间 牙 tooth tunnel &gt; Into the intersection of the stored/exposed (S/D) junction and the wear-through oxide in the program. For n+s/D counties, the junction is reverse biased to a certain degree, causing the soft material or Zener (3) to collapse. The pn junction has current when electrons pass from the valence band to the conduction band at the S/D and the intersection. The hole is generated by the valence band, and the floating (four) pole attracts the hole by applying a negative voltage to the control gate. The negative voltage on the control gate also enhances the BTBT current. If the accessed cell is not programmed, the bit line is biased at 0V and the S/D junction is not reverse biased. Under: conditions there is no BTBT tunneling current. Erasing is performed by having all of the cells in a selected block have a higher critical value. During erasing, electrons tunnel from the channel to the floating gate through FN tunneling. Stylized, erased, and read conditions are summarized in the following table.

Erase the programmed read selection of WL 20 V -5 V 0 V Unselected WL 20 V 10 V , V/ V 4 5 V SSL VCC 10 V 4.5 V GSL 0 V Floating 4.5 V BL (stylized 〇) 0 V 7 V 14 1293200 18424tw£d〇c/y

The hot hole injection produces a trapping tunneling oxidation and erasing durability. The electric two = 'and can reduce the effect of the process on the edge of the thermoelectric injection of the second channel, which will lower the electric field near the drain and make the hot electron effect = hole because the erase is over the entire tunnel oxide : And 'two methods in this mechanism = low due to _uN0R flash memory can cause dry pressure from the bit line. Suppose, for example, that WL2 is selected and a unit cell is programmed. WL 〇 and WL1 are unselected word lines between the selected word line and the bit line. Pull WLO, WL1, and SSL to 10 V. Set WL2 to -5 V. There is no interference in the body. Unselected word line = Yuan line voltage passed. The unit cell on the set when it is not transferred does not have the interference. The lion-free block also has a -selective transistor to protect the unit cell. The bit line voltage cannot be transferred to the unit cell. To ensure that the S/D junction is reverse biased, the S/D requires a positive bias. The 7 V bias on the bias line will pass through the S/D region between WL1 and WL2. The S/D region will have a BTBT tunneling current. The negatively biased WL2 attracts the hole to the floating gate of this unit cell. Since WL2 is negatively biased and the bias voltage is lower than the Vth of the erased state, the cell is turned off. Therefore, the 7 V bias will not pass to WL3 and other word lines. 15 1293200 18424 twf.doc/y Figures 4A to 4D illustrate the process described above in connection with Figures 3A to 3F, which are applicable to § ONOS (矽/ΟΝΟ/矽) memories as described in U.S. Patent No. 6,580,120 to Haspeslagh. Formation of bulk unit cells, which is herein incorporated by reference in its entirety. In FIGS. 4A to 4D, similar component symbols as in FIGS. 3A to 3F refer to a similar structure. As shown in FIG. 4A, a tantalum layer 200 is formed on the substrate 10. The tantalum layer 200 preferably has an effective oxide thickness of between about 110 and 140 Torr. Layer 200 includes a first insulating layer 202, a storage layer 204, and a second insulating layer 206. The tantalum layer may be deposited using a LPCVD (Low Pressure Chemical Vapor Deposition) process having a top oxide layer 206 deposited from SiH2CL2/02 gas to a thickness of about 20 A, having a bottom deposited from SiH2eLV(R) 2 gas to a thickness of about 40 A. Oxide layer 202, and having a SiN storage layer 204 deposited from SiHfl^/N2 gas to a thickness of about 80 A, is substantially the same as described above in connection with Figures 3A-3F. A control gate polysilicon layer 126 is formed over layer 200. A vaporized layer 128 is formed as appropriate, after which a first set of spaced oxide masks 13 and SiN layers 132 are formed. Referring to FIG. 4B, the SiN layer 132 is etched to form the SiN spacers 132. In Figure 4C, a second oxide layer is deposited and etched to expose the SiN spacers 132' leaving a second set of spaced oxide masks 134. As shown in Figure 4D, the SiN spacers 132' are removed and then the mask set is used for = penetrating vaporization layer 128 and top polysilicon layer 126. Person 1293200 18424twf.doc/y In the example, Figure 4D shows the final unit cell structure, although the illustrated mask portions 130' and 134 are removed. In an alternate embodiment, the etch process continues from 〇N 层 layer 20Q to substrate 10. In this alternative embodiment, an implanted region (as shown in Figure 3F above) is formed and FN is tunneled for programming/dividing. Stylized/erase/read conditions for implant embodiments are shown in the table below for NMOS cells. &lt;

ί^___ stylized read floating float

12~15 V 6~9 V 6~9 V 0 V 0 V 4.5 V 4.5 V 4.5 V

The selected WL unselected WL SSL GSL... BL (stylized 〇) BL (the stylized 1 ontology does not exist in the implanted area' then the source side is injected (8 〇 ^ ^ as injection) for stylization, And the use of the FN is used for erasing. The stylized/erasing method is described in U.S. Patent No. 6,58(), 12(), the entire disclosure of which is incorporated by reference. An exemplary reading condition is also described. A good T, described above, in the present invention, a method of forming a word line having a reduced interval and forming a unit cell thereof, the method having a preferred accumulation system 1293200 18424twf.doc/y. The small cell spacing improves the accumulation density, thereby reducing the size and/or capacity of the device. Although the invention has been disclosed above in the preferred embodiment, it is limited to the invention, any familiarity This artist is not taking off

Within the scope of 1σ, when a few changes and refinements can be made, the date of this application is defined by the scope of the patent application. ” X [Simple description]

Figure 1 is a partial circuit diagram of a plurality of NAND memory cells. "~, Figure 2 is a cross-sectional view of a cell string of an exemplary memory device, and 1 shows a sub-line spacing. 霄3A~3F illustrate - an exemplary method of fabricating the structure of Figure 2. 4A~4D 言 明 明 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一

BL0, BL1: bit line WL0, WL WL2, ..., WLn: word line SSL, GSL: selection line Mnm: memory cell SL0, SL1, GSL0, GSL1: selection transistor 10: substrate 12: Mitsui region 14: implanted region 16: gate dielectric layer 1293200 18424twf.doc/y 1 8 : memory cell 20a, 20b: selective transistor 22, 122: floating gate 24, 32, 34, 124 · · insulating layer 26, 126: control gate 28, 128: germanide layer 30: plug 36: conductive bit line 38: via _ 130, 130, 134 · oxide mask 132 · SiN layer η3 Τ 2, · Clearance wall 200 ·· ΟΝΟ Layer 202, 206 ··Insulation layer 204: Storage layer F, X ·· Dimensions

Claims (1)

1293200 18424twf.doc/y X. Patent Application Range: 1. A method of forming a reverse (NAND) flash memory device comprising the steps of: forming a gated polysilicon layer on a substrate; Forming a mask layer on the gate polysilicon layer, wherein the mask layer includes a fresh pattern defining a plurality of spaced word lines of the opposite (4) memory, the word lines being _-distance from each other The distance is less than a minimum feature size, the minimum feature size being imaged by a selective photolithography process for forming at least a portion of the pattern, and etching the control gate through the mask layer Polycrystalline germanium layer. The method for forming a reverse flash memory device according to the first aspect of the invention, wherein the mask layer forming step comprises the following steps: forming a layer on the control gate polycrystalline layer a first layer, and using the mask, to form the first layer to form a first set of spaced masks and two knives, the first set of spaced mask portions defining a first group of sub-elements a line forming a gap _ layer on the side edge of the first group of spaced mask portions; the second layer defining a first set of spaced word lines between the gap walls; And = dividing the spacer, thereby patterning the mask pattern of a plurality of spaced lines. 1293200 18424twf.doc/y 3 · device = please refer to the formation of item 2 and the flash memory wall contains nitriding) and the fossil eve (snsn 曰匕 3, oxide 'or The first and second layers comprise nitrogen (N) and the spacers comprise an oxide. The device 4 of the device 4, the range of the third embodiment of the formation of the anti-flash memory description __成步欢 includes the following Step: between the mask portions; and the spacer layer on the layer and the first layer and the first group spaced apart to form the spacer layer. The second name forming step includes the following steps: · depositing the second layer on the method of forming the anti-flash memory coating described in item 2 The substrate is coated on the spacer; and the second layer is etched to expose the spacer. The method of forming the anti-flash memory on the fifth aspect of the patent application is disclosed. The first layer of the towel has a thickness of about -1 Α, and the spacer has a thickness of about 300 A. Further, as in the patent application The method of forming a reverse flash memory device as described in item i, further comprising the step of forming an implant region in the substrate between the spaced word lines π after the side step. 8. The method of forming a reverse flash memory 1 according to claim i, wherein the control gate polycrystal layer is formed on an _ oxide/nitride/oxide layer 21 1293200 18424twf.doc/y 9. The method of forming a reverse flash memory device according to the above-mentioned item 7, wherein the oxide/nitride/oxide (〇n〇) layer has - an effective oxide thickness between about 11 G and 14 G A. 10. A method of forming a counter-flash memory device as described in the above-mentioned U-Patent Feu, further including a plurality of (four) layers of the control gate The method of forming a vaporization layer on the substrate, wherein the method of forming the anti-flash memory device according to claim 1 further comprises the steps of: forming a layer on the active region of the substrate a very polycrystalline layer in the floating region; and a layer formed on the floating gate polycrystalline layer a layer, wherein the etchant comprises etching the floating interpolar polycrystal step. 曰j body device: forming a reverse and flashing on the substrate to form a first insulating layer, at the first Forming a storage layer on the insulating layer; forming a second insulating layer on the storage layer, wherein the control gate polysilicon layer is formed on the insulating layer. Method, the mask layer comprises an oxide. 14. A method for forming a reverse flash memory. The method comprises the steps of: forming a dielectric layer on a substrate; 22 1293200 18424twf.doc/y Forming a polysilicon control gate layer on the electrical layer; depositing a first mask layer on the polysilicon control gate layer; and forming the first mask layer to form a first group of spaced masks Single-part, and the first set of spaced mask portions define a first set of spaced word lines/per-mask portions having a width and the width is dependent on a minimum feature size imaged by the selected light path Separate intervals - distance and said Greater than the minimum impurity size and from twice the minimum feature size; forming a first set of spaced mask portions and the second set of spaced mask portions defining a second set of spaced word lines, Individual mask portions of the second set of spaced apart mask portions are disposed between adjacent mask portions of the first set of mask portions, wherein the second set of spaced mask portions are individually covered The cover portion is configured to be spaced apart from the mask portion adjacent the first set of mask portions and the distance is less than the minimum feature size; and the mask portion is etched by the first and second groups of spacers The polysilicon control gate layer. 15. The method of forming a reverse flash memory device according to claim 14, further comprising the steps of: forming a sacrificial layer on the mask portion of the first set of intervals; a layer forming a spacer on a sidewall of the first set of spaced mask portions; forming a mask material layer on the first set of spaced mask portions and spacers; 23 1293200 18424twf.doc/y Eight etching the layer of masking material to expose the first set of spaced masking knives, wherein portions of the layer of masking material remain to form the second set of spaced apart mask portions; and removing the Clearance wall. A method for forming a reverse flash memory I according to claim 14 wherein the mask portions of the first and second sets of spacers comprise an oxide or tantalum nitride ( SiN). A method of forming a reverse flash memory device according to claim 14, wherein the dielectric layer comprises an oxide/nitride/oxide (germanium) layer. 18. The method of forming a reverse flash memory as described in claim 17, wherein the oxide/nitride/oxide layer is formed/formed on the substrate, The method further comprises forming a reverse flash memory device, the method further comprising the step of removing the mask portion, wherein the oxide/nitride/oxide layer is substantially unsaved . 19. The method of forming a reverse flash memory-disposing method according to claim 17, wherein the dielectric layer is formed on the floating gate polycrystalline layer. A mask portion through the first and second sets of spacers _ the dielectric layer and a floating interposer polycrystalline layer are included. 20. A method of forming a reverse flash memory device, the method comprising: forming a gate polysilicon layer on a substrate; forming a mask layer on the gate of the control gate (10) The mask b includes a plurality of spaced mask portions defining a plurality of spaced characters 24 1293200 18424 twf.doc/y lines of the flash memory device, each mask width, and a mask portion thereof _ 罩 罩 罩 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2L. The method of forming an anti-flash device according to claim 20, wherein the mask layer comprises 7 oxide or nitride (^N) 〇 The method of forming a reverse flash memory device according to claim 21, further comprising forming an oxide/nitride/oxide layer on the substrate and performing the oxidation The step of forming the gate polysilicon layer on the layer of material/nitride/oxide (〇N〇). 25