TWI290756B - Leadframe and chip package applying the same - Google Patents

Leadframe and chip package applying the same Download PDF

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Publication number
TWI290756B
TWI290756B TW095100052A TW95100052A TWI290756B TW I290756 B TWI290756 B TW I290756B TW 095100052 A TW095100052 A TW 095100052A TW 95100052 A TW95100052 A TW 95100052A TW I290756 B TWI290756 B TW I290756B
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Taiwan
Prior art keywords
lead frame
frame unit
wafer
units
filling
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TW095100052A
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Chinese (zh)
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TW200727419A (en
Inventor
Kuo-Sheng Chung
Hui-Chin Fang
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Advanced Semiconductor Eng
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Priority to TW095100052A priority Critical patent/TWI290756B/en
Publication of TW200727419A publication Critical patent/TW200727419A/en
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Publication of TWI290756B publication Critical patent/TWI290756B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadframe including multiple leadframe assemblies is provided, wherein each leadframe assembly includes multiple leadframe units. Each leadframe unit includes a chip holder, multiple leads, and a molding gate. The leads are disposed around the chip holder, and the molding gates of the leadframe units in each leadframe assembly are centralized.

Description

1290756 17770twf.doc/r 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於一 種具有較佳之封膠(molding)效果的晶片封裝製程。 【先兩技術】 在半導體產業中，積體電路（Integrated Circuits，IC)的 生產主要分為三個階段：積體電路的設計、積體電路的製 Φ 作及積體電路的封裝（Packa§〇等。在積體電路的封裝中， 裸晶片係先經由晶圓（wafer)製作、電路設計、光罩製作以 及=割晶圓等步驟而完成，而每一顆由晶圓切割所形成的 裸曰曰片，經由裸晶片上之焊墊（b〇n(Jing pa(J)與承載器 Reamer)電性連接後，再藉由封膠材料將裸晶片加以包 ^其目的在於防止裸晶片受到外界之濕氣、熱量及雜訊 等影響，其中在目前的半導體製程中，導線架（leadframe) 是經常使用的構裝承載器之一。 圖1疋習知之一種導線架的上視圖。請參考圖丨，習 •=之導線架10〇包括多個導線架單元11〇，每一個導線架 單元110則包括一晶片座112、多個導腳114及一灌模澆 庄口 116，其中導腳114是配置於晶片座112周圍。特別 的是，每一個配設於導線架單元11〇上之灌模澆注口 ιΐ6 有相同的配設位置。圖2A是晶片與圖丨之導線架接合後 的上視圖，圖2B是圖2A之晶片封裝結構進行封膠製程後 的上視圖。請芩考圖2A，習知之導線架100上的每一個晶 片座112配設有一晶片no,其中晶片120上有多個焊墊 I29(m〇c/r 120a，而焊墊i2〇a可蕻由容 no之導腳114電性連^線140來與導線架單元 元η::形示’進行封膠製程，以在導線架單 用模呈以n、衣f體16G’。請同時參考圖3，其緣示利 用杈八以進仃封膠製程的示意圖 應於導線架單元11()㈣·、/ 具有對BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor process, and more particularly to a wafer package process having a preferred sealing effect. [First two technologies] In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the design of integrated circuits, the fabrication of integrated circuits, and the packaging of integrated circuits (Packa§ In the package of the integrated circuit, the bare die is first completed by wafer fabrication, circuit design, mask fabrication, and wafer cutting, and each wafer is formed by wafer cutting. The bare die is electrically connected to the pad (bingn (Jing pa (J) and the carrier Reamer) on the bare wafer, and then the bare wafer is packaged by the sealing material to prevent the bare wafer It is affected by the external moisture, heat and noise. Among the current semiconductor processes, the leadframe is one of the frequently used carrier carriers. Figure 1 is a top view of a conventional lead frame. Referring to the drawing, the lead frame 10 of the ••= includes a plurality of lead frame units 11〇, each of the lead frame units 110 includes a wafer holder 112, a plurality of guide legs 114, and a filling die 116, wherein The foot 114 is disposed around the wafer holder 112. The filling gates ι 6 of each of the lead frame units 11 have the same arrangement position. FIG. 2A is a top view of the wafer and the lead frame of the drawing, and FIG. 2B is the wafer of FIG. 2A. A top view of the package structure after the encapsulation process. Referring to FIG. 2A, each of the wafer holders 112 on the lead frame 100 is provided with a wafer no, wherein the wafer 120 has a plurality of pads I29 (m〇c/ r 120a, and the solder pad i2〇a can be electrically connected to the lead frame unit η:: indicates that the lead frame unit is electrically sealed to form a sealing process for the lead frame n, clothing f body 16G'. Please also refer to Figure 3, the point of view is to use the 杈 eight to enter the 仃 sealing process diagram should be in the lead frame unit 11 () (four) ·, / have

Bi , θ 0 )夕们枳八2〇〇a，當進行封膠製程 二係將杈具200包覆導線架1〇 對應位於模穴聽中 =于¥線木早兀110 填入封膦铋Μ 门在权具200之灌部（P〇t)200b 膠材来對封膠材料160加熱施屢，以使封 内，財^者模具MO内的模流通道綠注入模穴施 ㈣母—導線架單元UG上形成封裝膠體·，。形成 目的在於包覆晶片12。、導線14。及: :汗;;:;元"。5以避免晶片1峨 羽4 参考圖2B與圖3，為了便於後續脫模的方便， 二:導線架單元HO的同-角落形成-灌模洗注 一 ^在’主.日守使彳于封膠材料160經由每一個導線架 曰兀10的灌模澆注口 116流入模穴2〇如内。值得注意的 3所示之習知導線架100的配置方式，是在模具 一狄、/翟部200b的兩側分別放置一條導線架10〇，其中每 1線架1GG上通常會有多行導線架單元11〇。 曰$而，由於每一條導線架單元110上的灌模澆注口 116 為每二^同的相對位置上，因此在進行封膠製程時，會因 母^線架單元110與模具200之灌部200b的距離不 6 I29〇mwl f.doc/r 同，而產生封膠效果不一致的問題。更詳細地說，由於流 道，度的不同’導致_材料⑽流至每—_穴 而其模流速度也不相等。如此—來，將使得 :一核八2〇〇a之封膠材料16〇的固化時間長短不一致，而 =同的固化程度，進而影響晶片封裝結構的可靠度。另 速产==由：2時，每一模穴2〇〇a之封膠材料的模流 =不至欠，使得每—導線架單元11〇會有不同的沖線變 局也間接增加了線路設計上的困難度。 ^ 【發明内容】 上述之改:::導j力的是提供-種晶片封裝製程，可藉由 為達來解決習知封膠效果不佳的問題。 包括多個導線架單元級目二f日;提力出二種導線架，其 導線架單元，且每一、八母導線架單元組包括多個 腳及一灌模洗注"Γ導線架單元包括—晶片座、多個導 線架單元組内i多個，Γ是圍繞著晶片座配置，而導 置。 v線罙早元的灌模澆注口是集中配 在本發明之一嫌厶 括相鄰的兩個導線广例中，每—個導線架單元組可以包 口例如分触於執姑導_單元的灌模洗注 在本發明之一；相鄰的-角落上。 、也例中，母一導線架單元組可以包括 7 I29〇m wf.doc/r 四個導線架單元，发 單元的灌模纽口例成—2X2矩陣，且這些導線架 角落上。 ^位料些導、_單元相鄰的- 本备明再提出—種晶片 提供上述之導_。接著;好料：首先， -晶片，並使日日日片電性至==之母—日日日片座上配置 後，進行-封谬曰曰片座周圍的多個導腳。之 封裝膠體於每一個導’線些::J注口同時形成-少覆蓋其所對應的晶片’其中母-個封裝膠體至 ，本發明之—實施例中’封 ―极具’並使模具包覆導線架 ★供 組之多個灌模繞注口的上 =*母一導線架單元 這些灌鶴注口而將封膠材料注料。之後’經由 線架單元上形成封裝膠體。 一内’以在每—個導 在本發明之一實施例中，使每— 所對應之多個導腳的方 口曰曰片祕連接至其 透過多條導線電性連接晶片與打線接合製程，以 之灌模ί注广’題，係對導線架上 兀的灌模洗注口集中配置，並由== 目鄰之導線架單 :亍注膠的動作。如此一來，封膠材;==中處進 將可大幅改善封裝膠體的固化:二，間幾乎 導線架單元具有相同之沖線變形量 ^ 題，且每-之線路佈局的設計較為容易。 •曰曰片與導線架 I2907^twf.—/r 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】Bi , θ 0 ) 夕 枳 〇〇 〇〇 〇〇 〇〇 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The door is heated in the potting part of the right armor 200 (P〇t) 200b to heat the sealing material 160 so that the mold flow channel in the mold MO is injected into the mold hole (four) mother- An encapsulant colloid is formed on the lead frame unit UG. The purpose is to coat the wafer 12. , wire 14. And: : Khan;;:; Yuan ". 5 to avoid wafer 1 feathers 4 refer to Figure 2B and Figure 3, in order to facilitate the convenience of subsequent demoulding, two: the same-corner formation of the lead frame unit HO - filling the mold a ^ in the 'main. The sealant material 160 flows into the cavity 2 through the potting spout 116 of each lead frame 10 . It is noted that the conventional lead frame 100 shown in FIG. 3 is arranged such that a lead frame 10 放置 is placed on both sides of the die 1 and the 翟 200b, and there are usually multiple rows of wires on each of the 1 GG racks 1GG. The shelf unit 11〇.曰$, because the filling nozzles 116 on each lead frame unit 110 are in the same relative position, so when the sealing process is performed, the filling unit of the mother and the mold unit 110 and the mold 200 The distance of 200b is not the same as that of I29〇mwl f.doc/r, and the problem of inconsistent sealing effect is generated. In more detail, due to the different degrees of the flow path, the material (10) flows to each of the holes and the mold flow speed is not equal. In this way, the curing time of the 16 〇A sealing material of a core of 8 〇〇a is inconsistent, and the same degree of curing, which in turn affects the reliability of the chip package structure. Another speed production == by: 2, the mold flow of the sealing material of each cavity 2〇〇a = not owed, so that each wire frame unit 11〇 will have different rushing lines and indirectly increase the line The difficulty of design. ^ [Summary of the Invention] The above changes:: The introduction of the force is to provide a kind of chip packaging process, which can solve the problem of poor sealing effect by the conventional method. Including a plurality of lead frame unit level 2 f day; lifting two kinds of lead frame, its lead frame unit, and each and eight female lead frame unit group includes a plurality of feet and a filling mold " Γ lead frame The unit includes a wafer holder and a plurality of plurality of lead frame unit groups, and the crucible is disposed around the wafer holder and guided. The filling line of the v-line 罙 early element is concentrated in one of the two examples of the adjacent two wires of the present invention, and each of the lead frame unit groups can be covered by the stalking unit. The filling of the mold is in one of the inventions; adjacent to the corners. In another example, the mother-lead frame unit group may include four I lead frames of 7 I29〇m wf.doc/r, and the filling port of the transmitting unit is exemplified by a -2×2 matrix, and these lead frames are on the corners. ^The material is guided, the _cell is adjacent - this is a further description - the kind of wafer provides the above _. Next; good material: First, - the wafer, and the day and day electricity to the mother of the == day-day seat, after the configuration, carry out - a number of guide feet around the seat. The encapsulant of the package is formed on each of the wires: the J-junction is simultaneously formed - less covering the corresponding wafers, wherein the mother-package colloids are, in the embodiment of the invention, the 'sealing-electrode' and the mold Covered lead frame ★ For the group of multiple filling molds, the upper = * female one lead frame unit, these grouting nozzles will be used to fill the sealing material. The encapsulant is then formed on the bobbin unit. In one embodiment of the present invention, each of the corresponding plurality of lead pins is connected to the wafer and the wire bonding process is performed by connecting the wires to the wires through a plurality of wires. In order to fill the mold with 广 广 广 广 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 In this way, the sealant; == in the middle will greatly improve the curing of the encapsulant: Secondly, almost the lead frame unit has the same amount of punching deformation, and the layout of each line layout is relatively easy. The above and other objects, features and advantages of the present invention will become more apparent from the aspects of the accompanying drawings. described as follows. [Embodiment]

圖4A至圖4C是本發明較佳實施例之一種晶片封裝製 私的流程示意圖。首先，如圖4A所示，提供一導線架400。 在本實施例中，導線架400包括多個導線架單元組41〇(圖 4=僅繪示1個），其中每一個導線架單元組41〇包括多個 導線架單7L 412。每一個導線架單元412則包括一晶片座 412a、多個導腳412b及一灌模澆注口 412c，這些導腳412b 疋圍繞著晶片座412a配置。特別的是，本實施例中的導線 ，單το組410内之多個導線架單元412的灌模澆注口 412c =集中配置。舉例來說，本實施例之每一導線架單元組4 j〇 疋由四個導線架單元412所組成，其可排列成一 2χ2矩 陣’且這些導線架單元412的灌模澆注口 4i2c分別位於這 些導線架單元412相鄰的一角落上。 =外，導線架400例如有一外框4〇2與多個支撐條 合日日片座412a與導腳412b均位於外框402内，而這些 支404可連接於晶片座412a與外框402之間，以固定 扩Ini座412&。$外，導線架400更可以包括一導腳連接 些導腳4ΐΪΓ、Γ外才匡4〇2内/且與這些支擇條404以及這 ’ 連接，以強化導線架400的結構，並使得導腳 此更為穩固。 接著，如圖4Β所示，在導線架400的每一個晶片座 9 129〇敬_ 412a上配設一晶片420，並使晶片42〇電性連接至晶 412a周圍的多個導腳412b。舉例來說，使晶片42〇 ^性 接至其所對應之多個導腳412b的方法是進行一打: 製程，以藉由多條導線440連接晶片42G上的多個ς 420a與導線架單元412之導腳412b。4A through 4C are schematic views showing the flow of a wafer package manufacturing process in accordance with a preferred embodiment of the present invention. First, as shown in FIG. 4A, a lead frame 400 is provided. In the present embodiment, the lead frame 400 includes a plurality of lead frame unit groups 41 (Fig. 4 = only one), wherein each lead frame unit group 41 includes a plurality of lead frame sheets 7L 412. Each of the lead frame units 412 includes a wafer holder 412a, a plurality of lead pins 412b, and a filling gate 412c. The lead pins 412b are disposed around the wafer holder 412a. In particular, the wires in the present embodiment, the filling gates 412c of the plurality of lead frame units 412 in the single τ group 410 are collectively arranged. For example, each lead frame unit group 4 of the present embodiment is composed of four lead frame units 412, which can be arranged in a matrix of 2χ2 and the filling gates 4i2c of the lead frame units 412 are respectively located. The lead frame unit 412 is adjacent to a corner. In addition, the lead frame 400 has, for example, an outer frame 4〇2 and a plurality of support strips. Each of the day holders 412a and the guide legs 412b are located in the outer frame 402, and the branches 404 are connectable to the wafer holder 412a and the outer frame 402. In between, to expand the Ini seat 412 & In addition, the lead frame 400 may further include a lead connecting the lead pins 4, 4, and/and the connecting strips 404 and the 'connections to strengthen the structure of the lead frame 400, and The foot is more stable. Next, as shown in FIG. 4A, a wafer 420 is disposed on each wafer holder 9 129 〇 _ 412a of the lead frame 400, and the wafer 42 is electrically connected to the plurality of lead pins 412b around the crystal 412a. For example, the method of connecting the wafer 42 to the corresponding plurality of leads 412b is performed by a process of: connecting a plurality of wires 420a and lead frame units on the wafer 42G by a plurality of wires 440. Guide pin 412b of 412.

之後，如圖4C所示，進行—封膠製程，以在每一個 導線架單元412上同時形成一封裝膠體46〇，，其中每一個 封裝膠體460’至少覆蓋其所對應的晶片42〇('請參考^ 4B)。值得-提的是，在導線架單元412上形成封裝膠體 460’後，會對導線架400進行剪切（trimming)的動作〔以 將導線架400之外框402、部份支撐條404與導腳連接框 406去除。如此，即可得到多個晶片封裝結構。 請同時參考圖5，其繪示利用模具以進行圖4C所示 之封膠製程的示意圖。如圖5所示，模具500例如呈有對 應於導線架單元412的多個模穴5〇〇a，當進行封膠製程 時，係將模具500包覆導線架4〇〇，使得導線架單元412 對應位於模穴500a中。同時，在每一導線架單元組41〇(請 麥考圖4A)之灌模澆注口 412c的集中處配置一封膠材料 460,其例如是一膠餅。在本實施例中，例如是將封膠材料 460填入模具500的灌部5〇〇b内。之後，便可藉由對封膠 材料460施壓，而將封膠材料46〇經由灌模澆注口 4ι“ 1入模具5〇〇内，以在每一個導線架單元412上形成封裝 膠體460’。其中，封裝膠體460,包覆晶片420、導線44〇 及部份之導線架單元412，以提供保護的功能。 謂傲㈤r 值得一提的是，本實施例 設於每-導線轉认简齡_並不限定配 口仙的上方。在本發明之圖Μ之多個灌模洗注 膠材料460配置於盡^加/他貝施例中，更例如可將封 之模流通道（未緣示）的言^計^ ’並藉由模具500内 個導線架單元組410中:灌界^材料460導引到每一 架單元412的灌模洗注口 412=隹考圖4A)之每一個導線 的距離相同，而從每-個灌模洗注口 412c i:二： 目同之流速。如此，每二： 中線相=變:量，進而有利封裝結構 每—導線牟單开4〗9u方面，由於注膠時間相等，因此 時間，因此F有助於ί之封膠材料460可具有相同的固化 升晶月封裳的可靠度，進而提 架單元的獅^ ^崎強觸重點在於將相鄰導線 芊罩-//衩口木中配置，因此並不限定每一個導線 括相鄰的兩個導線架單元，且這些 的—角$卜二口可分別位於這些導線架單元相鄰 之灌以相::：些導線架單元的灌模洗注口至模具 雖然本發明已以較佳實施例揭露如上，然其並非用以 12.9〇7漁一 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知之一種導線架的上視圖。 圖2A是晶片與圖1之導線架接合後的上視圖。 圖2B是圖2A之晶片封裝結構進行封膠製程後的上视 圖。 瞻 圖3是利用模具以進行封膠製程的示意圖。 圖4A至圖4C是本發明較佳實施例之一種晶片封裝製 程的流程示意圖。 圖5是利用模具以進行圖4C所示之封膠製程的示意 圖。 【主要元件符號說明】 100 導線架 110 導線架單元 112 晶片座 114 導腳 116 灌模澆注〇 120 晶片 120a :焊墊 140 ： 導線 160 ： 封膠材料 160, :封裝膠體 12Thereafter, as shown in FIG. 4C, a sealing process is performed to simultaneously form an encapsulant 46 在 on each of the lead frame units 412, wherein each of the encapsulants 460 ′ covers at least the corresponding wafer 42 〇 (' Please refer to ^ 4B). It is worth mentioning that after the encapsulation colloid 460' is formed on the lead frame unit 412, the lead frame 400 is trimmed (to guide the outer frame 402 of the lead frame 400, the partial support bar 404 and the guide The foot link 406 is removed. In this way, a plurality of chip package structures can be obtained. Please also refer to FIG. 5, which illustrates a schematic diagram of using the mold to perform the encapsulation process shown in FIG. 4C. As shown in FIG. 5, the mold 500 is, for example, provided with a plurality of cavities 5〇〇a corresponding to the lead frame unit 412. When performing the encapsulation process, the mold 500 is wrapped around the lead frame 4〇〇 so that the lead frame unit 412 is correspondingly located in the cavity 500a. At the same time, a glue material 460, which is, for example, a gum cake, is disposed at the center of the potting sprue 412c of each lead frame unit group 41 (Mc. Fig. 4A). In the present embodiment, for example, the sealant 460 is filled into the filling portion 5〇〇b of the mold 500. Thereafter, the sealing material 46 can be pressed into the mold 5 through the filling gate 4 by pressing the sealing material 460 to form the encapsulant 460' on each of the lead frame units 412. The encapsulant 460 encapsulates the wafer 420, the wires 44, and a portion of the lead frame unit 412 to provide a protective function. It is said that (5) r It is worth mentioning that the present embodiment is set on each-wire transfer confirmation. The age _ is not limited to the upper side of the matching scent. In the figure of the present invention, a plurality of filling squeegee materials 460 are disposed in the ^ 加 / / / / / / / / / / / / / / / / / The sufficiency of the sufficiency of the stencils 412 = 图 图 图 ' 内 内 内 内 内 内 内 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具 模具The distance of each wire is the same, and from each of the filling nozzles 412c i: two: the same flow rate. Thus, every two: the middle phase = variable: the amount, which is advantageous for the package structure per wire 4〗 9u, because the injection time is equal, so time, so F helps the sealing material 460 can have the same curing liter The reliability of the moon-studded skirt, and then the lion's strong focus of the racking unit is to arrange the adjacent wire cover-//mouth wood, so it is not limited to each of the two adjacent lead frames. Units, and the angles of the two can be respectively located adjacent to the lead frame units. The filling of the lead frames of the lead frame units to the molds. Although the present invention has been disclosed in the preferred embodiment as above However, it is not intended to limit the invention to 12.9, and the skilled person can make some modifications and retouchings without departing from the spirit and scope of the invention, so that the scope of protection of the present invention is regarded as BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top view of a conventional lead frame. Figure 2A is a top view of the wafer after engagement with the lead frame of Figure 1. Figure 2B is Figure 2A The top view of the wafer package structure after the encapsulation process is shown in Fig. 3. Fig. 4A to Fig. 4C are schematic diagrams showing the flow of a wafer package process according to a preferred embodiment of the present invention. 5 is to use the mold to A schematic diagram of the encapsulation process shown in Fig. 4C. [Main component symbol description] 100 lead frame 110 lead frame unit 112 wafer holder 114 lead pin 116 potting casting 120 wafer 120a: pad 140: wire 160: sealing material 160, : encapsulant 12

I2.9〇H 200 :模具 200a :模穴 200b :灌部 200c :模流通道 400 :導線架 402 :外框 404 :支撐條 406 :導腳連接框 ❿ 410 :導線架單元組 412 :導線架單元 412a :晶片座 412b :導腳 412c :灌模澆注口 420 :晶片 420a :焊墊 440 :導線 φ 460 :封膠材料 460’ ：封裝膠體 500 :模具 500a :模穴 500b :灌部 13I2.9〇H 200: mold 200a: cavity 200b: irrigation part 200c: mold flow channel 400: lead frame 402: outer frame 404: support bar 406: lead connection frame ❿ 410: lead frame unit group 412: lead frame Unit 412a: wafer holder 412b: lead 412c: filling gate 420: wafer 420a: pad 440: wire φ 460: sealing material 460': encapsulant 500: mold 500a: cavity 500b: filling portion 13

Claims (1)

129071- 十、申請專利範圍： 1. 一種導線架，包括多個導線架單元組，其中每一導 線架單元組包括多個導線架單元，且每一導線架單元包括： 一晶片座， 多個導腳，圍繞該晶片座配置；以及 一灌模澆注口，其中每一導線架單元組内之該些導線 架單元的該些灌模澆注口係集中配置。 2. 如申請專利範圍第1項所述之導線架，其中每一導 _ 線架單元組包括相鄰的兩個導線架單元，且該些導線架單 元的該些灌模澆注口係分別位於該些導線架單元之相鄰的 一角落上。 3. 如申請專利範圍第1項所述之導線架，其中每一導 線架單元組包括四個導線架單元，其係排列成一 2x2矩 陣，且該些導線架單元的該些灌模澆注口係分別位於該些 導線架單元之相鄰的一角落上。 4. 一種晶片封裝製程，包括： | 提供一導線架，該導線架包括多個導線架單元組，每 一導線架單元組包括多個導線架單元，且每一導線架單元 包括一晶片座、圍繞該晶片座配置的多個導腳以及一灌模 澆注口，其中每一導線架單元組内之該些導線架單元的該 些灌模澆注口係集中配置； 於每一晶片座上配置一晶片，並使該晶片電性連接至 該晶片座周圍的該些導腳，以及 進行一封膠製程，以經由該些灌模澆注口同時形成一 14 I2,9〇 氣。c/r 封裝膠體於每一導線架單元上，其中該些封裝膠體至少覆 蓋其所對應的該些晶片。 5. 如申請專利範圍第4項所述之晶片封裝製程，其中 該封膠製程包括： 提供一模具，並使該模具包覆該導線架； 在每一導線架單元組之該些灌模澆注口的上方配置 一封膠材料；以及 經由該些灌模洗注口而將該些封膠材料注入該模具 ί 内，以在每一導線架單元上形成該封裝膠體。 6. 如申請專利範圍第4項所述之晶片封裝製程，其中 使每一晶片電性連接至其所對應之該些導腳的方法包括進 行一打線接合製程，以透過多條導線電性連接該晶片與該 些導腳。129071- X. Patent Application Range: 1. A lead frame comprising a plurality of lead frame unit groups, wherein each lead frame unit group comprises a plurality of lead frame units, and each lead frame unit comprises: a wafer holder, a plurality of a lead pin disposed around the wafer holder; and a filling gate, wherein the filling nozzles of the lead frame units in each lead frame unit are collectively disposed. 2. The lead frame of claim 1, wherein each of the lead frame unit groups comprises two adjacent lead frame units, and the filling mold spouts of the lead frame units are respectively located Adjacent corners of the leadframe units. 3. The lead frame of claim 1, wherein each lead frame unit group comprises four lead frame units arranged in a 2x2 matrix, and the filling nozzles of the lead frame units They are respectively located on adjacent corners of the lead frame units. A chip packaging process comprising: providing a lead frame comprising a plurality of lead frame unit groups, each lead frame unit group comprising a plurality of lead frame units, and each lead frame unit comprising a wafer holder, a plurality of guide pins disposed around the wafer holder and a filling nozzle, wherein the filling nozzles of the lead frame units in each lead frame unit are collectively disposed; and each wafer holder is disposed on the wafer holder The wafer is electrically connected to the leads around the wafer holder, and a glue process is performed to simultaneously form a 14 I2, 9 helium gas through the filling gates. The c/r encapsulant is on each of the leadframe units, wherein the encapsulants cover at least the corresponding wafers. 5. The wafer packaging process of claim 4, wherein the encapsulation process comprises: providing a mold and wrapping the mold over the lead frame; and pouring the mold in each lead frame unit group A glue material is disposed above the mouth; and the sealant material is injected into the mold 355 through the mold filling ports to form the encapsulant on each lead frame unit. 6. The wafer packaging process of claim 4, wherein the method of electrically connecting each of the wafers to the corresponding ones of the leads comprises performing a wire bonding process to electrically connect through the plurality of wires. The wafer and the lead pins. 1515
TW095100052A 2006-01-02 2006-01-02 Leadframe and chip package applying the same TWI290756B (en)

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