TWI290730B - Manufacturing process for integrated circuit - Google Patents

Manufacturing process for integrated circuit Download PDF

Info

Publication number
TWI290730B
TWI290730B TW093126104A TW93126104A TWI290730B TW I290730 B TWI290730 B TW I290730B TW 093126104 A TW093126104 A TW 093126104A TW 93126104 A TW93126104 A TW 93126104A TW I290730 B TWI290730 B TW I290730B
Authority
TW
Taiwan
Prior art keywords
layer
trench
esd
gate
polysilicon layer
Prior art date
Application number
TW093126104A
Other languages
English (en)
Other versions
TW200608450A (en
Inventor
Hsin-Huang Hsieh
Chien-Ping Chang
Mao-Song Tseng
Tien-Min Yuan
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Priority to TW093126104A priority Critical patent/TWI290730B/zh
Priority to US11/035,700 priority patent/US7205196B2/en
Publication of TW200608450A publication Critical patent/TW200608450A/zh
Application granted granted Critical
Publication of TWI290730B publication Critical patent/TWI290730B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

1290730 玖、發明說明： 【本發明所屬之技術領域】 本案係為一種具有靜電保護（ESD)設計之溝渠式金氧 半場效電晶體（TrenchM0SFET)的製作方法及，特別是一 種同時製造渠溝式閘極元件和平面式靜電保護元件的製 作方法。 ^ 【先前技術】 功率70件金氧半場效電晶體（MOSFET、MOS)具有高輸 抗（1咖impedance)，因此特別容易受到靜電放電= (Ρ=)的損害。另夕卜，現今的積體電路製程中為了可 =具有較低起始電壓(vt)的M0S，其 厚度多需變的較薄，在這樣的需求下，^ 造成漏電等情形。因此，在功率元件二; 應 加上一靜電放電（ESD)防護電路是必要的。 卞中，冓7^式金氧半•效電晶體(Treneh M0SFET)技 術令，在靜電保護(_電路的製 ， 件MOS後，才加上_ Ρςη κ七省不 吊疋无衣垅功率兀 傳統渠溝式雙擴散電日μ 路。以Ν刪為例，在 ：Τ：：ΤΖ\Μ：：μ #" r 化物層形成之後，以—層羊曰在乳
Pol…neon)填滿渠溝，接著银刻到表乂二夕下〜(= 的多晶矽層以形成功率元件Μ γ ° 極的製造後，進行第二攻的少a 在凡成M〇S閘 (ESD)電路，即在準溝表六二二石“沈積以形成靜電保護 性植入P型離子（P+)'接Y —層未摻雜的多晶矽並全面 電路所需要的多晶彻Π =把 刻以t成細防護電路所需要的多日日日Μ 凊參考弟-圖’其為—具有咖防護電路之傳統渠溝 1290730 ^ # 11 ί f ® ° ^^ -r：r2；^ 化二層以 護電路17的厂日:/溝式M0s 15的閘極"及ESD保 成。上述的兩;:列層13分別於第一次及第… 渠溝上方的角茨氧;=及敍刻後在酸槽中的清洗，會使 的侵敍，造成'開;nΓ容易受到電漿及氫狀酸(酌 求而要將Lt: 層漏電。此外，為了因應電性需 更加嚴重β ㊈層變薄時，勢必也會讓漏電情況變得 之後是在製造功率元件刪 沈積及姓刻’其使用了兩次多晶石夕層的 太安揾仳接 易造成閘極氧化物層漏電，因此， 本木k供-種可同時製造渠溝 =匕 成本以及提Λΐ法’其可解決漏電的問題、降低生產 【發明内容】 本案係為一種改良式，具靜電 式金氣半場效電晶體〜nch ( 法，用於同時製造渠溝式閉極元）積體/路的製作方 元件，其顯然的進步包括只使用7次"7曰t電保護⑽⑺ 護（ESD)元件的多曰矽岸、^式兀件的閘極和平面式靜電保 層只經過一次電漿蝕刻，所以 夕、，5的間極氧化物 層的產品應用上，可提升耐麼。 -在相極乳化物 本案的内容將敘述於實 渠溝式閘極元件和平面弋於 匕括同時製造 方法及結構。本荦:由面電保護（ESD)元件的 再桊木係由申請專利範圍所定義。 1290730 【實施方式】 餘刻為的了製ΐ效改善既有技術中使用兩次多晶石夕層的沈積及 電問題、Γ安以及此既有製程所易造成的閉極氧化物層漏 述問題。’本木提出一種新穎的積體電路製作方法來解決上 根據本案之一實施例，本案積體電路的製作方法係可 弟一圖（a)至（e)所示的流程作說明。 、 π，考第二圖（a)，磊晶矽epi之半導體材質上具有準 沈積去：導體材質表面上是氧化物層22，氧化物層22上 域25 夕雜之多晶矽層23，此多晶矽層23區分為渠溝區 Φ、;巨壤晶矽層231及平面區域26之多晶矽層233,其 盥二I或25又進一步區分成單元區域251 (CeU area) 2、52甲二泪隹流排區域252 ，間極匯流排區域 夕曰木溝功用在於，其渠溝可將單元區域25丨渠溝中之 ^ ^ # ^ ( gate pad) 4 ° 二二榣切剖面示意圖，因而會隨著不同的橫切位置存有 ⑽：的差#，例如，本案可由另一橫切剖面位i，僅示出 早兀區域251之渠溝。 iiJ作同樣Γ考本案第二圖（a)，首先於多晶矽層23植入P 从1子（P )’並藉由加溫多晶石夕層23的表面，形成氧化 匕〇X。進一步地，在氧化物層〇x之上沈積氮化矽層SiN ShN^)，並在氮化矽層SiN上形成一光阻。此光阻 PR覆蓋至閘極匯流排區域252之渠溝開口近一半處，目的 在於防止多晶石夕敍刻時微渠溝效應（micr〇 trenching effect )的產生。此效應即是在光阻完成顯影之後，對多晶 =層進行私漿蝕刻時，於光阻覆蓋及光阻未覆蓋的界面處 冒有垂直往下及由側壁反彈的電漿，這些電漿會對界面下 方的閘極氧化物層產生不預期的過度蝕刻，進而傷及閘極 氧化物層。 730 發層^在光阻PR形成後，進行氮化 此罩Π’？止於氧化物層⑽，目的在形成-罩幕層Μ 的氧化L 未被㈣的氮化石”_及平面區域26 石夕層233。VI::):::用—保留平面區域26之多晶 之多晶石夕声231\# \被罩幕層厘覆蓋的渠溝區域25 曰23 1的表面係被植入摻質。 子為：以(:例)，，植入摻的方式為離子植入，此摻質
作為說明，本實施方=如^離子。儘管本實施例以NM〇s 的製作。 灵也> 5樣適用於其他功率元件PMOS 將N::二之：，f f阻PR移除，藉由高溫擴散方式 主離于均勻驅入渠溝區域 b 如第二圖⑷所示 層23卜至此’ 有n型之多晶石夕層，換^25Λ夕晶石夕層231已呈現具 型轉成Ν型。 換5之，多晶石夕層231之電性已由Ρ 之多曰‘W同日^件朱溝式M0s之閘極以及ESD防護電路 幕，進行多晶石夕乾式敍刻，j果/笛幕層M作為硬式罩 幕層Μ保留了 ESD防護電路：-曰圖:广『，:罩 由於本製程僅需進行一次之多曰上/曰曰矽層23。此外， 化物層221不會一再地被_曰:：餘刻，因此，角落氧 的厚度。 又、知失，因而容易維持均勻 及EsJ I ’則渠溝式M〇S之閘極21以 阻PR舜；$門κ「夕曰曰夕層23,便分別形成，其中因為光 以罝莫I 排區域252之渠溝開口近-半處，所
以罩幕層Μ亦因此f苗s Mt J 、 卞处尸/T 近-半處，故而形成後 區域之渠溝開口近—半處。如夕第層二亦、覆盘至間極匯流排 戈弟一圖（e)所示，形成的渠溝 1290730 式之間極21 4 N型多晶石夕，而形成的ESD保護電路 之：曰:矽層23則為p型多晶矽，而當然此ESD防護電路 =多晶矽層23’可依所需要的ESD防護電路需求，進一步 ΐρίίΛ型多晶石夕層中的N型區域，例如定義成胸或 乃-仆广的多晶矽層。另外，由於罩幕層Μ是由氮化矽層 及巩化物層組成，因此可分別利用磷酸及氫氟酸將之移除。 根據上述第二圖⑷至⑷的流程示意圖，依順序可實 二撼I法，亚據以獲得一結構。請參考第三圖，其係 = = = = 防護電路之_雙 ，'明本蚀案之積體電路製作方法及結構係以觀〇S為例作 ⑽sH呈本案的方法及結構也同樣適用於PM0S及 體材質^參石考日弟二圖之結構’本案之積體電路結構具有半導 面^ ePi ’該半導體材質具有渠溝區域34及平 “的絕緣層2體覆蓋以絕緣層32。渠溝區域 沒極雙擴散電晶體35 ’其具有源極s、
路37，1 ‘ ESD伴二^域36的絕緣層上為ESD防護電 ^ ^ 11 r ^ f " ^ ^ 3 ^ ^ N P N 溝區域34之絕^ 1具有—均句的厚度，且其位於渠 氧化物芦： 為渠溝式雙擴散電晶體35的問極
二:層，而位於該平面區域36的絕緣層32可作為二 防蠖電路37的介電層。 J作為ESD 其具有根尸據本案方ff得的上述結構’同樣參考第三圖，因 晶體的=，％緣層32、來源相同的渠溝式雙擴散電 3:，31以及ESD保護電路的多晶石夕層33，，吏ί: 茶勺方法具有顯然的進步。 便付本 自多晶_ -次㈣ -件的製程、降低生產成本。也因為絕緣層 1290730 名虫刻’特別是在渠溝 度，當其作為閘極氧化物層的時角， 提升功率元件的良率。有效解決漏電的問題， 同時:口盖述二用本案之積體電路製作方法及結構，可 二:：木溝式閑極元件和平面式靜電保護元件，且菁： 晶石夕層的沈積及截刻的製程，t因為渠 化物声·屏：絶緣層只經過—次蝕刻’戶斤以可以減少閘極氧 ”層漏電的問題，並提升功率元件的良率。0此2 -有突出的技術特徵及顯然的進步： 目的，而具有產業利用價值。 運成《展本木之 制太安本夕案：施例所敘述的方法或結構僅是舉例，而不應限 :ίΐ 想’本案得由熟悉本技藝之人士任施匠思 般修飾’然皆不脫如附申請專利範 【圖式簡單說明】 第一圖：習知具有ESD防護電路之傳統渠溝式雙擴散電晶 體（trench-DMOS)示意圖。 第二圖⑷至⑷：本案積體電路的製作方法之流程示意圖。 第三圖：根據本案方法所得其中之—具有esd㈣電路之 ^溝式雙擴散電晶體（trench_DM〇S)示棄圖。 【元件符號說明】 11 :閘極 12 :氧化物層 121:角落氧化物層 13 ·· ESD保護電路之多晶矽層
Η :渠溝 15 :渠溝式MOS 17:ESD保護電路21:渠溝式MOS之閑極 22 :氧化物層 221 :角落氧化物層 23 ··多晶矽層 23 1 ··渠溝區域之多晶石夕芦 233 ··平面區域之多晶矽層 9 23, ： ESD保護電路之多晶矽層 24 ··渠溝 25 :渠溝區域 1290730 251:單元區域 252:閘極匯流排區域 26 ··平面區域 3 1 :閘極 32 :絕緣層 321 ··角落氧化物層 33’ ： ESD保護電路之多晶矽層 34 :半導體材質之渠溝區域 35 :渠溝式雙擴散電晶體 36 ·•半導體材質之平面區域 37 ·· ESD防護電路 epi :蠢晶石夕 ox :氧化物層
SiN ( Si3N4):氮化矽層 PR:光阻 P+ : P型離子 N+ : N型離子

Claims (1)

1290730 【申請專利範圍】 1 · 一種積體電路之製作方法，其係包括： (勾在一具有渠溝之半導體材質上形成一第一氧化 層； 吻 (b) 形成一多晶矽層於該第一氧化物層之上，其中該夕 晶矽層區分為一渠溝區域之多晶矽層及一平面區== 晶石夕層；以及 夕 (c) 蝕刻部分該多晶矽層，以同時形成一渠溝式元件之 一閘極及一平面式靜電保護（ESD)元件之一多晶矽層， 其中該多晶矽覆蓋至閘極匯流排區域之渠溝開口近二 處。 干 2·如申請專利範圍第i項所述之方法，其中（.刻部分該 多晶矽層之前，更包括： κ 植入一第一掺質於該渠溝區域之多晶矽層；以及 利用一罩幕層覆蓋該平面區域之多晶石夕層。 3.如申哨專利範圍第2項所述之方法，其中⑷蝕刻部分該 夕晶矽層之後，更包括： 移除该罩幕層；以及 定義該平面式靜電保護（ESD)元件之該多晶矽層。 4·如申請專利範圍帛2項所述之方法，其中係利用一離子 植入之方式植入該第一摻質。 女申、明專利範圍第4項所述之方法，其中該離子植入之 方式係藉由高溫擴散來趨入。 申明專利範圍第2或第3項所述之方法，其中該罩幕 層包含一第二氧化物層。 7.如申請專利範圍帛i項所述之方法，其中該第一氧化物 層具有一均勻的厚度。 I如申請專利範圍帛1項所述之方法，其中該多晶矽層旦 有第二摻質。 α 10 1290730 9.如申請專利範圍第1項所述之方法，其中該渠溝式元件 為一渠溝式雙擴散電晶體（DMOS)。 11 1290730
1290730 伍、 中文發明摘要： 本案係為一種具有靜電保護（ESD)設計之溝渠式金氧 半場效電晶體的製作方法，其使用一次多晶石夕層的沈積及 蝕刻即可同時形成渠溝式元件的閘極及平面式具有靜電保 護（ESD)元件的多晶石夕層。本案的方法及結構克服了閘極氧 化物層漏電的問題，並且有效提升耐壓、降低生產成本及 提升良率。本案於溝渠式功率元件的技術領域中具有突出 的技術特徵。 陸、 英文發明摘要： The present invention provides a manufacturing process of a trench-MOSFET having the anti-ESD device. In the present invention, one polysilicon layer deposition and one policilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device having the anti-ESD simultaneously. The present invention not only has overcome the problem of electric leakage, but also has the advantages of withstanding higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of trench-type power device. 柒、指定代表圖·· (一） 本案指定代表圖為：第（三）圖。. (二) 本代表圖之元件代表符號簡單說明： 3 1 :閘極 33, ： ESI 33’ ： ESD保護電路之多晶矽層 34 :半導體材質之渠溝區域 3 5 :渠溝式雙擴散電晶體 36·半導體材質之平面區域 32 :絕緣層 321 :角落氧化物層 37 : ESD防護電路 捌、本案若有化學式時， epi :磊晶矽 請揭示最能顯示發明特徵的化學式··
TW093126104A 2004-08-30 2004-08-30 Manufacturing process for integrated circuit TWI290730B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093126104A TWI290730B (en) 2004-08-30 2004-08-30 Manufacturing process for integrated circuit
US11/035,700 US7205196B2 (en) 2004-08-30 2005-01-14 Manufacturing process and structure of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093126104A TWI290730B (en) 2004-08-30 2004-08-30 Manufacturing process for integrated circuit

Publications (2)

Publication Number Publication Date
TW200608450A TW200608450A (en) 2006-03-01
TWI290730B true TWI290730B (en) 2007-12-01

Family

ID=35943837

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093126104A TWI290730B (en) 2004-08-30 2004-08-30 Manufacturing process for integrated circuit

Country Status (2)

Country Link
US (1) US7205196B2 (zh)
TW (1) TWI290730B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4955222B2 (ja) 2005-05-20 2012-06-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI441335B (zh) * 2009-04-10 2014-06-11 Anpec Electronics Corp 溝渠式半導體元件及其製作方法
CN102263105B (zh) * 2010-05-26 2013-04-03 茂达电子股份有限公司 沟渠式半导体组件及其制作方法
CN102299102B (zh) * 2010-06-22 2013-11-20 茂达电子股份有限公司 具备漏极电压保护的功率半导体组件及其制作方法
CN102412159B (zh) * 2011-10-28 2016-06-08 上海华虹宏力半导体制造有限公司 形成umos晶体管和esd电路的方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
TWI248136B (en) * 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode

Also Published As

Publication number Publication date
US7205196B2 (en) 2007-04-17
TW200608450A (en) 2006-03-01
US20060046389A1 (en) 2006-03-02

Similar Documents

Publication Publication Date Title
US6518623B1 (en) Semiconductor device having a buried-channel MOS structure
TWI246769B (en) Method of forming high voltage devices with retrograde well
TWI231044B (en) Semiconductor device
TW520568B (en) Semiconductor device
TWI320954B (en) Semiconductor component and method of manufacture
TW476136B (en) Method of forming a trench DMOS having reduced threshold voltage
JP3831602B2 (ja) 半導体装置の製造方法
TWI267923B (en) Method for making semiconductor device
TW201232760A (en) Semiconductor device and fabrication method thereof
TW201015719A (en) Lateral DMOS transistor and method for fabricating the same
TW201021212A (en) Lateral double diffused MOS device and method for manufacturing the same
TW200414374A (en) Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers
TWI361472B (en) Semiconductor structure and semiconductor chip
JPH0923010A (ja) 半導体素子及びその製造方法
TW201243961A (en) MOS semiconductor device and methods for its fabrication
JP2004140274A (ja) 半導体装置及びその製造方法
KR20080082998A (ko) 동일 기판 상에 도전 타입이 같은 로우 및 하이 퍼포먼스장치를 갖는 반도체 장치 구조
JP2004508717A5 (zh)
TWI290730B (en) Manufacturing process for integrated circuit
TW200822360A (en) Semiconductor device and manufacturing method thereof
JP2005332993A (ja) 半導体装置および半導体装置の製造方法
JP2012064648A (ja) 半導体装置及びその製造方法
TWI364800B (en) Semiconductor device and method for fabricating the same, bipolar-cmos (complementary metal-oxide-semiconductor transistor)-dmos (double diffused metal-oxide-semiconductor transistor) and method for fabricating the same
TWI240414B (en) A double-gate field effect transistor (DGFET) structure and method of forming such a structure
KR20100020688A (ko) Ｌｄｍｏｓ 반도체 소자와 그 제조 방법