1290588 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種製造半導體裝置的方法，特別有關於以化學氣相 沈積形成氮化鈦膜的方法以及製造DRAM裝置之電容部分的應用。 【先前技術】 動態隨機存取記憶體（DRAM )是一種廣泛應用的積體電路 元件。目前生產線上常見的動態隨機存取記憶單元（Dram cell ) 大多是由一電晶體和一電容器所構成。如熟習此藝者所知，電 谷器疋用來健存電荷以提供電子資訊的，其應具有足夠大的電 谷里’方可避免資料的流失並減低充電更新（refresh)的頻率。 目前日益高度積集化之DRAM元件，必須利用三度空間結構的疊層形電 谷器來實現，並且以金屬—絕緣物—金屬（metai—insulat〇r—或 金屬一絕緣物 ~ 半導體（metal-insulat〇r—semic〇nduct〇r;MIS)材質結構 來組成電容ϋ。其中，為了提高電容II的電容量，理論上可從：⑴增加儲 存電極的表_，⑵提高介電介料數，和⑶減小介電層的厚度幾 個方向著手。在增加儲存電極表面積方面，其原理不外是形成縐褶的 (nigged)表面構造，例如鰭形、樹形等立體的電極構造。而在減小介電層 的厚度方面’現今製造的記憶元件電容器多已使用極薄之介電層，然而當 子又J於50 A時，卻谷易因直接載子隨穿（以代以tunneHng)而產生 過大的漏電w ’影響元件的特性。因此，另有研究致力於尋找具有高介電 韦數的”電材料’以取代_般常用的氧切層，雛找_步提昇電容器 的電容量，其中五氧化二纽加_ Pentoxide; Ta2⑻是頗受重視的介 電層材料之’且已逐漸取代驗或者祕，成為更理想的介電材料。其 1290588 « 原因在於五氧化二鈕具有齡電常數(dielectricc〇nstant)，九約為&孤 的二倍’即22〜25之間，因此能夠大幅增加儲存的電荷量，進而提高元件 性能。 -般使用五氧化二纽為介電材料的堆疊式電容丨的結構如第丨圖所示， 其中2代表M0S電晶體，1〇代表以導電材料如複晶石夕或嫣等所形成之插塞 及下電極板，12為滅電容介電層，14為氮化鈦上電極板，16為内層介 電層。位於減電容介電層12上的TiN上電極板14，通常係藉由化學氣 相沈積(CVD)形成。然而，以一般習知氯化歛TiCh和氨氣舰反應產生氮 化欽TiN做為上電極板的製程，不易形成厚度均句的ΉΝ膜層。也因此， 在晶圓上形成厚度不均自的’臈層，易在電極板厚度偏_區域元件產 生漏電流leakage偏高的情形。 【發明内容】 有鑑於此’本發明之目的為提供一種以化學氣相沈積形成薄膜的方法， 可以改善習知技術沉積之薄膜均勻性不佳之情形。 為達上述目的，本發明提供一種形成氮化鈦膜的方法，包括：首先，將 一基板置於充滿惰性氣體之環境進行預加熱步驟，且此預加熱步驟之壓力 係介於0· ΙΤοιτ至3T〇rr之間。接下來，進行一氮化鈦沉積步驟，使基板 暴露於至少包含氨氣及氯化鈦之反應氣體中，且此沉積步驟之反應壓力至 少為5Torr，溫度至少為500。(：。 此外’本發明之形成氮化鈦膜的方法更可於上述反應壓力至少為5T〇rT 及反應溫度至少為50(TC的氮化鈦沉積步驟之前，先進行另一沉積步驟，於 上述氮化鈦層底下先形成另一氮化鈦層。並且，此另一氮化鈦沉積步驟之 1290588 反應壓力係維持於ITorr以下，且反應溫度小於500°C，並且，可於兩氮化 鈦沉積步驟之後，各進行至少兩次回火步驟，以獲得品質較佳之氮化鈦薄 膜。 根據本發明之形成氮化鈦膜的方法，當用於形成氮化鈦層於電容介電層 上’例如氧化鈕(Ta2〇5)時，所形成之氮化鈦層的電阻低且漏電亦低，是極 佳的作為電容材料Ta2〇5的上電極板(Plate)材料。 為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特 舉一較佳實施例，並配合所附圖示，作詳細說明如下： 【實施方式】 【實施例】 請參閱第3A〜3G圖，其顯示本發明之實施例中，形成氮化鈦膜作為仏晶 電容介電層之上電極板的製程剖面圖。 首先，提供一如第3A圖所示之半導體基板1〇〇，在半導體基板1〇〇上 形成有兩個相鄰的M0S電晶體101，並沉積内層介電層104 (interlayer dielectric)，例如氧化層覆蓋在電晶體1〇1上之，在兩電晶體之間具有一 源極/沒極接觸區1G2 ’且其上具有-插塞⑽與其接觸，插塞⑽係由如 複晶矽或金屬鎢等之導電材料所形成，另外，在内層介電層1〇4中還形成 有一電容預定區106。 接著’沿著電容預定區106順應性沉積以形成如第3B圖所示之一導電 層no作為下電極板，導電層之材料可使用與上述插塞1〇8相同之複晶石夕 或金屬鎢。然後，移除位於電容預定區1〇6 上的導電層ιι〇，而保留位 於電容預定區1G6之側壁及底部的導電層11()。接著，如第％圖所示般， 1290588 沿著電容預定區以及導電層11()順應性沉積以臟—電容介電層112, 可例如以氧化组(Ta2〇5)構成。以氧化组之電容介電層 112來說，上述電容 電層112之形成可在一低壓化學氣相沈積(LpcVD)反應室中進行，此時反 應溫度較佳為45G°C，而先驅物較料Ta(QGH5)5<a及氧氣，雜(earrier) 乳體則較佳使關如氬氣或其他適合的載航體而形成減€容介電層 112。 接下來，則利用本發明之方法，於電容介電層112上形成氮化鈦膜。 本較佳實施例之形成氮化鈦膜的方法的詳細步驟係由如第 2圖所示之流程 圖所不，藉由預加熱步驟S100、第一沈積步驟sl〇1、第一回火步驟31〇2、 第二沈積步驟S104以及第二回火步驟sl〇6而達成。 睛參照第4圖’將形成有下電極板和Ta2〇5電容介電層之晶圓ι〇〇置入 一沉積室404中，進行預加熱步驟sl〇〇。此時，預加熱晶圓1〇〇，預加熱 的μ度較佳控制在小於500。C，更佳的溫度範圍為3〇〇。C〜500。C。於上 述預加熱步驟中通入-惰性氣體，例如氬氣或是氮氣。上述預加熱步驟時， /儿積至404之壓力需維持在一低壓力狀態下，例如〇. 1T〇r至3T〇rr之間， 進行預加熱。 在進行預加熱之後，升高沉積室404的壓力，進行主要沉積步驟。 將上述形成有TaM容介電層之半導體基板暴露於包含TiCh以及腦 之反應氣體巾進行第-沈齡驟漏沈積如第3D圖所示之氮化鈦層馳 於丁祕電容介電層112上。此時反應麼力較佳控制在i T〇m下，， TiCh的比例較佳為大於！，更佳為3〜1〇，且反應溫度可和預加熱步驟的溫 1290588 度相同，較佳為小於500°C，而所形成之氮化鈦層114a的厚度較佳為至少 30A以上，廳流量則較佳為4〇〜60sccm。在此第一沈積步驟中，Tici^ 流量較佳為控制在低流量，以緩慢速度進行氮化鈦的沈積，較佳為控制在 30〜8〇A/min的範圍，藉此控制形成於Ta2〇5的氣濃度在最低的程度，進而減 低氮化鈦薄膜的電阻。此外，使用低TiCh流量亦能避免形成Ti〇2，因而減 少由Ti〇2造成漏電來源的可能。 然後，在一充滿NIL·氣體的反應槽中對氮化鈦層114a進行如第3E圖所 示之第一回火(anneal)步驟S102而形成氮化鈦層114b，此時壓力較佳控制 鲁 在1〜3 Torr之間，且跳的流量較佳為lOOOsccm以上。此第一回火步驟 係於高溫且充滿NH3的環境中進行，因此存在於氮化鈦膜的ci將被nh3中的 N原子所置換，因而使氮化鈦膜更為緻密化。 接下來，將基板置於TiCh以及腦所組成之反應氣體中進行第二次沈 積步驟S104，此時壓力較佳控制在大於5 Torr的範圍，壓力上限較佳為 lOTorr，且NIL·/ TiCL的比例較佳為大於1(更佳為大於，此時基板溫度 較佳控制在500〜600°C。當控制壓力大於5Τοιτ時，氣體量增多，會帶走 _ 部分熱量，因此基板下的加熱器將偵測到此一變化，而加熱基板，使其溫 度維持在500〜600°C之間。在此第二沈積步驟中，可使用較高的TiCh流量 以較快的沈積速度進行，較佳的TiCL·流量為至少25 sccm，而沈積速度較 佳為100〜500A/min。藉由此方式，將可減少所形成之氮化鈇膜的電阻。 第二次沈積步驟形成之氮化鈦層，如第3F圖所示之114c，其厚度較佳為至 少 60 A 〇 9 1290588 接著，再次於NH3氣體中進行第二回火步驟S106之氮化(nitridation) 步驟，此時壓力較佳為大於5 Torr，且小於1〇 Torr。透過高溫處理再度 使氮化鈦層更為緻密，並能釋放存在於氮化鈦與TiCl4的應力，形成品質優 異的如第3G圖所示之氮化鈦層li4d。 請參閱第4圖，相較於習知技術之沉積氮化鈦膜時之於預加熱階段採用 高壓力（至少5Τοιτ)，本實施例採用較低之預熱壓力，可以減少因為通入惰 性氣體408之溫度和晶圓1〇〇表面溫度的差異，將晶圓1〇〇表面熱量帶走， 造成晶® 100表面溫度不均勻的現象。_，因為晶1〇〇表面溫度留失 較少，晶圓100底下之加熱器406亦可減少增加能量加熱晶圓1〇〇的頻率。 也因此在預熱過程中加熱器偏能量的波動相對較小。此時，在晶圓副 表面提供-較穩定的狀態，也因此在後續的主要沉積步科，可以得到厚 度及致密性㈣勻_膜。也因此，以本發财法所可_柄勻性較佳 的鼠化鈦賴。再者’以上述㈣之氮化鈦膜做為電極之電容朗電極板 有均勻之厚度，因此漏電流亦相對較低。 雖然本發邮啸佳_麵如上，财並_嫌林發明，任何 熟習此技藝者，林麟本發明之輯和範_，當可作麵之更動翔 佛’例如適用於本發明之半導體基板並不限於使用具有上述結構之半導體 基板，軸有麵元叙半導板 範圍當視後附之申請專利範固所界定者為準。因此本發明之保護 【圖式簡單說明】 第1圖係顯示一習知之堆疊式電容的剖面圖。 1290588 第2圖係顯示根據本發明之實施例形成氮化鈦膜之方法的流程圖。 第3A〜3G圖係顯示本發明實施例的形成氮化鈦膜的方法的製程剖面 圖。 第4圖係顯示本發明實施例形成氮化鈦膜的裝置示意圖。 【主要元件符號說明】 1〜堆疊式電容； 2〜MOS電晶體； 10〜下電極板； 12〜Ta2〇5電容介電層； 14〜上電極板； 16〜内層介電層； 1〇〇〜半導體基板； 101〜MOS電晶體； 102〜源極/汲極接觸區； 104〜内層介電層； 106〜電容預定區； 108〜插塞； 110〜導電層； 112〜Ta205電容介電層； 114a、114b、114c、114d” “氮化鈦層； 404〜沉積室； 408〜純性氣體。 406〜加熱器； 11BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of forming a titanium nitride film by chemical vapor deposition and an application of a capacitor portion for fabricating a DRAM device. [Prior Art] Dynamic Random Access Memory (DRAM) is a widely used integrated circuit component. Most of the current dynamic random access memory cells (Dram cells) on the production line are composed of a transistor and a capacitor. As is known to those skilled in the art, the battery is used to store charge to provide electronic information, which should be large enough to avoid data loss and reduce the frequency of charge refresh. At present, the increasingly accumulative DRAM components must be realized by a three-dimensional structure of a laminated electric grid, and metal-insulator-metal (metai-insulat〇r- or metal-insulator-semiconductor (metal) -insulat〇r-semic〇nduct〇r; MIS) material structure to form the capacitor ϋ. Among them, in order to increase the capacitance of the capacitor II, theoretically from: (1) increase the storage electrode table _, (2) increase the number of dielectric materials And (3) reducing the thickness of the dielectric layer in several directions. In terms of increasing the surface area of the storage electrode, the principle is not only to form a nigged surface structure, such as a three-dimensional electrode structure such as a fin shape or a tree shape. In terms of reducing the thickness of the dielectric layer, most of the memory device capacitors manufactured today have used a very thin dielectric layer. However, when the sub-J is at 50 A, the valley is easily worn by the direct carrier (instead of tunneHng). ) and excessive leakage w 'affects the characteristics of the component. Therefore, another study is devoted to finding "electrical materials" with high dielectric flux to replace the commonly used oxygen-cut layer, and find the power of the _ step-up capacitor. Capacity, where Oxidized Ninja _ Pentoxide; Ta2 (8) is a highly regarded dielectric layer material 'and has gradually replaced the or the secret, becoming a more ideal dielectric material. Its 1290588 « The reason is that the five-oxide two button has an age constant (dielectricc 〇nstant), nine is about & twice the 'lone' is between 22 and 25, so it can greatly increase the amount of stored charge, thereby improving the performance of the component. - Stacked capacitors using pentoxide oxide as dielectric material The structure of the crucible is as shown in the figure, wherein 2 represents a MOS transistor, 1 〇 represents a plug and a lower electrode plate formed of a conductive material such as a polycrystalline stone or a crucible, and 12 is a capacitor dielectric layer, 14 For the titanium nitride upper electrode plate, 16 is an inner dielectric layer. The TiN upper electrode plate 14 on the reduced capacitance dielectric layer 12 is usually formed by chemical vapor deposition (CVD). However, conventional chlorine is used. The reaction between TiCh and ammonia gas is used to produce NiN as the upper electrode plate, and it is difficult to form a ruthenium layer with a uniform thickness. Therefore, a layer of thickness unevenness is formed on the wafer, which is easy to Electrode plate thickness is biased _ area component generates leakage current leakage In view of the above, it is an object of the present invention to provide a method for forming a film by chemical vapor deposition, which can improve the uniformity of film uniformity deposited by the prior art. To achieve the above object, the present invention A method for forming a titanium nitride film includes: first, placing a substrate in an environment filled with an inert gas for a preheating step, and the pressure of the preheating step is between 0·ΙΤοιτ and 3T〇rr. Next, a titanium nitride deposition step is performed to expose the substrate to a reaction gas containing at least ammonia gas and titanium chloride, and the deposition step has a reaction pressure of at least 5 Torr and a temperature of at least 500. (: In addition, the method for forming a titanium nitride film of the present invention can further perform another deposition step before the above reaction pressure is at least 5T〇rT and the reaction temperature is at least 50 (the titanium nitride deposition step of TC) Another titanium nitride layer is formed under the titanium nitride layer, and the 1290588 reaction pressure of the other titanium nitride deposition step is maintained below ITorr, and the reaction temperature is less than 500 ° C, and can be nitrided. After the titanium deposition step, each of the tempering steps is performed at least twice to obtain a titanium nitride film of better quality. The method of forming a titanium nitride film according to the present invention, when used to form a titanium nitride layer on a capacitor dielectric layer For example, when the oxidation button (Ta2〇5) is used, the formed titanium nitride layer has low electrical resistance and low leakage, and is excellent as an upper electrode plate material of the capacitance material Ta2〇5. The other objects, features, and advantages will be more apparent and understood. The following detailed description of the preferred embodiments, together with the accompanying drawings, will be described in detail as follows: [Embodiment] [Examples] Please refer to Figures 3A to 3G Which shows the invention In the embodiment, a titanium nitride film is formed as a process profile of the upper electrode plate of the germanium capacitor dielectric layer. First, a semiconductor substrate 1A as shown in FIG. 3A is provided, which is formed on the semiconductor substrate 1 There are two adjacent MOS transistors 101, and an inner dielectric layer 104 is deposited, for example, an oxide layer covering the transistor 〇1, and a source/no-pole contact between the two transistors. The region 1G2' has a plug-in (10) in contact therewith, and the plug (10) is formed of a conductive material such as a polysilicon or a metal tungsten. Further, a predetermined region of the capacitor is formed in the inner dielectric layer 1? 106. Then 'conforming along the capacitor predetermined region 106 to form a conductive layer no as shown in FIG. 3B as the lower electrode plate, and the material of the conductive layer can use the same as the above-mentioned plug 1〇8 Or metal tungsten. Then, the conductive layer ιι located on the predetermined region 1 〇 6 of the capacitor is removed, while the conductive layer 11 () on the sidewall and the bottom of the predetermined region 1G6 of the capacitor is retained. Then, as shown in the % diagram, 1290588 accommodating along the predetermined area of the capacitor and the conductive layer 11 () The deposition of the dirty-capacitor dielectric layer 112 can be performed, for example, by an oxidation group (Ta2〇5). In the case of the oxide dielectric layer 112 of the oxidation group, the formation of the capacitor dielectric layer 112 can be performed in a low pressure chemical vapor deposition ( LpcVD) is carried out in the reaction chamber, at which time the reaction temperature is preferably 45 G ° C, and the precursor is better than Ta (QGH5) 5 < a and oxygen, and the (earrier) emulsion is preferably closed such as argon or other suitable The carrier body is formed to form a dielectric layer 112. Next, a titanium nitride film is formed on the capacitor dielectric layer 112 by the method of the present invention. The method for forming a titanium nitride film according to the preferred embodiment The detailed steps are as shown in the flow chart shown in FIG. 2, by the preheating step S100, the first deposition step sl1, the first tempering step 31〇2, the second deposition step S104, and the second The fire step sl6 is reached. The wafer ι which is formed with the lower electrode plate and the Ta 2 〇 5 capacitor dielectric layer is placed in a deposition chamber 404 with reference to Fig. 4, and a preheating step s1 is performed. At this time, the wafer is preheated 1 Torr, and the degree of preheating is preferably controlled to be less than 500. C, a better temperature range of 3 〇〇. C~500. C. In the above preheating step, an inert gas such as argon or nitrogen is introduced. In the above preheating step, the pressure of the product to 404 is maintained at a low pressure, for example, between 1T〇r and 3T〇rr, and preheating is performed. After the preheating is performed, the pressure of the deposition chamber 404 is raised to perform the main deposition step. Exposing the above-mentioned semiconductor substrate on which the TaM dielectric layer is formed to a reaction gas towel containing TiCh and brain for the first-thirty-thickness leakage deposition, and the titanium nitride layer shown in FIG. 3D is on the dielectric layer 112. on. At this time, the reaction force is preferably controlled under i T〇m, and the ratio of TiCh is preferably greater than! More preferably, it is 3 to 1 Torr, and the reaction temperature may be the same as the temperature of the preheating step of 1290588 degrees, preferably less than 500 ° C, and the thickness of the formed titanium nitride layer 114a is preferably at least 30 A or more. The flow rate is preferably 4 〇 to 60 sccm. In this first deposition step, the Tici gas flow rate is preferably controlled at a low flow rate, and the deposition of titanium nitride is performed at a slow speed, preferably in the range of 30 to 8 A/min, whereby the control is formed in Ta2. The gas concentration of 〇5 is at a minimum, thereby reducing the electrical resistance of the titanium nitride film. In addition, the use of low TiCh flow also avoids the formation of Ti〇2, thus reducing the potential for leakage sources caused by Ti〇2. Then, the titanium nitride layer 114a is subjected to a first anneal step S102 as shown in FIG. 3E in a reaction tank filled with NIL gas to form a titanium nitride layer 114b, and the pressure is preferably controlled. It is between 1 and 3 Torr, and the flow rate of the jump is preferably more than 100 sccm. This first tempering step is carried out in an environment of high temperature and full of NH3, so that ci existing in the titanium nitride film is replaced by N atoms in nh3, thereby making the titanium nitride film more dense. Next, the substrate is placed in a reaction gas composed of TiCh and brain for a second deposition step S104, wherein the pressure is preferably controlled in a range of more than 5 Torr, the upper pressure limit is preferably 10 Torr, and the NIL·/TiCL is The ratio is preferably greater than 1 (more preferably greater than, at which time the substrate temperature is preferably controlled at 500 to 600 ° C. When the control pressure is greater than 5 Τοιτ, the amount of gas is increased, and part of the heat is taken away, so the heater under the substrate This change will be detected and the substrate heated to maintain a temperature between 500 and 600 ° C. In this second deposition step, a higher TiCh flow rate can be used at a faster deposition rate, preferably. The TiCL·flow rate is at least 25 sccm, and the deposition rate is preferably 100 to 500 A/min. In this way, the resistance of the formed tantalum nitride film can be reduced. The titanium nitride layer formed by the second deposition step 114c, as shown in FIG. 3F, preferably has a thickness of at least 60 A 〇9 1290588. Next, the nitridation step of the second tempering step S106 is performed again in the NH 3 gas, and the pressure is preferably greater than 5 Torr and less than 1 Torr. The temperature treatment again makes the titanium nitride layer denser, and can release the stress existing in titanium nitride and TiCl4 to form a titanium nitride layer li4d having excellent quality as shown in Fig. 3G. Please refer to Fig. 4, compare In the conventional deposition of a titanium nitride film, a high pressure (at least 5 Τοιτ) is used in the preheating stage. In this embodiment, a lower preheating pressure is used, and the temperature of the inert gas 408 and the wafer can be reduced. The difference in surface temperature of the crucible takes away the surface heat of the wafer, causing the surface temperature of the crystal 100 to be uneven. _, because the surface temperature of the crystal 1 is less lost, the heater 406 under the wafer 100 It can also reduce the frequency at which the energy is heated to heat the wafer. Therefore, the fluctuation of the heater's partial energy during the preheating process is relatively small. At this time, a relatively stable state is provided on the wafer subsurface, and thus The main sedimentation step can obtain thickness and compactness (4) uniform film. Therefore, it is possible to use the method of the present invention to provide a nitrile-titanium film with better uniformity. As a capacitor, the electrode has a uniform thickness. Therefore, the leakage current is relatively low. Although this is the same as the above, the financial and _ suspected Lin invented, anyone who is familiar with this skill, Lin Lin's invention and the model _, when the face can be changed to the Buddha' For example, the semiconductor substrate to which the present invention is applied is not limited to the use of the semiconductor substrate having the above structure, and the range of the surface of the semiconductor has been defined in the appended patent application. Therefore, the protection of the present invention BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional stacked capacitor. 1290588 Fig. 2 is a flow chart showing a method of forming a titanium nitride film according to an embodiment of the present invention. Figs. 3A to 3G are drawings showing A process cross-sectional view of a method of forming a titanium nitride film according to an embodiment of the invention. Fig. 4 is a view showing a device for forming a titanium nitride film according to an embodiment of the present invention. [Main component symbol description] 1~Stacked capacitor; 2~MOS transistor; 10~lower electrode plate; 12~Ta2〇5 capacitor dielectric layer; 14~upper electrode plate; 16~inner dielectric layer; ~ semiconductor substrate; 101 ~ MOS transistor; 102 ~ source / drain contact area; 104 ~ inner dielectric layer; 106 ~ capacitor predetermined area; 108 ~ plug; 110 ~ conductive layer; 112 ~ Ta205 capacitor dielectric layer 114a, 114b, 114c, 114d" "titanium nitride layer; 404 ~ deposition chamber; 408 ~ pure gas. 406~heater; 11