1287833 A7 五、發明說明（ 發明領域= 經濟部智慧財產局員工消費合作社印製 本發明係有關於複晶矽閘極之結構及其製造方法，特 別是有關於利用高介電係數材料作為閘極氧化層的複晶矽 閘極之結構及其製造方法。 發明背景： 所謂的積體電路，就是把特定電路的各種電子元件及 線路’縮小製作在面積小於2cm2的一種電子產品。因為積 體電路大多是由數以萬計，大小需由顯微鏡才能觀看到的 固態電子元件所組合而成，因為又稱為「微電子元件」。 基本上，常利用線路所能設計與製造的最小線寬、積體電 路所使用的晶片直徑、與動態隨機儲存記憶（Dram)所能儲 存的容量，來評斷積體電路製程的發展情形。現今積體電 路的技術發展趨勢係朝向較大的晶片、與較小的線寬來進 化。 一般係可利用濕式蝕刻製程與乾式蝕刻製程來製造積 體電路元件之複晶矽閘極層。第1 a圖至第1 c圖所繪示為 習知利用濕蝕刻製程來製造複晶矽閘極之製造流程圖。請 參照第1 a圖，先利用例如化學氣相沈積以形成閘極氧化層 1 2在基材1 0上，接著，形成複晶矽材料於閘極氧化層1 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------—--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 12878331287833 A7 V. INSTRUCTIONS INSTRUCTIONS (Invention Fields = Ministry of Economic Affairs, Intellectual Property Bureau, Staff Consumer Cooperatives, Printing The present invention relates to the structure of a polycrystalline silicon gate and its manufacturing method, in particular to the use of a high dielectric constant material as a gate BACKGROUND OF THE INVENTION The so-called integrated circuit is to reduce the various electronic components and circuits of a specific circuit into an electronic product having an area of less than 2 cm 2 . Most of them are composed of tens of thousands of solid-state electronic components that need to be viewed by a microscope, because they are also called "microelectronic components." Basically, the minimum line width that can be designed and manufactured by the line is often used. The diameter of the wafer used in the integrated circuit and the capacity that can be stored by the dynamic random access memory (Dram) to judge the development of the integrated circuit process. The current trend of the integrated circuit technology is toward larger wafers and A small line width is evolved. Generally, a wet etching process and a dry etching process can be used to fabricate a compound crystal of a composite circuit component. Gate layer. Figures 1a to 1c are diagrams showing a manufacturing flow chart for manufacturing a germanium gate using a wet etching process. Referring to Figure 1a, first, for example, chemical vapor deposition is used. Forming a gate oxide layer 12 on the substrate 10, and then forming a polysilicon material on the gate oxide layer 1 2 This paper scale applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- ---------------Book--------- (Please read the notes on the back and fill in this page) 1287833
五、發明說明（） 經濟部智慧財產局員工消費合作社印製 再進仃疋義步驟，定義出複晶矽閘極層1 4的位置。其 :般多利用將矽晶片暴露在高溫且含氧的環境裡一段 1即可在矽晶片的表面長成一層與矽附著性良好， 且電性符合要求的絕緣體·二氧化矽(si〇2)，以做為上述之 閘極氧化g 1 2。接著，請參照第i b圖，進行濕#刻步驟， 藉以去除未被複晶石夕問極層14戶斤覆蓋的部分問極氧化層 12’而形成閘極氧化居 化層12a。其中，可利用例如氫氟酸 (Υ 〇nC Acid)溶液、或與氟化氨（Ammonium Fluoride) 的混口 /合液來進行以二氧化矽做為閘極氧化層的蝕刻。接 著，請再參照第卜圖，在間極氧化層⑴與複晶石夕問極層 14的兩側形成間隙壁16，即完成一般複晶矽閘極的結構。 、而第2a圖至第2e圖所緣示為習知利用乾姓刻製程來 製造複晶發閘極之制；生、、衣&面 怎製k机程圖。請參照第2a圖，先利用 如化學氣相沈積以形成閉極氧化層22在基材2〇上，接著， 形成複晶碎材料於^ a a 、 竹付於閘極氧化層22上，再進行定義步驟，定 義出複晶硬閘極層. 層24的位置。接著，請參照第2b圖，在 複晶矽閘極層24的兩側形成間隙壁26。接著，請再參照 第2c圖’進仃乾姓刻步驟’藉以去除未被複晶石夕問極層24 所覆蓋的部分閘極氣# 〇 1 乳化層22 ’而形成閘極氧化層22a，如 此即完成一般複晶梦閉極的結構。其巾，可利用含有如氟 化碳的電漿來執行二氧化矽的乾蝕刻製程。 本紙張尺錢帛 + _ CCNS)A4 (210 χ 29?Hn -I i_l ϋ mmi (請先閱讀背面之注意事項再填寫本頁) A7 1287833 五、發明說明（ 由於現今積體電路开杜抽/ ^ ^ ^ 俗疋件越小，積體電路結構中複晶矽 閘極下的閘極氧化層也必須越薄。因此，在閘極氧化層薄 到只剩幾層原子的厚度時，會有穿随效應的情況發生，造 成閉極氧化層的品質不良。如此一來，係增加了積體電路 製造的難度。 發明目的及概述： 鑒於上述之發明背景中，由於現在積體電路元件尺寸 的縮小，習知利用熱氧化層作為複晶石夕閘極結構之問極 化層：遭遇到製程瓶頸，本發明的目的之一係為提供一種 利用高介電係數材料作為閘極氧化層的複晶石夕問極結構， 如此可提高閘極氧化層的品質，有助於朝縮小積體^路尺 寸的方向發展’並兼顧產品的良率與品質。 再者，由於習知利用；愚餘刻製程並不易選擇 1 他複晶矽閘極材料而僅去除高介電係數材料的適當^ = 液，而且利用乾蝕刻製程來去除高介電係數材料時Y = 成暴露複晶石夕閘極層的兩側，而在後續形成金屬石 ^ 時，造成複晶矽閘極易短路的缺點。因此， 夕化物 馬解決上述之 製程瓶頸’本發明的另—目的係為提供__種複晶 製造方法’可用來製造上述利用高介電係數 虽之 氧化層之本發明複晶矽閘極之結構。 為問極 ‘紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f I —--------訂---- (請先閱讀背面之注意事項再填寫本頁) s'. 經濟部智慧財產局員工消費合作社印製 1287833 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明< ) 根據以上所述之目的，本發明複晶矽閘極之製造方 法包括·、提供一基材；形成一閘極氧化層於基材上，其 中間極氧化層係由—高介電係數材料所構成；形成-複晶 矽閘極層於閘極氧化層i ;形成一間隙壁於複晶矽閘極層 之兩側；進行一蝕刻步驟，去除一部分之複晶矽閘極層， 藉以使得複晶矽閘極層之另一部份之表面低於間隙壁；以 及進行疋義步驟’係利用複晶碎閘極層之另一部份與 間隙壁做為罩幕，去除未被複晶矽閘極層之另一部份與間 隙壁所覆蓋之閘極氧化層之一部分，以暴露出基材之一部 分。 本發明複晶石夕閘極之製造方法，其中上述之高介電係 數材料係為一氧化物，例如可選自於二氧化鍅（Zr02)、三 氧化二鋁（Al2〇3)、三氧化二釔（Y2〇3)、二氧化铪（Hf〇2)、 二氧化鑭（LaO_2)、錯；5夕氧化物（ZrSixOy)、錯鋁氧化物 (ZrAlx〇y)、姶矽氧化物（Hfsix〇y)、铪鋁氧化物（HfAlx〇y)等 具高介電係數之材質。而上述之蝕刻步驟中，去除複晶石夕 閘極層部分之厚度約介於1〇〇A至500A之間，並可利用氮 之濺擊（Ar Sputter)蝕刻製程來進行上述之定義步驟。另 外，本發明複晶矽閘極之製造方法，更包括在上述之定義 步驟之後，形成一金屬碎化物（Silicide)於基材之部分與複 晶石夕閘極層之另一部份。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------I-----------訂---------線^^ (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（） 在本發明複晶矽閘極之製造方法的較佳實施例中，形 成複晶矽閘極層之步驟係包括先形成複晶矽材料於基材 上’再進行一定義步驟，利用一光阻做為罩幕，籍以去除 部分之複晶矽材料，以暴露出部分之閘極氧化層，之後再 去除光阻進而形成複晶矽閘極層。另外，更可在上述之複 晶矽閘極層上形成一抗反射塗佈（Anti-Refection c〇ating) 層，以利於微影製程的進行。 利用上述本發明複晶梦閘極層之製造方法，所製造的 本發明複晶矽閘極之結構，包括：一基材；一閘極氧化層 位於基材上’並暴露出基材之一部份，其中閘極氧化層係 由上述之高介電係數材料所構成；一複晶矽閘極層位於閘 極氧化層上，其中複晶矽閘極層之寬度係小於閘拯氧化層 之寬度’而暴露出閘極氧化層之一部份；以及，一間隙壁 位於複晶石夕閘極層之兩側，其中間隙壁係位於閘極氧化層 暴露之部分上。另外，本發明複晶矽閘極之結構，更包括 一金屬石夕化物位於複晶矽閘極層之表面與基材之表面。 利用本發明複晶矽閘極之結構及其製造方法，由於利 用高介電係數材料的沈積可製造品質良好的氧化層，並改 善後續金屬矽化物形成易短路的情況。因此，可縮小積體 電路元件之尺寸與線寬方面。 6 經濟部智慧財產局員工消費合作社印製 1287833 Α7 Β7 五、發明說明（) 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1 a圖至第1 C圖所繪示為習知利用濕蝕刻製程來製 造複晶矽閘極之製造流程圖； 第2a圖至第2c圖所繪示為習知利用乾蝕刻製程來製 造複晶矽閘極之製造流程圖；以及 第3圖至第1 0圖所繪示為利用本發明複晶矽閘極之製 造方法之流程圖。 圖號對照說明： 10 基材 12 閘極氧化層 12a 閘極氧化層 14 複晶$夕閘極層 16 間隙壁 20 基材 22 閘極氧化層 22a 閘極氧化層 24 複晶矽閘極層 26 間隙壁 26a 間隙壁 100 基材 102 閘極氧化層 102a 閘極氧化層 104 複晶矽閘極層 104a 複晶矽閘極層 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1287833 A7 B7 五、發明說明（） 104b 複晶矽閘極層 106 抗反射塗佈層 106a 抗反射塗佈層 108 光阻 108a 光阻 110 間隙壁 110a 間隙壁 112 金屬矽化物 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 鏗於習知利用熱氧化製程所製造的二氧化矽之閘極氧 化層’在其厚度減薄的情況下，並不易獲得良好的氧化層 品質。因此，本發明提供一種利用高介電係數材料作為閘 極氧化層的複晶矽閘極結構。一般閘極氧化層所利用二氧 化石厌’其介電係數大約在4左右，因此，在較薄的厚度下 要具有較高的電容，就必須提高材料的介電係數。 另外，請參照第2b圖與第2c圖，由於利用習知乾蝕 刻製程來去除做為閘極氧化層2 2之高介電係數材料時，會 造成暴露複晶矽閘極層24的兩側，而形成閘極氧化層 22a。因此，在後續在基材20表面與複晶矽閘極層24形成 金屬石夕化物時’造成複晶石夕閘極層24易短路的缺點。另 外，習知濕蝕刻製程來去除做為閘極氧化層之高介電係數 材料時’通常可去除高介電係數材料的蝕刻液也會傷害到 其他複晶矽閘極結構，例如淺溝渠隔離，因此在蝕刻液的 選擇上並不方便。因此’本發明更提供一種複晶矽閘極的 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---------訂---------· 1287833V. Description of the invention () Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumers' Cooperatives, and the steps to define the gate layer of the polycrystalline silicon gate. It is generally used to expose the tantalum wafer to a high temperature and oxygen-containing environment for a period of 1 to form a layer on the surface of the tantalum wafer with good adhesion to the crucible, and the electrical conductivity meets the requirements of the insulator · cerium oxide (si〇2 ), as the above-mentioned gate oxidation g 1 2 . Next, referring to the figure i b, a wet etching step is performed to remove the portion of the gate oxide layer 12' which is not covered by the polycrystalline stone layer 14 to form the gate oxide oxide layer 12a. Among them, etching using cerium oxide as a gate oxide layer can be performed by, for example, a hydrofluoric acid (Υ 〇 nC Acid) solution or a mixed/combined liquid with ammonium fluoride (Ammonium Fluoride). Next, referring to the second drawing, a spacer 16 is formed on both sides of the inter-electrode oxide layer (1) and the polycrystalline quartz layer 14 to complete the structure of the general polysilicon gate. And the 2A to 2e diagrams show the conventional system of making the complex crystal gate by using the dry name engraving process; the raw, clothing & surface method is made. Referring to FIG. 2a, first, for example, chemical vapor deposition is used to form the gate oxide layer 22 on the substrate 2, and then the polycrystalline material is formed on the gate oxide layer 22, and then applied to the gate oxide layer 22, and then The definition step defines the location of the polycrystalline hard gate layer. Next, referring to Fig. 2b, spacers 26 are formed on both sides of the polysilicon gate layer 24. Next, please refer to the 2c figure 'into the dry step of engraving step' to form the gate oxide layer 22a by removing part of the gate gas #〇1 emulsion layer 22' which is not covered by the polycrystalline stone layer 24 This completes the structure of the general polycrystalline dream closed pole. The towel can be subjected to a dry etching process using cerium oxide using a plasma containing, for example, carbon fluoride. This paper size 帛 帛 + _ CCNS) A4 (210 χ 29? Hn - I i_l ϋ mmi (please read the back note first and then fill out this page) A7 1287833 V. Invention description (Because the current integrated circuit is open pumping / ^ ^ ^ The smaller the vulgar component, the thinner the gate oxide layer under the gate of the polysilicon gate in the integrated circuit structure. Therefore, when the gate oxide layer is as thin as a few layers of atoms, there will be The wear-through effect occurs, resulting in poor quality of the closed-pole oxide layer. As a result, the difficulty in manufacturing the integrated circuit is increased. SUMMARY OF THE INVENTION AND SUMMARY: In view of the above-mentioned background of the invention, due to the size of the integrated circuit component Reduction, it is conventional to use the thermal oxide layer as the polarization layer of the polycrystalline quartz gate structure: encountering the process bottleneck, one of the objects of the present invention is to provide a compound using a high dielectric constant material as a gate oxide layer. The spar is called the pole structure, which can improve the quality of the gate oxide layer and help to reduce the size of the integrated body and the quality and quality of the product. Moreover, due to the use of the knowledge; Engraving process is not easy to choose 1 He polysilicones the gate material and removes only the appropriate ^ = liquid of the high dielectric constant material, and uses the dry etching process to remove the high dielectric constant material when Y = becomes the side of the exposed polytecedic gate layer. However, in the subsequent formation of the metal stone ^, the polycrystalline silicon gate is extremely short-circuited. Therefore, the invention is to solve the above-mentioned process bottleneck. The other object of the present invention is to provide a method for manufacturing a polycrystalline crystal. The structure of the above-mentioned polycrystalline germanium gate of the present invention using the high dielectric constant oxide layer is manufactured. The Chinese National Standard (CNS) A4 specification (210 X 297 public f I.----- ---Order---- (Please read the note on the back and fill out this page) s'. Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed 1278833 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 5, invention DESCRIPTION OF THE INVENTION According to the above, the method for manufacturing a polysilicon gate of the present invention comprises: providing a substrate; forming a gate oxide layer on the substrate, wherein the interlayer oxide layer is Electrical coefficient material; forming-polycrystalline gate The pole layer is formed on the gate oxide layer i; a spacer is formed on both sides of the gate layer of the polysilicon gate; an etching step is performed to remove a portion of the gate layer of the polysilicon gate, thereby making the gate layer of the polysilicon gate The surface of the portion is lower than the spacer; and the step of performing the derogation step is to use another portion of the polycrystalline gate layer and the spacer as a mask to remove the other portion of the gate layer that is not the polysilicon gate And a portion of the gate oxide layer covered by the spacer to expose a portion of the substrate. The method for manufacturing a polycrystalline silicon gate of the present invention, wherein the high dielectric constant material is an oxide, for example, From cerium oxide (Zr02), aluminum oxide (Al2〇3), antimony trioxide (Y2〇3), cerium oxide (Hf〇2), cerium oxide (LaO 2 ), erbium; Material with high dielectric constant such as ZrSixOy, ZrAlx〇y, Hfsix〇y, HfAlx〇y. In the etching step described above, the thickness of the portion of the gate oxide layer removed is about 1 〇〇A to 500 Å, and the above-defined step can be performed by an Ar Sputter etching process. In addition, the method for fabricating the gate of the polysilicon gate of the present invention further comprises forming a portion of the metal compound on the substrate and another portion of the layer of the polycrystalline silicon gate after the above defined steps. 5 The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------I----------------- Line ^^ (Please read the precautions on the back and then fill out this page.) 5. Inventive Note () In the preferred embodiment of the method for fabricating the gate of the polysilicon gate of the present invention, the step of forming a gate of the polysilicon gate Including forming a polysilicon material on the substrate first, and then performing a definition step, using a photoresist as a mask to remove part of the polysilicon material to expose a portion of the gate oxide layer, and then removing The photoresist further forms a polysilicon gate layer. In addition, an anti-refection coating layer may be formed on the above-mentioned polysilicon gate layer to facilitate the lithography process. The structure of the polysilicon gate of the present invention produced by the above method for manufacturing a polycrystalline monk gate layer of the present invention comprises: a substrate; a gate oxide layer on the substrate and exposing one of the substrates In part, wherein the gate oxide layer is composed of the above high dielectric constant material; a polysilicon gate layer is located on the gate oxide layer, wherein the width of the polysilicon gate layer is smaller than that of the gate oxide layer Width ' exposes a portion of the gate oxide layer; and a spacer wall is located on either side of the polycrystalline cristobalite gate layer, wherein the spacer is located on the exposed portion of the gate oxide layer. In addition, the structure of the polysilicon gate of the present invention further comprises a metal lithium compound on the surface of the gate layer of the polysilicon layer and the surface of the substrate. With the structure and manufacturing method of the polysilicon gate of the present invention, a good quality oxide layer can be produced by deposition of a high dielectric constant material, and the subsequent metal halide formation can be improved to be easily short-circuited. Therefore, the size and line width of the integrated circuit component can be reduced. 6 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1287833 Α7 Β7 V. Inventive Note () Brief Description of the Drawings: The preferred embodiment of the present invention will be explained in more detail in the following explanations with the following figures. Wherein: FIG. 1 a to FIG. 1 C are diagrams showing a manufacturing flow chart for manufacturing a polysilicon gate using a wet etching process; FIGS. 2 a to 2 c are diagrams showing a conventional dry etching process A manufacturing flow chart for fabricating a polysilicon gate; and a third to a tenth diagram showing a flow chart of a method for fabricating a germanium gate of the present invention. Figure No. Description: 10 Substrate 12 Gate Oxide Layer 12a Gate Oxide Layer 14 Polycrystalline 夕 Gate Layer 16 Gap 20 Substrate 22 Gate Oxide Layer 22a Gate Oxide Layer 24 Complex Crystal Gate Layer 26 Gap 26a Gap 100 Substrate 102 Gate Oxide Layer 102a Gate Oxide Layer 104 Polysilicon Gate Layer 104a Polysilicon Gate Layer 7 This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 PCT) --------------------- Order --------- (Please read the notes on the back and fill out this page) 1287833 A7 B7 V , invention description () 104b polycrystalline germanium gate layer 106 anti-reflective coating layer 106a anti-reflective coating layer 108 photoresist 108a photoresist 110 spacer 110a spacer 112 metal germanium economic department intellectual property bureau employee consumption cooperative printing DETAILED DESCRIPTION OF THE INVENTION: In the case where the thickness of the gate oxide layer of the cerium oxide produced by the thermal oxidation process is reduced, it is difficult to obtain a good oxide layer quality. Accordingly, the present invention provides a polysilicon gate structure using a high dielectric constant material as a gate oxide layer. In general, the oxide oxide layer utilizes a dioxide dioxide with a dielectric constant of about 4, and therefore, a higher capacitance at a thinner thickness requires an increase in the dielectric constant of the material. In addition, referring to FIGS. 2b and 2c, since the high dielectric constant material used as the gate oxide layer 2 2 is removed by a conventional dry etching process, both sides of the gate layer 24 of the polysilicon gate are exposed. A gate oxide layer 22a is formed. Therefore, when the metal ceramsite is formed on the surface of the substrate 20 and the polysilicon gate layer 24, the shortcoming of the polycrystalline quartz gate layer 24 is likely to be short-circuited. In addition, when the wet etching process is used to remove the high dielectric constant material as the gate oxide layer, the etching liquid which usually removes the high dielectric constant material may also damage other polysilicon gate structures, such as shallow trench isolation. Therefore, it is not convenient to select the etching solution. Therefore, the present invention further provides a repeating crystal gate of 8 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the back note and then fill out this page) ---- -----Order---------· 1287833
本發明-種複晶石夕間極之製造方法包括··在基材上以 例㈣學氣相沈積方式，形成閉極氧化層；再利用例如化 學虱相沈積在閘極氧化層的表面形成複晶矽閘極層，並在 複晶矽閘極層的兩側形成間隙壁；接I，進行蝕刻步驟， 去除-部分的複晶矽閘極層，藉以使得剩餘複晶矽閘極層 的表面低於間隙壁的表面；#進行定義步驟，利用複晶石夕 閘極層與間隙壁做為罩幕，#以去除未被複晶石夕閘極層與 間隙壁所覆蓋之閘極氧化層，以暴露出部分的基材。 -----------舍 (請先¾讀背面之注意事項再填寫本頁) 本發明的特點在於進行閘極氧化層之定義步驟之前， 先進行蝕刻步驟，使複晶矽閘極層表面高度低於間隙 壁。因此，在後續利用例如氬濺擊的乾蝕刻製程時，雖然 會同時去除部分的間隙壁，但經過定義步驟後的間隙壁之 高度並不會低於複晶矽閘極層，如此一來，後續形成金屬 石夕化物時，就降低短路狀況的機率。 訂---------· 經濟部智慧財產局員工消費合作社印製 第3圖至第1 0圖所繪示為利用本發明複晶矽閘極之製 造方法之流程圖。請參照第3圖，利用例如化學氣相沈積 製程以形成高介電係數材料所構成的閘極氧化層丨〇2於基 材1 00上，並在閘極氧化層丨〇2上形成一層複晶矽閘極層 本紙張尺度適用中國國家標準（CNS)A4規格（210 297 公f ) 1287833The invention relates to a method for manufacturing a polycrystalline cristobalite electrode comprising: forming a closed-pole oxide layer on the substrate by way of example (4) vapor deposition; further forming a surface of the gate oxide layer by, for example, chemical 虱 phase deposition a polysilicon gate layer, and a spacer is formed on both sides of the gate of the polysilicon gate; and an etching step is performed to remove a portion of the gate layer of the polysilicon gate, thereby leaving the gate layer of the remaining germanium gate The surface is lower than the surface of the gap wall; #The definition step is to use the double crystal and the spacer as the mask, # to remove the gate oxide which is not covered by the double crystal and the spacer Layer to expose a portion of the substrate. ----------- (Please fill in the note on the back). The feature of the present invention is that before the step of defining the gate oxide layer, an etching step is performed to make the crystal The surface of the gate layer is lower than the spacer. Therefore, in the subsequent dry etching process using, for example, argon sputtering, although a part of the spacer is removed at the same time, the height of the spacer after the defined step is not lower than the polysilicon gate layer, and thus, When the metallization is subsequently formed, the probability of a short circuit condition is reduced. Order ---------· Printed by the Intellectual Property Office of the Intellectual Property Office of the Ministry of Economic Affairs. Figures 3 to 10 show a flow chart of the manufacturing method using the gate of the polysilicon gate of the present invention. Referring to FIG. 3, a gate oxide layer 2 formed of a high dielectric constant material is formed on the substrate 100 by, for example, a chemical vapor deposition process, and a layer is formed on the gate oxide layer 丨〇2. The crystal gate layer is applicable to the Chinese National Standard (CNS) A4 specification (210 297 public f ) 1287833
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 1 04。其中，本發明實施例中所使用的高介電係數材料如二 氧化鍅（Zr02)、三氧化二鋁（Al2〇3)、三氧化二釔（γ2〇3)、 二氧化铪（Hf02)、二氧化鑭（La〇-2)、锆矽氧化物（ZrSix〇y)、 鍅鋁氧化物（ZrAlxOy)、铪矽氧化物（Hfsix〇y)、铪鋁氧化物 (HfAlxOy)等。 接著，需一定義步驟，利用光阻丨〇8作為罩幕，以定 義出複晶石夕閘極層104的位置，其中為了微影製程的方 便’係在複晶矽閘極層1 04的表面加上一層抗反射塗佈層 1 0 6。接著，請參照第4圖，進行上述的定義步驟，先去除 部分的第3圖中的抗反射塗佈層1〇6，以形成抗反射塗佈 層106a，同時也去除部分的光阻1〇8而形成光阻1〇8a。接 著，再利用光阻108a與抗反射塗佈層106a作為罩幕，去 除部分的複晶矽閘極層1 04，以形成複晶矽閘極層， 如第5圖所示。之後，請參照第6圖，去除第5圖中的光 阻108a與抗反射塗佈層i〇6a，並在複晶矽閘極層1〇4a的 兩側形成間隙壁1 1 0，如第7圖所示。 接著，請參照第8圖，進行一蝕刻步驟，去除部分第7 圖中的複晶矽閘極層l〇4a，而形成複晶矽閘極層！ 〇4b，藉 以使付複晶石夕閘極層1 〇 4 b的表面低於兩側的間隙壁1 1 〇。 其中’上述钱刻步驟中’複晶梦閘極層1 〇 4 a的去除厚度約 介於100A至500A之間。接著，再進行另一定義步驟，係 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） __ » · ---------—--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1287833 A7 B7 五、發明說明（） 利用複晶矽閘極層104b與間隙壁i 1〇做為罩幕，去除部分 未被複晶矽閘極層104b與間隙壁11〇所覆蓋之閘極氧化^ 102,以暴露出基材100之一部分，形成閘極氧化層， 如第9圖所示。另外，去除部分閘極氧化層ι〇2的同時， 間隙壁1 ίο也被去除部分，而形成間隙壁丨l〇a。其中，在 本發明實施例中，上述的定義步驟係利用氮之賤擊#刻製 程。 如此一來，經過上述步驟即可完成本發明複晶矽間極 之結構。隨後，在上述之定義步驟後，可視需要可形成金 屬矽化物112於基材1〇〇未被閘極氧化層1〇2&覆蓋的部 分，以及複晶矽閘極層l〇4b的表面部份，如第1〇圖所示。 依照上述本發明複晶矽閘極之製造方法所完成的複晶 矽閘極之結構’係如第9圖所示·。請參照第9圖，其中本 發明複晶矽閘極之結構包括：基材10〇;由高介電係數材 料所構成的閘極氧化層l〇2a位於基材1〇〇上，此閘極氧化 層1 02 a並未完全覆蓋基材100，而暴露出基材1〇〇的一部 份；一複晶矽閘極層l〇4b位於閘極氧化層102a上，此複 晶矽閘極層1 04b之寬度係小於閘極氧化層1 〇2a之寬度， 而暴露出閘極氧化層1 〇2a之兩端表面；以及，一間隙壁 1 1 〇a位於複晶矽閘極層1 〇4b之兩側，此間隙壁1 1 〇a係位 於閘極氧化層l〇2a未被複晶矽閘極層1〇4b所覆蓋的部 本紙張&度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------I-----------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1287833 A7 __ B7 五、發明說明（） 分。上述本發明複晶矽閘極之結構中，複晶矽閘極層104b 的高度可等於或小於間隙壁110a之高度。並且，本發明複 晶矽閘極之結構更可包括在後續步驟所形成第10圖之金 屬矽化物112,此金屬矽化物112係位於複晶矽閘極層⑺朴 的表面，與基材100未被閘極氧化層1〇2a覆蓋的表面，本 發明不限於此。 利用本發明複晶矽閘極之結構及其製造方法，由於利 用高介電係數材料的沈積可製造品質良好的氧化層，並改 善利用乾#刻製程在後續金屬矽化物形成易短路的情況。 如此一來，可製造良率較高的積體電路元件，並在縮小積 體電路元件之尺寸與線寬方面，有所突破。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍，凡其他未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 -------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t )Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperatives, printing, five, invention description () 1 04. The high dielectric constant materials used in the embodiments of the present invention are, for example, cerium oxide (ZrO 2 ), aluminum oxide (Al 2 〇 3 ), antimony trioxide (γ 2 〇 3 ), cerium oxide (HfO 2 ), Cerium oxide (La〇-2), zirconium lanthanum oxide (ZrSix〇y), lanthanum aluminum oxide (ZrAlxOy), lanthanum oxide (Hfsix〇y), lanthanum aluminum oxide (HfAlxOy), and the like. Next, a definition step is required to use the photoresist 8 as a mask to define the position of the polycrystalline quartz gate layer 104, wherein the convenience for the lithography process is in the gate of the polysilicon gate layer 104. The surface is coated with an anti-reflective coating layer 106. Next, referring to FIG. 4, the above-described definition step is performed, and the anti-reflection coating layer 1〇6 in the third FIG. 3 is removed first to form the anti-reflection coating layer 106a, and part of the photoresist is also removed. 8 to form a photoresist 1 〇 8a. Then, the photoresist 108a and the anti-reflective coating layer 106a are used as a mask to remove a portion of the polysilicon gate layer 104 to form a polysilicon gate layer, as shown in FIG. Thereafter, referring to FIG. 6, the photoresist 108a and the anti-reflective coating layer i〇6a in FIG. 5 are removed, and spacers 1 1 0 are formed on both sides of the polysilicon gate layer 1〇4a, as described in Figure 7 shows. Next, please refer to FIG. 8 to perform an etching step to remove the polysilicon gate layer l〇4a in part 7 to form a polysilicon gate layer! 〇 4b, so that the surface of the paying slab gate layer 1 〇 4 b is lower than the gap 1 1 两侧 on both sides. The removal thickness of the polycrystalline dream gate layer 1 〇 4 a in the above-mentioned money engraving step is between about 100A and 500A. Then, carry out another definition step, which is 10 Chinese paper (CNS) A4 specifications (210 X 297 mm). __ » · ----------------- -Book--------- (Please read the notes on the back and fill out this page) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1287833 A7 B7 V. Invention Description () Using the Fujing 矽 gate layer 104b and the spacer i1〇 serve as a mask to remove a portion of the gate oxide 102 that is not covered by the polysilicon gate layer 104b and the spacer 11〇 to expose a portion of the substrate 100 to form a gate oxide. Layer, as shown in Figure 9. Further, while a part of the gate oxide layer ι 2 is removed, the spacer 1 ίο is also removed to form a spacer 丨l〇a. In the embodiment of the present invention, the above defined steps are performed by using the nitrogen smashing process. In this way, the structure of the polycrystalline inter-electrode pole of the present invention can be completed through the above steps. Subsequently, after the above defined steps, the metal germanide 112 may be formed as part of the substrate 1〇〇 not covered by the gate oxide layer 1〇2& and the surface portion of the polysilicon gate layer l〇4b. Share, as shown in Figure 1. The structure of the polysilicon gate completed in accordance with the above-described method for fabricating a germanium gate of the present invention is as shown in Fig. 9. Please refer to FIG. 9 , wherein the structure of the polysilicon gate of the present invention comprises: a substrate 10 〇; a gate oxide layer 〇 2 a composed of a high dielectric constant material is located on the substrate 1 ,, the gate The oxide layer 102a does not completely cover the substrate 100, but exposes a portion of the substrate 1〇〇; a polysilicon gate layer 104b is located on the gate oxide layer 102a, and the polysilicon gate is The width of the layer 1 04b is smaller than the width of the gate oxide layer 1 〇 2a, and the both end surfaces of the gate oxide layer 1 〇 2a are exposed; and a spacer 1 1 〇a is located at the gate layer 1 of the polysilicon layer On both sides of 4b, the spacer 1 1 〇a is located in the gate oxide layer l〇2a is not covered by the polysilicon gate layer 1〇4b. The paper is suitable for the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) ---------I-----------Book--------- (Please read the notes on the back and fill out this page. ) 1287833 A7 __ B7 V. Description of invention () points. In the above structure of the polysilicon gate of the present invention, the height of the polysilicon gate layer 104b may be equal to or smaller than the height of the spacer 110a. Moreover, the structure of the polysilicon gate of the present invention may further comprise a metal germanide 112 formed in a subsequent step in the step 10, the metal germanide 112 being located on the surface of the polysilicon gate layer (7), and the substrate 100. The surface not covered by the gate oxide layer 1〇2a is not limited thereto. By using the structure and manufacturing method of the polysilicon gate of the present invention, a good quality oxide layer can be produced by deposition of a high dielectric constant material, and the use of a dry etching process can be used to form a short circuit in the subsequent metal telluride formation. As a result, an integrated circuit component having a high yield can be manufactured, and a breakthrough is made in reducing the size and line width of the integrated circuit component. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention. Modifications or modifications are intended to be included in the scope of the claims below. -------------------Book--------- (Please read the notes on the back and fill out this page) Ministry of Economic Affairs Intellectual Property Office Staff Cooperatives The printed paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 metric tons)