412785 A7 B7 五 '發明説明（丨） ~~~~412785 A7 B7 Five 'Explanation (丨) ~~~~
請 先I I I 1' 之I f主· r I 項} 再- 4 ί 本裝 頁I 本發明係有關於半導體積體電路的製造，且特别是有 關於一種定義閘極圖案之改良製程，其利用薄光阻層/抗反 射層/硼磷矽玻璃的疊層，並配合適當的蝕刻配方，使得薄 光阻層和抗反射層在蝕刻程序中可自動地去除，藉此改善 習知技術的缺點，並提昇產品之性質。 在半導體積體電路元件製程中，微影成像程序佔有很 重要的關鍵地位，隨著元件特徵尺寸（critical dimensi〇…持 訂 續地縮小化，必須使用更短波長的光源來進行曝光，然而 微影成像的施行條件（process window),例如聚焦景深 (depth of f0cus)，卻也因此變得更爲嚴苛，相對於以往較= 尺寸元件的製程，現今之製程已邁入G25_甚或〇」一 領域光阻層之厚度、平坦度等往昔較被忽視的因素，也Please refer to I f main · r I of III 1 '}-4 ί This page I The present invention relates to the manufacture of semiconductor integrated circuits, and in particular to an improved process for defining gate patterns, which uses Lamination of thin photoresistive layer / anti-reflective layer / borophosphosilicate glass and suitable etching formula, so that the thin photoresistive layer and anti-reflective layer can be automatically removed in the etching process, thereby improving the shortcomings of the conventional technology and improving the product The nature. In the process of manufacturing semiconductor integrated circuit components, the lithography imaging program occupies a very important and critical position. As the critical feature size (critical dimensi0 ...) continues to shrink, light sources with shorter wavelengths must be used for exposure. The process window of film imaging, such as the depth of focus (f0cus), has also become more stringent. Compared with the previous process of = size components, the process has now entered G25_ or even 0. " In the past, factors such as the thickness and flatness of the photoresist layer have been overlooked.
逐漸成爲影響元件性質的主要變數，吾人有必要予以重視 並謀求因應對策D 線 經濟部中央樣準局貝工消費合作社印製 叫參見第1A圖，在一平坦的矽基底1〇上，首先，施 行局部石夕氧化方法（LOCOS)形成一場氧化層12，以隔離元 件區（active area),造成—高底起伏的表面。其次，以熱氧 化成長方法（thermal oxidation)形成一閘極氧化屠14，覆蓄 在石夕基底的元件區表面上。接著，形成1極導電層Μ: 例如是則t學氣彳目沈積(CVDm序轉—複晶 閉極氧化層u上。之後’在間極導電層16的表面上塗： 層18 ’藉由其可流動的特性，可補償高低起伏的基 得到—平坦的表面，如第^所示者，場氧化區 12上万料的厚❹小於錢料料“。於施行 經濟部中央標率局員工消費合作社印装 412785 A7 ----—___B7 五、發明説明（） 2 程序之後，即可定義複晶矽層丨6的圖案，製得如第1B圖 顯示不同線寬的複晶石夕導線]6A、1犯、和1 6c。 然而，上述光阻層18中不同的厚度a和b，卻也造 成不佳的罩幕圖索，導致元件尺寸的偏移。由於駐波效應 的影響’光阻層不同厚度的部分將造成光阻圖案尺寸的變 化’稱之爲變異效應（swing effect)。此外，在曝光程序時， 位於場氧化層12邊緣之傾斜區域上方的複晶矽層16會將 入射光20反射’而使部分的光阻圖案失眞’造成所謂的縮 頸問題（necking problem)。 爲了更清楚地説明’第1C圖是第1B圖的上視圖，顯 不場氧化層12、元件區22、及複晶矽導線16A、16B、和 16C。雖然用來定義複晶矽導線16A和16B的光罩尺寸是 相等的，但由於光阻層18有不同的厚度變化和b)，使 得轉移到光阻層18上圖案的尺寸也隨之不同，其後更造成 複晶矽導線16A和1 όΒ尺寸的差異。此外，在第1 c圖中 同時也顯示複晶矽導線16C的縮頸部位24，其發生在基底 表面上有較明顯高度變化的區域，例如是場氧化層12與元 件區22的交界處附近。此一縮頸部位24會造成元件提早 崩潰，嚴重影響元件的電子特性。It gradually becomes the main variable that affects the properties of the components. We need to pay attention to it and seek a response. D-line Ministry of Economic Affairs Central Prototype Bureau Shellfish Consumer Cooperative Co., Ltd. Printed as shown in Figure 1A. On a flat silicon substrate 10, first, The local stone oxidation method (LOCOS) is performed to form a field oxide layer 12 to isolate the active area, resulting in a high-level undulating surface. Secondly, a gate oxidation layer 14 is formed by thermal oxidation, and is deposited on the surface of the element region of the Shixi substrate. Next, a 1-electrode conductive layer M is formed: for example, a tantalum deposition (CVDm sequential transfer—on the multi-crystal closed-pole oxide layer u.) Then, 'coating on the surface of the inter-electrode conductive layer 16: layer 18' Flowable characteristics, which can compensate for the high and low base-flat surface, as shown in Figure ^, the thickness of the material in the field oxidation zone is more than 120,000. The thickness of the material is less than that of the "material." Cooperative printed 412785 A7 --------___ B7 V. Description of the invention () 2 After the procedure, the pattern of the polycrystalline silicon layer 丨 6 can be defined, and the polycrystalline stone wires with different line widths can be produced as shown in Figure 1B] 6A, 1 and 16c. However, the different thicknesses a and b in the photoresist layer 18 described above also cause poor masking patterns, resulting in component size shifts. Due to the effect of the standing wave effect 'light The different thickness of the resist layer will cause the photoresist pattern size to change. This is called the swing effect. In addition, during the exposure process, the polycrystalline silicon layer 16 located above the sloped area of the edge of the field oxide layer 12 will The incident light 20 reflects 'and causes part of the photoresist pattern to be lost' causing the so-called The necking problem. In order to explain more clearly that FIG. 1C is a top view of FIG. 1B, the field oxide layer 12, the device region 22, and the polycrystalline silicon wires 16A, 16B, and 16C are shown. To define the size of the masks of the polycrystalline silicon conductors 16A and 16B are equal, but because the photoresist layer 18 has different thickness variations and b), the size of the pattern transferred to the photoresist layer 18 will also be different, thereafter The size difference of the polycrystalline silicon wire 16A and 1 is also caused. In addition, in FIG. 1 c, the constricted position 24 of the polycrystalline silicon wire 16C is also shown, which occurs in a region with a significant height change on the substrate surface. For example, it is near the boundary between the field oxide layer 12 and the device region 22. This shrinkage of the neck position 24 will cause the device to collapse prematurely and seriously affect the electronic characteristics of the device.
爲改善上述傳統製程的缺點，一種定義閘極蜀案的改 良製程被提出，其利用一平坦化層改善基底表面的構形 (topography)，並於塗佈光阻層之前先形成一抗反射層，既 可防止不當反射造成光阻圖案失眞，並可作爲硬式罩幕 (hard mask)供定義閘極圖案之用。以下，即參照第2A至2E 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公廣） (請先閲讀背面之注意事項再填寫本頁) .裝.In order to improve the shortcomings of the above traditional process, an improved process to define the gate electrode case is proposed, which uses a planarization layer to improve the topography of the substrate surface, and forms an anti-reflective layer before coating the photoresist layer , Which can prevent the photoresist pattern from being lost due to improper reflection, and can be used as a hard mask for defining the gate pattern. Below, referring to 2A to 2E, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). (Please read the precautions on the back before filling this page).
I I I 412785 A7 B7 五、發明説明（ 經濟部中央標準局員工消費合作社印製 圖，詳細説明此一習知技術的製造流程。 首先，如第2A圖所示，在一平坦的石夕基底1〇上，施 行局部矽氧化方法（LOCOS)形成一場氧化層12,以隔離元 件區，造成一鬲底起伏的表面。以熱氧化成長方法形成— 閘極氧化層14,覆蓋在矽基底1〇的元件區表面上。接著， 形成一閘極導電層I6,例如是以化學氣相沈積程序沈積— 複晶矽層，覆蓋在閘極氡化層14上。之後，在閘極導電層 16表面上形成一平坦化層（pianarizati〇n iay er) 15，例如是以 CVD程序沈積一堋磷矽玻璃（BPSG)層，或是塗佈一旋附玻 璃（S0G)，以改善基底的表面構形。接著在平坦化層1 $上 形成一抗反射層（anti-reflection layer)17，例如是以藏鍵程 序形成一氮化鈦（TiN)層，或是以CVD程序沈積一非晶矽 (amorphous silicon)層。 接下來’在抗反射層17表面上塗佈一光阻層18，並 施以一微影成像程序，得到如第2B圖所示之光阻圖案 18a。此處由於光阻層18係塗佈於平坦的基底表面上，並 事先形成一抗反射層I7,可防止曝光時不當的反射，因此 光罩上的圖案（未顯示）可以很眞實地轉移到光阻層18上， 並不會有圖案失眞的問題。 請參見第2C圖，利用光阻圖索丨8a當作罩幕，依序 蝕刻抗反射層17、平坦化層1 5、閘極導電層丨6、及閘極氧 化層14’得到圖中所示之圖案17a、⑸、16a、及14a。其 中’利用電漿或濕式蝕刻程序來蝕刻抗反射層17，利用含 氟之電漿独刻平坦化層15，而當蝕刻閘極導電層丨6時係利 表紙張尺度適用中國國家椟準（CNS ) A4規格（210X297公着 n tut m» , ί請先閲讀背面之注意事項再填寫本頁) 訂_ 線 經濟部中央標準局員工消費合作社印策 412785 A7 ----- B7 五、發明説明（)' '—~--- 用閘極氧化層Μ當作姓刻終止層。接著，以適當溶液或電 漿蝕刻去除光阻圖萦18a，即留下如第2D圖所示之構造二 接下來，凊參見第2E圖，去除抗反射層圖索丨和 平坦化層圖案15a，完成閘極圖案構造。例如，以氨水/雙 氧水(NH4〇H/H2〇2)溶液來蝕去抗反射層圖案17a，而以^ 氟酸（HF)溶液，或以電漿蝕刻程序去除平坦化層圖案^ 。 很明顯地，此一改良製程由於定義光阻層丨8圖索時沒有失 眞’並且抗反射層17可供作硬式罩幕’因此圖案轉移到閉 極導電層16上時’仍可保持其線寬尺寸的均一性，有效改 善傳統製程的縮頸問題。 然而，相較於傳統之製程，上述改良製程於蝕刻閘極 導電層16後’必須額外施行去除抗反射層圖案1 7a和平坦 化層圖案15a的步驟，方能留下所需的閘極圖案，因此會 增加製程的複雜度，不僅降低生產的效率，也增加影響元 件性質的機會。特别是當基底10與閘極導電層16的材質 分别爲矽與複晶矽時，若再選用非晶矽當作抗反射層17, 將因爲三者的性質相近，在去除抗反射層圖案17a的蝕刻 過程中，不可避免地會在閘極導電層16的側壁和基底1〇 露出的表面上，形成不必要的凹陷26和28，導致閘極圖案 的失眞，如第3圖之箭號所示者。 有鑑於此，本發明之一個目的，在提供一種半導體元 件的改良製程，其可避免因曝光時不當的反射所造成的縮 頸問題（necking problem)，而在起伏不平的基底表面上定義 出尺寸均一的閘極圖案。 -—--------- - 7 _ ___ 本紙張尺度適用中圑國家標準（CNS ) 格< 210XW?公釐） (請先閱讀背面之注意事項再填寫本頁) ·*·"* 經濟部中央標率局員工消費合作社印裝 412785 A7 A7 _ B7 五、發明説明（） ' 5’ 本發明另一個目的，在提供一種利用硬式罩幕以定義 閘極圖案的改良製程，其可自動移除（disp〇sable)而避免不 當钱刻所造成閘極圖案和基底表面的損傷，並可放寬曝光 程序時的操作條件（process window)，有效簡化製程步骤以 提高生產效率及降低生產成本。 爲達成上述各目的，本發明提出一種定義閘極圖案之 改良製程：首先，在一半導體基底上，依序形成—閘極氧 化層和一閘極導電層；接著，在閘極導電層上形成一疊層 構造，由下而上包括一平坦化層（planarizati〇n layer)、一抗 反射層（anti-reflection layer)、和一薄光阻層（thin photoresm);施行一微影成像程序以定義出薄光阻層的圖 案，並用以作爲一蝕刻罩幕而將其圖案轉移到抗反射層 上；接下來，選用-適當的钱刻配方，繼續钱刻平坦化層 以轉移抗反射層的圖案，其間上述薄光阻層亦一併被去 除；之後’選用另-適當的餘刻配方，繼續姓刻聞極導電 層以定義出-閘極圖案，其間抗反射層亦一併被去除；接 下來’依序餘刻閘極氧化層露出的部分，以及去除剩餘的 平坦化層，便完成該閘極圖索的製程。 根據本發明的較佳實施例，係先以熱氧化程序形成上 述閘極氧化層’其厚度介於5〇和观之間，再以一沈積 程序形成-複晶㈣當作閘極導電層，其厚度介於謂和 4000A I間。接著，上述平坦化層係_蝴缚發玻璃（Bp⑹ 層或-旋附玻璃（SOG)層，其厚度介於】_和彻〇A之間； 上述抗反射層係一氮化鈇（TiN)層或一非晶石夕^ 本紙張尺纽财關緖以〇Ts > A4_ --- (請先閱讀背面之注意事項再填寫本頁) 訂 線 娌濟部中央標準局員工消費合作杜印裝 412785 at ；------___ B7 五、發明説明（） *---- s山con)層，其厚度介於2〇〇和5〇〇A之間；上述薄光阻層 的厚度則係介於！_和5刚A之間。於域薄光阻層的圖 案後’係使用氨水/雙氧水（NH4〇H/H2〇2)溶液當作蝕刻液， 而將薄光阻層的圖案轉移到抗反射層上。接下來，選用— 適當触刻程序，其對平坦化層的㈣率大於對抗反射層 者，用以繼續蝕刻平坦化層以轉移抗反射層的圖案並且可 一併蝕去薄光阻層，例如是使用.氫氟酸（HF)或緩衝蝕刻液 (6(^)等/谷液進行濕式蝕刻，或是使用含碳氟（cf 化 合物當作反應器體進行乾式蝕刻。接著，選用另一適當蝕 刻程序，其對閘極導電層的蝕刻率大於對平坦化層者，用 以繼續蝕刻閘極導電層以定義出閘極圖案並且可一併蝕去 柷反射層，例如是使用熱磷酸溶液進行濕式蝕刻，或是使 用含氣(Cl based)化合物（CU、SiCU)或含氟(F based)化合物 (SFe、NR、和CFO當作反應氣體進行乾式蝕刻。之後，以 電漿蝕刻程序去除剩餘的平坦化層。 爲了讓本發明之上述和其他目的、特徵、及優點能更 明顯易懂，下文特舉一較佳貫施例，並配合所附圖式，作 洋細説明如下： 圖式之簡單説明 第1A至1B圖均爲剖面圖，顯示傳統之半導體元件閘 極圖案的製造流程； 第1C圖爲一上視圖，用以顯示傳統製程的缺點； 第2A至2E圖均爲剖面圖，顯示一習知利用厚光阻層 /抗反射層/平坦化層之疊層來定義閘極圖案的製造流程； __丄_____ 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公麓) " ____ (請先閣讀背面之注意事項再填寫本頁)III 412785 A7 B7 V. Description of the Invention (Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, detailing the manufacturing process of this conventional technology. First, as shown in Figure 2A, a flat Shixi substrate 1 Above, a local silicon oxidation method (LOCOS) is performed to form a field oxide layer 12 to isolate the device area and create a undulating surface. It is formed by a thermal oxidation growth method—the gate oxide layer 14 covering the device on the silicon substrate 10. Then, a gate conductive layer I6 is formed, for example, by a chemical vapor deposition process—a polycrystalline silicon layer covering the gate gate layer 14. Then, a gate conductive layer 16 is formed on the surface. A planarization layer (pianarization iayer) 15 is used, for example, to deposit a phosphophosphosilicate glass (BPSG) layer by a CVD process, or to coat a spin-on glass (S0G) to improve the surface configuration of the substrate. An anti-reflection layer 17 is formed on the planarization layer 1 $, for example, a titanium nitride (TiN) layer is formed by a key concealment process, or an amorphous silicon is deposited by a CVD process. Layer. Next 'in anti-anti- A photoresist layer 18 is coated on the surface of the radiation layer 17 and subjected to a lithography imaging procedure to obtain a photoresist pattern 18a as shown in FIG. 2B. Here, since the photoresist layer 18 is coated on a flat substrate surface And an anti-reflection layer I7 is formed in advance to prevent improper reflection during exposure, so the pattern (not shown) on the photomask can be transferred to the photoresist layer 18 without any problem. Please refer to FIG. 2C, using the photoresist line 8a as a mask, and sequentially etching the anti-reflection layer 17, the planarization layer 15, the gate conductive layer 6 and the gate oxide layer 14 '. The patterns 17a, ⑸, 16a, and 14a are shown. Among them, the anti-reflection layer 17 is etched by a plasma or wet etching process, the planarization layer 15 is etched by a plasma containing fluorine alone, and the gate conductive layer is etched丨 At 6 o'clock, the paper scale of the profit table is applicable to China National Standards (CNS) A4 specifications (210X297 public n tut m », please read the precautions on the back before filling in this page) Cooperative cooperative policy 412785 A7 ----- B7 V. Description of the invention () '' ~~ --- Use gate oxidation M is used as the last stop layer. Next, the photoresist pattern (18a) is removed with a suitable solution or plasma etching, leaving the structure shown in Figure 2D. Next, see Figure 2E to remove the anti-reflection layer. Solenoid and flattening layer pattern 15a to complete the gate pattern structure. For example, using ammonia / hydrogen peroxide (NH40H / H2O2) solution to etch away the anti-reflection layer pattern 17a, and using fluoric acid (HF) solution, Or use a plasma etching process to remove the planarization layer pattern ^. Obviously, this improved process has no loss when defining the photoresist layer, and the anti-reflection layer 17 can be used as a hard mask. Therefore, the pattern can be retained when the pattern is transferred to the closed-electrode conductive layer 16. The uniformity of the line width size effectively improves the necking problem of the traditional process. However, compared with the traditional process, the above-mentioned improved process after the gate conductive layer 16 is etched must additionally perform the steps of removing the anti-reflection layer pattern 17a and the planarization layer pattern 15a to leave the required gate pattern. Therefore, it will increase the complexity of the process, not only reduce the efficiency of production, but also increase the opportunity to affect the properties of the components. Especially when the materials of the substrate 10 and the gate conductive layer 16 are silicon and polycrystalline silicon, if the amorphous silicon is used as the anti-reflection layer 17, the anti-reflection layer pattern 17a will be removed because the properties of the three are similar. During the etching process, it is inevitable that unnecessary recesses 26 and 28 will be formed on the sidewalls of the gate conductive layer 16 and the exposed surface of the substrate 10, resulting in the loss of the gate pattern, as shown by the arrow in Figure 3. Shown. In view of this, it is an object of the present invention to provide an improved process for a semiconductor device, which can avoid necking problems caused by improper reflection during exposure, and define a size on the surface of an uneven substrate. Uniform gate pattern. -—----------7 _ ___ This paper size applies to China National Standard (CNS) grid < 210XW? Mm) (Please read the precautions on the back before filling this page) · * · " * Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 412785 A7 A7 _ B7 V. Description of the invention () '5' Another object of the present invention is to provide an improved process that uses a hard screen to define the gate pattern. It can be automatically removed (disposable) to avoid damage to the gate pattern and substrate surface caused by improper money engraving, and can relax the process window during the exposure process, effectively simplifying the process steps to improve production efficiency and reduce Cost of production. In order to achieve the above objects, the present invention proposes an improved process for defining a gate pattern: first, a gate oxide layer and a gate conductive layer are sequentially formed on a semiconductor substrate; and then, a gate conductive layer is formed on the semiconductor substrate. A stacked structure including a planarization layer, an anti-reflection layer, and a thin photoresm from bottom to top; a lithography imaging procedure is performed to define The pattern of the thin photoresist layer is used as an etch mask to transfer its pattern to the anti-reflection layer. Next, select the appropriate coin-cut formula and continue to coin the flattening layer to transfer the pattern of the anti-reflection layer. The thin photoresist layer was also removed at the same time; after that, another “appropriate remaining formula” was used, and the conductive layer was engraved to define the gate pattern, and the anti-reflection layer was also removed in the meantime. The exposed part of the gate oxide layer is etched, and the remaining planarization layer is removed to complete the gate map process. According to a preferred embodiment of the present invention, the above-mentioned gate oxide layer is first formed by a thermal oxidation process with a thickness of between 50 and 50 Å, and then formed by a deposition process-a polycrystalline silicon oxide is used as the gate conductive layer. Its thickness is between so-called and 4000A I. Next, the above-mentioned planarization layer is a ________ (Bp⑹ layer or a spin-on-glass (SOG) layer, the thickness of which is between __ and 〇〇A; the anti-reflection layer is a thallium nitride (TiN) Layer or an amorphous stone eve ^ This paper rule New Cai Guan Xu 〇Ts > A4_ --- (Please read the precautions on the back before filling out this page) Threads of the Ministry of Economic Affairs Central Standards Bureau Consumer Consumption Du Yin 412785 at; ------___ B7 V. Description of the invention () * ---- s mountain con) layer, the thickness is between 200 and 500A; the thickness of the thin photoresistive layer is It's between! _ And 5 Gang A. After the pattern of the thin photoresist layer in the domain, an ammonia / hydrogen peroxide (NH4OH / H2O2) solution is used as an etching solution, and the pattern of the thin photoresist layer is transferred to the anti-reflection layer. Next, choose—appropriate engraving procedure, the rate of flattening layer is higher than that of anti-reflection layer, and it is used to continue to etch the flattening layer to transfer the pattern of the anti-reflection layer and etch away the thin photoresist layer together. Hydrofluoric acid (HF) or buffered etching solution (6 (^), etc./valley solution for wet etching, or dry etching using fluorocarbon (cf compound as the reactor body). Then, another appropriate etching is selected. Program, which has a higher etch rate for the gate conductive layer than for the planarization layer, and is used to continue to etch the gate conductive layer to define the gate pattern and etch away the radon reflection layer, such as using a hot phosphoric acid solution to wet Type etching, or dry etching using Cl based compounds (CU, SiCU) or F based compounds (SFe, NR, and CFO as reactive gases). After that, the remaining plasma is removed by a plasma etching process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and the following detailed description is given in conjunction with the accompanying drawings: Brief Description Section 1A Figure 1B is a cross-sectional view showing the manufacturing process of a traditional semiconductor device gate pattern. Figure 1C is a top view showing the disadvantages of the traditional process. Figures 2A to 2E are cross-sectional views showing a conventional use. The stack of thick photoresistive layer / anti-reflection layer / planarization layer to define the gate pattern manufacturing process; __ 丄 _____ This paper size applies to Chinese national standards (CNS > A4 specification (210X297)) " ____ (Please read the notes on the back before filling out this page)
經濟部中央標準局員工消費合作社印製 五、發明説明（7) 第3圖爲一剖面圖，顯示當抗反射層爲一非晶矽層 時，第2A至2E圖的習知製程會造成閘極導電層側壁和基 底表面產生凹陷；以及 第4A至4E圖均爲剖面圖，顯示根據本發明改良方法 一較佳實施例的製造流程。 實施例 首先，如第4A圖所示，β局部矽氧化方法（LOCOS) 在一平坦的半導體基底40，例如是一矽晶圓上，形成一場 氧化層42以隔離元件區，造成高底起伏的表面構形。以熱 氧化方法成長一閘極氧化層44,覆蓋在半導體基底40表面 上，其厚度介於50和200A之間。接著，形成一閘極導電 層46，例如是以化學氣相沈積程序沈積一複晶矽層，覆蓋 在閘極氧化層44上，其厚度介於2000和4000人之間。之 後，在閘極導電層46表面上形成一平坦化層（planarization layer)45,例如是以CVD程序沈積一硼磷矽玻璃（BPSG)層， 或是塗佈一旋附玻璃（S0G)層，以改善基底的表面構形，其 厚度介於1000和4000A之間。接著，在平坦化層45上形 成一抗反射層（anti-reflection layer)47，例如是以濺鍍程序 形成一氮化鈦（TiN)層，或是以CVD程序沈積一非晶矽 (amorphous silicon)層，其厚度介於200和50〇A之間。 接下來，在抗反射層4 7表面上塗怖一薄光阻層，並施 以一微影成像程序，得到如第4B圖所示之光阻圖案48a。 由於此一光阻層的功用僅在於後續蝕刻抗反射層47時作爲 罩幕之用，因此其厚度可較習知者爲小，例如是介 -10- -----------------ΐτ—-----^ - -· - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） 412785 Α7 Β7 五、發明説明（ 經濟部中央標準局貞工消費合作社印製 % 1000 p 5000A之間，不僅可放寬微影成像的施行條件， 有利於70件尺寸更加縮小化的應用，且其所需的曝光劑量 (dosage)也得以降低，有助於提昇生產效率。 凊參見第4B圖，利用光阻圖案48a當作罩幕，蝕刻 抗反射層47至露出平坦化層45爲止，用以形成抗反射層 圖案47a。由於抗反射層47的材質爲氮化鈦或非晶矽，囡 此可以氨水/雙氧水（NH4〇H/H2〇2)溶液來進行蝕刻。接著， 選用一適當蝕刻程序，例如是使用氫氟酸（HF)或緩衝蝕刻 液(BOE)等溶液進行濕式蝕刻，或是使用含碳氟（cf based) 化合物當作反應氣體進行乾式蝕刻，用以繼續向下蝕刻平 坦化層45至露出閘極導電層46爲止，形成如第4C圖所示 之平坦化層圖案45a。由於此一蝕刻程序，對平坦化層45 的蝕刻率大於對抗反射層47者，並且也會蝕刻光阻層圖案 48a ’因此抗反射層圖案47a可作爲蝕刻平坦化層時的 硬式罩幕，且當定義完成平坦化層圖案45a後，薄光阻層 圖案48a也可自動移除（disp〇sable)，毋須額外的清除步驟。 接下來，施行第二次蝕刻程序’例如是使用熱磷酸溶 液進行濕式蝕刻，或是使用含氣（C1 based)化合物（C12、Sicu) 或含孰（Fbased)化合物（SF6、NF3、和CF4)當作反應氣體進 仃乾式蝕刻，用以繼續向下蝕刻閘極導電層46至露出閘極 氧化層44爲止，形成如第4D圖所示之閘極導電層圖案 46a。再一次地，由於此一蝕刻程序對閘極導電層46的蝕 刻率大於對平坦化層45者，並且也會蝕刻抗反射層圖案 47a，因此平坦化層圖案45a可作爲蝕刻閘極導電層牝時 請 先 閱 ύ 背 Λ 之 注 _ 項 再 旁 % 丁 線 I紙張尺度適用準（CNS )八4胁（2【〇χ 29?^ - —__ A7 —------B7 五、發明説明（) ------ 9 的硬式罩幕’且當定義完成閘極導電層圖t伽後，抗反 射層圖案47a可自動移除（tiisposab丨e)，亦毋須額外的清除 步驟。 ' 接著，請參見第4E圖，蝕去閘極氧化層44未被閘極 導電層圖案46a蓋住的部分，形成閘極氧化層圖索44a。最 後以迫桌钱刻程序，去除平坦化層圖案45a，即完成定義 閘極圖案的製程。 、與習知技術栢比較，本發明所提出定義閘極圖案之改 良製程，具有下列優點： 1. 由於利用平坦化層來補償基底上的高低起伏，得到 一平坦的表面，並且利用抗反射層來消除曝光時不當的光 反射，因此可避免光阻圖案發生縮頸問題。 2. 由於光阻層僅用以當作蝕刻抗反射層時的罩幕，其 所而厚度遠較習知者爲小，不僅可放寬微影成像的施行條 件’有利於70件尺寸更加縮小化的應用，其所需的曝光劑 TE也可以降低’有助於提昇生產效率。 經濟部中央標準局貝工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 3. 由於適當地選用蝕刻配方，因此薄光阻層和抗反射 層可分别在触刻平坦化層和蝕刻閘極導電層時自動移除， 並不需額外的蝕刻處理，可簡化製程步骤，降低元件的生 產成本。 本發明雖然已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者’在不脱離本發明之精 神和範園内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範園所界定者爲準。 張尺度朝巾關家料（CNS )Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) Figure 3 is a cross-sectional view showing that when the anti-reflection layer is an amorphous silicon layer, the conventional manufacturing process of Figures 2A to 2E will cause a gate The side walls of the electrode conductive layer and the surface of the substrate are recessed; and FIGS. 4A to 4E are cross-sectional views showing a manufacturing process according to a preferred embodiment of the improved method of the present invention. Embodiment First, as shown in FIG. 4A, the β local silicon oxidation method (LOCOS) is formed on a flat semiconductor substrate 40, such as a silicon wafer, to form a field oxide layer 42 to isolate the device region, resulting in high-level undulations. Surface topography. A gate oxide layer 44 is grown by a thermal oxidation method and covers the surface of the semiconductor substrate 40 with a thickness between 50 and 200A. Next, a gate conductive layer 46 is formed. For example, a polycrystalline silicon layer is deposited on the gate oxide layer 44 by a chemical vapor deposition process, and the thickness is between 2000 and 4,000. After that, a planarization layer 45 is formed on the surface of the gate conductive layer 46, for example, a borophosphosilicate glass (BPSG) layer is deposited by a CVD process, or a spin-on-glass (SOG) layer is coated. In order to improve the surface texture of the substrate, its thickness is between 1000 and 4000A. Next, an anti-reflection layer 47 is formed on the planarization layer 45, for example, a titanium nitride (TiN) layer is formed by a sputtering process, or an amorphous silicon is deposited by a CVD process. ) Layer with a thickness between 200 and 50 OA. Next, a thin photoresist layer is coated on the surface of the anti-reflection layer 47, and a lithography imaging process is performed to obtain a photoresist pattern 48a as shown in FIG. 4B. Since the function of this photoresistive layer is only used as a mask when the anti-reflection layer 47 is subsequently etched, its thickness can be smaller than those known, for example, -10--10 --------- ------- ΐτ —----- ^----(Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X29? mm) 412785 Α7 Β7 V. Description of the invention (printed between% 1000 p and 5000A by the Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, not only can relax the implementation conditions of lithography imaging, but also facilitate 70 applications that have been reduced in size. The required exposure dose is also reduced, which helps to improve production efficiency. 凊 Refer to Figure 4B, using the photoresist pattern 48a as a mask, and etching the anti-reflection layer 47 until the planarization layer 45 is exposed for forming Anti-reflection layer pattern 47a. Since the material of the anti-reflection layer 47 is titanium nitride or amorphous silicon, it can be etched with ammonia / hydrogen peroxide (NH4OH / H2O2) solution. Then, an appropriate etching process is selected. For example, wet etching using a solution such as hydrofluoric acid (HF) or buffered etching solution (BOE), Or use cf based compound as a reactive gas for dry etching to continue to etch the planarization layer 45 downward until the gate conductive layer 46 is exposed to form a planarization layer pattern as shown in FIG. 4C 45a. Because of this etching process, the etch rate of the planarization layer 45 is greater than that of the anti-reflection layer 47, and the photoresist layer pattern 48a is also etched. Therefore, the anti-reflection layer pattern 47a can be used as a hard mask when etching the planarization layer. After the flattening layer pattern 45a is defined, the thin photoresist layer pattern 48a can also be automatically removed (disposable) without the need for an additional removal step. Next, a second etching process is performed, for example, using a hot phosphoric acid solution. Wet etching, or dry etching using gas-containing (C1 based) compounds (C12, Sicu) or F-based compounds (SF6, NF3, and CF4) as reactive gases to continue to etch down the gate The gate conductive layer 46 is formed until the gate oxide layer 44 is exposed, and a gate conductive layer pattern 46a as shown in FIG. 4D is formed. Again, the etching rate of the gate conductive layer 46 is greater than that of the flat layer due to this etching process. The layer 45 and the anti-reflection layer pattern 47a will be etched. Therefore, the flattening layer pattern 45a can be used as an etching gate conductive layer. Please read the Note_ item on the back of the Λ item next to% 丁 线 I paper size applicable standards (CNS) Eight 4 threats (2 [〇χ 29? ^-—__ A7 —------ B7 V. Description of the invention () ------ 9's hard cover 'and when the gate is defined After the conductive layer pattern is t-gamma, the anti-reflection layer pattern 47a can be automatically removed (tiisposab), and no additional cleaning step is required. 'Next, referring to FIG. 4E, a portion of the gate oxide layer 44 not covered by the gate conductive layer pattern 46a is etched to form a gate oxide layer map 44a. Finally, the process of defining the gate pattern is completed by removing the flattening layer pattern 45a by using a forcing process. Compared with the conventional technology, the improved process of defining the gate pattern proposed by the present invention has the following advantages: 1. A flattening layer is used to compensate for the fluctuations on the substrate, a flat surface is obtained, and an anti-reflection layer is used. In order to eliminate improper light reflection during exposure, the necking problem of the photoresist pattern can be avoided. 2. Since the photoresist layer is only used as a mask when etching the anti-reflection layer, its thickness is much smaller than that of a known person, which not only relaxes the implementation conditions of lithography imaging, which is conducive to reducing the size of 70 pieces For the application, the required exposure agent TE can also be reduced, which helps improve production efficiency. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative (please read the precautions on the back before filling this page) 3. Due to the appropriate selection of the etching formula, the thin photoresist layer and anti-reflection layer can be etched on the flattening layer and the etching respectively The gate conductive layer is automatically removed when no additional etching is required, which can simplify the process steps and reduce the production cost of the device. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be as defined in the attached patent application park. Zhang Jiuzhi Chaojin Guan Family Materials (CNS)