TW200402779A

TW200402779A - Method for fabricating a gate structure of a field effect transistor

Info

Publication number: TW200402779A
Application number: TW092116580A
Authority: TW
Inventors: Wei Liu; Thorsten B Lill; David S L Mui; Christopher Dennis Bencher
Original assignee: Applied Materials Inc
Priority date: 2002-06-20
Filing date: 2003-06-18
Publication date: 2004-02-16
Also published as: WO2004001799A2; WO2004001799A3; US20040043623A1; US6924191B2

Abstract

A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Description

200402779 玖、發明說明【發明所屬之技術領域1 本發明大體上係關於一種製造元件於半導體基方法。更特定地，本發明係關於一種製造一場效電閘極結構的方法。【先前技術】超大型積體（ULSI)電路典型地包括多於一百萬個體它們被形成在一半導體基材上且相合作用以在一電置中實施不同的功能。這些電晶體可包括互補的金屬物半導體（cos)場效電晶體。一 CMOS電晶體包括一閘極結構其被設置在該體基材上的一源極區與一汲極區之間。該閘極結構大包含一閘極電極其形成在一閘極介電材質之上。該閘極控制一電荷載體流，其在該閘極界電質底下的一通内’該通道係形成在該汲極區與源極區之間，用以將晶體打開或關閉。該通道，嫉極與源極區在此技藝中稱為”電晶體接面，，。降低電晶體接面的尺寸是一不變勢’因此閘極電極的寬度被減小用以提高電晶體的操度。在一 CMOS電晶體製程中，一被石版印刷地形案的罩幕於飿刻及沉麥處理期間被使用，用以形成該電極。然而，當電晶體接面尺寸被減小時（如，尺寸 1 Onm時）’即很難用傳統的石版印刷技術來精確地界上的體的電晶子裝氧化半導體上極電道區該電被通的趨作速成圖閘極小於定閘 200402779 極電極寬度。因此，在此技藝中對於可製造具有縮小的尺寸之場效電晶體的閘極結構的方法存在者需求。【發明内容】本發明是-種製造特徵結構於一縮小尺寸的基材上之方法。該等特徵結構是藉由界定一第一罩幕於該基材的區域上而形成的。該第-罩幕係使用石版印刷術製造的。一第二罩幕然後被保形地（conformably)形成在該第一罩幕的或多個側壁上。該等特徵結構係藉由將該第一罩幕去除’然後用該第二罩幕作為一蝕刻罩幕來蝕刻該基材而被形成在該基材上。在本發明的一實施例中，一場效電晶體的一閘極結構被製造。該閘極結構包含一閘極電極其形成在一閘極介電層上。該閘極結構係藉由沉積一第一罩幕層於一形成在一基材上的閘極介電層上覆蓋多個需要被界定電晶體接面的區域上而被製造的。一第一罩幕被石版印刷地界定在該第一罩幕層上。然後一第二罩幕被保形地形成在該第一罩幕的一或多個側壁上。該閘極電極係藉由去除掉該第一罩幕並使用該第二罩幕作為一蝕刻罩幕來蝕刻該閘極電極層而被形成的。【實施方式】本發明是一種製造特徵結構於一縮小尺寸的基材上之 4 200402779 方法。該等特徵結構是藉由界定一第一罩幕於該基材的區域上而形成的。該第一罩幕係使用石版印刷術製造的。一第一罩幕然後被保形地（conf〇rmably)形成在該第一罩幕的一或多個側壁上。該等特徵結構係藉由將該第一罩幕去除’然後用該第二罩幕作為一蝕刻罩幕來蝕刻該基材而被形成在該基材上。本發明以用於製造一場效電晶體的的一閘極結構於一基材的方法為例來加以說明。該閘極結構包含一閘極電極其形成在一閘極介電層上。該閘極結構係藉由沉積一第一罩幕層於一形成在一基材上的閘極介電層上覆蓋多個需要被界定電晶體接面的區域上而被製造的。一第一罩幕被石版印刷地形成在該閘極電極層上介於需要形成電晶體接面的相鄰區域之間。第二罩幕然後被保形地形成在該第一罩幕的一或多個側壁上，使得每一第二罩幕都位在一將被形成的電晶體接面的一通道區上方。該閘極結構係藉由去除掉該第一罩幕並使用該第二罩幕作為一蝕刻罩幕來蝕刻該閘極電極層而被形成的。被保形地形成在該第一罩幕的一或多個側壁上的第二罩幕的厚度被用來界定該等但晶體的閘極但極的寬度。此第二罩幕寬度與沉積處理有關，而與石版印刷處理無關，且可有利地提供小於3〇nm的閘極寬度。第1 A-1 B圖共同顯示依據本發明的一製造一閘極電極的處理程序1 00的流程。此處理程序1 〇〇包含於一場效電晶體（如，CMOS電晶體）的製造期間被實施於一閘極電 200402779 極膜層堆疊上的處理步驟。第2A-2G圖顯示一基材的示意剖面圖（第2A-2H，2J， 2N-2Q圖）及示意頂視圖（第21，2K-2M圖），其中一閘極電極使用第1圖的處理程序被形成於該基材上。為了更清楚地瞭解本發明，讀者應同時參照第1A-1B圖與2A-2Q 圖。第2A-2Q圖與用來形成閘極電極的各個處理步驟相關連。次要製程及石版印刷常規處理（如，光阻的曝光及200402779 (ii) Description of the invention [Technical field to which the invention belongs 1 The present invention relates generally to a method for manufacturing a device based on a semiconductor. More specifically, the present invention relates to a method for manufacturing a field effect gate structure. [Prior Art] Ultra large integrated circuit (ULSI) circuits typically include more than one million bodies that are formed on a semiconductor substrate and cooperate to perform different functions in an electrical device. These transistors may include complementary metal-semiconductor (cos) field-effect transistors. A CMOS transistor includes a gate structure disposed between a source region and a drain region on the bulk substrate. The gate structure generally includes a gate electrode formed on a gate dielectric material. The gate controls a charge carrier flow, which is in a pass under the gate boundary mass. The channel is formed between the drain region and the source region to open or close the crystal. This channel, the electrode and source region is called "transistor junction" in this technique. Reducing the size of the transistor junction is a constant potential, so the width of the gate electrode is reduced to increase the transistor. In a CMOS transistor manufacturing process, a lithographic mask was used during engraving and Shenmai processing to form the electrode. However, when the size of the transistor junction was reduced ( For example, when the size is 1 Onm), that is, it is difficult to use traditional lithographic printing technology to accurately determine the size of the body's electrical crystals. The upper electrode track area of the semiconductor has a tendency to become faster. The gate is smaller than the fixed gate 200402779. The width of the electrode. Therefore, there is a need in this technology for a method of manufacturing a gate structure of a field effect transistor having a reduced size. [Summary of the Invention] The present invention is a method for manufacturing a characteristic structure on a reduced size substrate The above method. The characteristic structures are formed by defining a first mask on the area of the substrate. The first mask is manufactured using lithography. A second mask is then conformal (Conformably) formed on the side wall or walls of the first mask. The features are etched by removing the first mask and then using the second mask as an etching mask to etch the substrate. Is formed on the substrate. In an embodiment of the present invention, a gate structure of a field effect transistor is manufactured. The gate structure includes a gate electrode formed on a gate dielectric layer. The The gate structure is manufactured by depositing a first cover layer on a gate dielectric layer formed on a substrate to cover a plurality of areas that need to define transistor junctions. A first cover The curtain is lithographically defined on the first mask layer. Then a second mask is conformally formed on one or more side walls of the first mask. The gate electrode is removed by removing the The first mask is formed by using the second mask as an etching mask to etch the gate electrode layer. [Embodiment] The present invention is a manufacturing method of a feature structure on a reduced-size substrate 4 200402779 Method. The characteristic structures are defined by a first curtain on the The first mask is made using lithography. A first mask is then conformally formed on one or more side walls of the first mask. The characteristic structures are formed on the substrate by removing the first mask and then using the second mask as an etching mask to etch the substrate. The invention is used for manufacturing a field effect. The method of a gate structure of a transistor on a substrate is described as an example. The gate structure includes a gate electrode formed on a gate dielectric layer. The gate structure is formed by depositing a first A mask layer is fabricated on a gate dielectric layer formed on a substrate and covering a plurality of areas that need to define a junction of the transistor. A first mask layer is lithographically formed on the gate. The electrode layer is interposed between adjacent regions where the junction of the transistor is needed. A second mask is then conformally formed on one or more side walls of the first mask such that each second mask is positioned above a channel region of a transistor junction to be formed. The gate structure is formed by removing the first mask and using the second mask as an etching mask to etch the gate electrode layer. The thickness of the second mask, which is conformally formed on one or more side walls of the first mask, is used to define the gate but pole width of the crystals. This second mask width is related to the deposition process and has nothing to do with the lithographic process, and can advantageously provide a gate width of less than 30 nm. Figures 1A-1B together show the flow of a processing procedure 100 for manufacturing a gate electrode according to the present invention. This processing procedure 100 includes processing steps implemented on a gate electrode 200402779 electrode film layer stack during the manufacture of a field effect transistor (eg, a CMOS transistor). Figures 2A-2G show a schematic cross-sectional view of a substrate (Figures 2A-2H, 2J, 2N-2Q) and a schematic top view (Figures 21, 2K-2M). One of the gate electrodes uses the A processing program is formed on the substrate. In order to understand the present invention more clearly, the reader should refer to Figures 1A-1B and 2A-2Q simultaneously. Figures 2A-2Q are related to the various processing steps used to form the gate electrode. Minor processes and conventional lithographic processes such as photoresist exposure and

顯影’晶圓清洗程序，及類此者）並未於第1 A -1 B圖及第 2A-2Q圖示出。在第2A-2Q圖中的圖像並不是以比例被晝出且其只是作為舉例的目的。處理程序100藉由形成一閘極電極堆疊2〇2於一晶圓 200上而從步驟101開始。晶圓200 ,如一矽晶圓，具有源極區（井）234及汲極區（井）232，它們被一通道區236所隔開將被形成於該通道區中的接面係以虛線示出。該問極電極堆疊202包含一榨極電極層206其被形成在；1電層204上。該閘及電極層206是由經過摻雜的矽所形成且達約2000埃（A)的厚度。介電層2〇4是由二氧化夕（。2)所形成且達約2〇-60埃（A)的厚度。該閘極介電層 2〇4可非必要地由_或多層物質戶斤構成，如二氧化石夕 θ 氧化蛤矽Sl〇1)，及三氧化二鋁（αι2ο3)且其厚度等於單一的二氧化石夕層相同。“，應被瞭解的是，該閘極電極油蟲0 Λ 0 且可匕3由其它物質形成的層或據有不同厚度的層。包含閘極電極堆疊 1 02的層可使用一真空沉積技術 200402779 像是原子層沉積（ALD)，物理氣相沉積（PVD)，化學氣相沉積（CVD)，蒸發，及類此者。CMOS場效電晶體的製造可使用由設在美國加州Santa Clara市的Applied Material 公司所製造的 CENTURA®，ENDURA®，及其它半導體晶圓處理系統來實施。在步驟104，一第一罩幕層226及一介電抗反射塗層 (DARC)208被依序地形成在該閘極電極層 206上（第2B 圖）。在一舉例性的實施例中，該第一罩幕層 2 2 6包含一非晶形碳（即，α -碳）其厚度介於3 0 0埃至5 0 0埃之間，而該介電抗反射塗層（DARC)208則可包含璗氧化石夕 (Si ON)，二氧化系，及類此者且其厚度介於1〇〇至300埃之間。該DARC層208的作用是要將圖案形成步驟期間的光線反射減至最小。當特徵結構的尺寸被所縮小時，在餘刻罩幕圖案轉移處理中的不精確性會因為石版印刷處理所本有的光學限制，像是光的反射，而產生。罩幕層2 26 及D ARC層1〇8沉積技術被描述於2000年六月8入提申的美國專利申請案第〇9/5 90,3 22號及2001年七月13入提申的美國專利申請案第09/9〇5，172號中，該等申請案的内容藉由此參照而被併於本文中。在步驟106，一第一圖案光阻罩幕212被形成在該介電抗反射塗層（DARC)208的區域221中（第2C圖）。該第一圖案光阻罩幕2 1 2 :係使用傳統的石版印刷圖案常規處理來形成，即該光阻經由一罩幕被曝光，被顯影，且該光阻之未被顯影的部分被去除。被顯影的光阻大體上為一碳基 7 200402779 的聚合物其如一蝕刻罩幕般地留在該區域22 1的DARC 層2〇8的上方，該區域在一蝕刻處理期間需要被保護（第 2C圖）。該光阻罩幕212具有一線寬207(如，約l〇〇nm) 及一空間209(約150nm)它們一起界定節距214(即，線寬加上空間，l〇〇nm+15〇nm = 25〇nm)。該光阻212被放在該 DARC層208上使得區域221位在相鄰的電晶體252及254 之將被形成的閘極對2 5 0的上方及之間的中心處。Development 'wafer cleaning procedures and the like are not shown in Figures 1A-1B and 2A-2Q. The images in Figures 2A-2Q are not scaled out and are for illustration purposes only. The process 100 starts from step 101 by forming a gate electrode stack 202 on a wafer 200. Wafer 200, such as a silicon wafer, has a source region (well) 234 and a drain region (well) 232, which are separated by a channel region 236. The interface to be formed in the channel region is shown in dotted lines. Out. The interrogation electrode stack 202 includes a squeezing electrode layer 206 which is formed on an electrical layer 204. The gate and electrode layer 206 is formed of doped silicon and has a thickness of about 2000 Angstroms (A). The dielectric layer 204 is formed of the oxide (.2) and has a thickness of about 20-60 angstroms (A). The gate dielectric layer 204 may optionally be composed of _ or multiple layers of material, such as SiO2, θ, SiO2, and Al2O3 (αι2ο3) and their thickness is equal to a single thickness. The dioxide layer is the same. "It should be understood that the gate electrode oil worm 0 Λ 0 and which can be formed of other materials or layers with different thicknesses. The layer containing the gate electrode stack 102 can be vacuum-deposited. 200402779 Such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, and the like. CMOS field effect transistors can be manufactured by Santa Clara, California. CENTURA®, ENDURA®, and other semiconductor wafer processing systems manufactured by Applied Material Corporation are implemented. At step 104, a first cover layer 226 and a dielectric anti-reflective coating (DARC) 208 are sequentially It is formed on the gate electrode layer 206 (FIG. 2B). In an exemplary embodiment, the first mask layer 2 2 6 includes an amorphous carbon (that is, α-carbon) with a thickness between 3 and 3 Å. Between 0 0 angstroms and 50 angstroms, and the dielectric anti-reflection coating (DARC) 208 may include thoron oxide (Si ON), dioxide, and the like and its thickness is between 10 0 to 300 angstroms. The role of the DARC layer 208 is to reduce the reflection of light during the patterning step. Minimal. When the size of the feature structure is reduced, inaccuracies in the pattern transfer process of the remaining masks will be caused by the inherent optical limitations of the lithography process, such as light reflection. Mask layer 2 The 26 and D ARC layer 108 deposition technology is described in U.S. Patent Application Nos. 09 / 90,3,22 filed on June 8, 2000 and U.S. Patent Applications filed on July 13, 2001. The contents of these applications are incorporated herein by reference in No. 09 / 90.5, 172. At step 106, a first patterned photoresist mask 212 is formed on the dielectric anti-reflection coating. Layer (DARC) 208 in area 221 (Figure 2C). The first patterned photoresist mask 2 1 2: is formed using conventional lithographic printing pattern conventional processing, that is, the photoresist is exposed through a mask, It is developed, and the undeveloped part of the photoresist is removed. The developed photoresist is generally a carbon-based 7 200402779 polymer, which remains as an etching mask in the area 22 1 of the DARC layer 2. Above 8 the area needs to be protected during an etching process (Figure 2C). The photoresist mask 21 2 has a line width of 207 (eg, about 100 nm) and a space 209 (about 150 nm) which together define a pitch 214 (ie, line width plus space, 100 nm + 150 nm = 25 nm) The photoresistor 212 is placed on the DARC layer 208 so that the region 221 is located above and between the gate pairs 250 of the adjacent transistor 252 and 254 to be formed.

在步驟208，該光阻罩幕212的線寬207可非必要地藉由使用一光阻罩幕修整（trimming)處理而被減小至一所想要的值21 1 (如，約40至80nm)(第2D圖）。該線寬207 可被修整用以更加精確地將該光阻罩幕2 1 2放在相鄰的電晶體252及254之將被形成的閘極對250的上方及之間的中心處。該罩幕修整處理為一電漿處理其使用氧基的化學物來實施光阻的等方向蝕刻。該修整處理將線寬207減小至所想要的值2 1 1，以及減小該光阻罩幕2 1 2的高度。該被修整的罩幕212保護比區域221 (第2C圖）更窄的區域 223(第 2D 圖）。該經過修整的罩幕212的線寬211被選擇成與將被製造的閘極對250的空間關鍵尺寸（CD)相等。該空間213 被選擇用以不大於介於電晶體2 5 2，2 5 4的相鄰對（如，對 250及260)之間的間隔219。當石版印刷圖案疼理的解析度不足以將一精確的閘極結構圖像轉移至一光阻罩幕212上時，該光阻罩幕修整處理是所想要的。 8 200402779 步驟1 0 8可在一蝕刻反應器中實施，像是由設在美國加州 Santa Clara市的 Applied Material 公司所製造之 CENTURA®的 Decoupled Plasma Source(DPS) Π 模組。該 DPS II使用2MHz的電感式電漿源來產生一高密度電漿。該晶圓被一 13·56ΜΗζ偏壓源所偏壓。該電漿源的解耦合本質讓離子能量及離子密度的獨立控制成為可能。該DPS II模組將於下文中參照第3圖加以詳細說明。In step 208, the line width 207 of the photoresist mask 212 may be optionally reduced to a desired value 21 1 (eg, about 40 to 80nm) (Figure 2D). The line width 207 can be trimmed to more accurately place the photoresist mask 2 1 2 above and at the center between the gate pair 250 to be formed of the adjacent transistors 252 and 254. The mask trimming process is a plasma treatment that uses an oxygen-based chemical to perform isotropic etching of photoresist. This trimming process reduces the line width 207 to a desired value 2 1 1 and reduces the height of the photoresist mask 2 1 2. The trimmed mask 212 protects an area 223 (Figure 2D) which is narrower than the area 221 (Figure 2C). The line width 211 of the modified mask 212 is selected to be equal to the spatial critical dimension (CD) of the gate pair 250 to be manufactured. The space 213 is selected to be no larger than the interval 219 between adjacent pairs (eg, pairs 250 and 260) of the transistors 2 5 2 and 2 5 4. When the resolution of the lithographic pattern is insufficient to transfer an accurate gate structure image to a photoresist mask 212, the photoresist mask trimming process is desired. 8 200402779 Step 108 can be implemented in an etch reactor, such as a CENTURA® Decoupled Plasma Source (DPS) Π module manufactured by Applied Material Corporation of Santa Clara, California. The DPS II uses a 2MHz inductive plasma source to generate a high-density plasma. The wafer was biased by a 13 · 56MΗζ bias source. The decoupling nature of the plasma source enables independent control of ion energy and ion density. The DPS II module will be described in detail below with reference to FIG. 3.

在一替代實施例中，該罩幕2 1 2的窗係使用一電漿來修整，該電聚包含3至200sccm流率的溴化氫（HBr)，5 至lOOsccm的氧氣（相應於Hbr:02的流率比為1:3〇至40: 1)及氬氣（Ar)的流率在1〇至200sccm之間。該電漿係使用200至約2000W的電漿功率及0至30W的偏壓功率，晶圓托盤的溫度係介於0至80 °C之間且室壓力是在2至 30mTorr之間所產生的。一舉例性的光阻修整處理為使用 80sccm的 HBr流率，2 8 s c c m的Ο 2流率（即，Η B r: Ο 2的流率比約為2 5 · 1)， 20sccm的Ar流率，500W的電漿功率，0W的偏壓功率，及在4mTorr的室壓力下的65°C晶圓托盤溫度。在步驟110，該蝕刻罩幕的圖案經由DARC層208及非晶型碳罩幕層226(第2E圖）被轉移用以形成一第一罩幕220。在步驟110期間，該DARC層208係使用氟化碳氣體來钱刻的（如，啤氟化破（C F 4)，六氟化硫（s F 6)，三IL 甲烧（CHF3)’二氟乙烧（CH2F2)，及類此者）。之後，該非晶型碳罩幕層2 2 6使用一蝕刻處理來加以蝕刻，該蝕刻處 200402779In an alternative embodiment, the window of the cover 2 1 2 is trimmed with a plasma, the electropolymer containing hydrogen bromide (HBr) at a flow rate of 3 to 200 sccm, and oxygen at 5 to 100 sccm (corresponding to Hbr: The flow rate ratio of 02 is 1:30 to 40: 1) and the flow rate of argon (Ar) is between 10 and 200 sccm. The plasma system uses a plasma power of 200 to about 2000W and a bias power of 0 to 30W. The temperature of the wafer tray is between 0 and 80 ° C and the chamber pressure is between 2 and 30mTorr. . An exemplary photoresist trimming process uses an HBr flow rate of 80 sccm, an O 2 flow rate of 2 8 sccm (ie, a flow rate ratio of Η B r: Ο 2 is about 2 5 · 1), and an Ar flow rate of 20 sccm. , 500W plasma power, 0W bias power, and 65 ° C wafer tray temperature at 4mTorr chamber pressure. In step 110, the pattern of the etch mask is transferred via the DARC layer 208 and the amorphous carbon mask layer 226 (FIG. 2E) to form a first mask 220. During step 110, the DARC layer 208 is engraved using a fluorinated carbon gas (eg, beer fluorination (CF 4), sulfur hexafluoride (s F 6), tri-IL methane (CHF 3) ' Fluoroethane (CH2F2), and the like). After that, the amorphous carbon cover layer 2 2 6 is etched using an etching process, and the etching place is 200402779

理包括一氣體（或氣體混合物），其包含了溴化氫（ΗΒγ)，氧氣（〇2)及至少一鈍氣，像是氬氣（Ar)，氦氣（He)，氖氣 (Ne)。在本文中，”氣體”及”氣體混合物，，等詞是可互換的。在一實射例中，步驟1 1 0使用光阻罩幕2 1 2作為一餘刻罩幕及該閘極電極層2 0 6作為一餘刻停止層《或者，該餘刻反應裔的一終點偵測系統可監看在一^特定波長的電漿發射用以決定該蝕刻處理的終點。又，步驟11 〇的兩個蝕刻處理都是在同一地被實施（即，在同一蝕刻反應室中實施）。在一舉例性的實施例中，包含氮氧化矽（si0N)的該 DARC層208係使用40至200sccm的四氟化碳（CF4)流率， 40至20sccm的氬氣（Ar)流率（即，CF4: Ar流率比為1:5 至5:1)，250W至75 0W的電漿功率，〇至300W的偏壓功率，且晶圓托盤溫度被保持在40至85 °C，室壓力被保持在2至lOmTorr來餘刻的。該DARC層208餘刻處理係藉由觀察在3865埃的電漿發射光譜的量來終止的，其在到達底下的非晶型碳罩幕層226且進行了約40%的過度蝕刻之後會顯著地下降（即，持續該蝕刻處理達會導致觀察到該發射光譜的量會有所改變的時間的40%)。一舉例性的氮氧化矽（SiON)DARC層208的蝕刻處理是在120sccm的四I化碳（CF4)流率，120sccm的氣氣（Ar) 流率（即，CF4:Ar流率比為1:1)，360W的電漿功率，60w 的偏壓功率，且晶圓e托盤溫度被保持在6 5 °C，室壓力被保持在4mTorr進行的。在一實施例中，該非晶型碳罩幕層226係使用20至 10 200402779 lOOsccm的溴化氫（HBr)流率，5至60sccm的氧氣（〇2)流率（即，HBr: Ο,流率比為1:3至2〇:1)，2〇至1〇sccm的氬氣（A〇流率，5 00W至1 500W的電漿功率，〇至30〇w的偏壓功率’且晶圓托盤溫度被保持在4 〇至8 5它，室壓力被保持在2至1 OmTorr來餘刻的。此處理具有至少2〇 : 1 的蝕刻方向性。本文中’’蝕刻方向性，，一詞被用來描述該非晶型碳層226於水平表面上與在垂直表面上（如側壁229) 被移除的飯刻率比❶在步驟丨丨〇期間，該蝕刻處理的高蝕刻方向性可保護光阻罩幕2 1 2的側壁229及非晶型碳罩幕層226不會受到側向的餘刻，因而可保持它們的尺寸。在步驟112，該光阻罩幕212從該基材上被去除（或剝除）（第2F圖）。大體上，步驟1丨2係使用傳統的光p旦剝除處理來實施，即其使用氧基的化學物，如包含氧及氮的氣體混合物。或者，步驟1 1 2可使用與在步驟丨丨〇中的# 晶型碳罩幕層226#刻所使用的相同氣體，且可在同刻反應器中實施。在步驟11 2期間，該蝕刻化學物及處理參數被特別選擇用以提供高蝕刻方向性來保持該非晶变碳罩幕層2 2 6的尺寸及位置。在一舉例性的實施例中，夕驟 110及112係使用DPS II模組在同一地方實施。一舉例性的光阻剝除處理係使用6〇sccm的溴化氫 (HBr)流率，至20 seem的氧氣（〇2)流率（即，HBr : 02流率比為3:1)，6 0sccm吟氬氣（Ar)流率，600W的電漿功率’ ioow的偏壓功率，且晶圓托盤溫度被保持在65。〇，室麈力被保持在4mTorr來實施的。此剝除處理具有至少1 〇 : 200402779 1的餘刻方向性，以及至少2〇 : 1之DARC層208(如，氮氧化砂）對光阻罩幕2 1 2的蝕刻選擇性。在步驟1 1 4，一第二罩幕2 1 4係使用一傳統的沉積技術’像是原子層沉積（ALD)，物理氣相沉積（PVD)，化學氣相沉積（CVD)，強化的CVD(PECVD)等技術，而被保形地沉積在該晶圓200上（第2G圖）。該第二罩幕214被沉積至一足以界定該閘極電極寬度的側壁厚度23 1。該第二罩幕214大體上是由氮化矽（Si3N4)，二氧化矽（si〇2)所形成。在步驟116，該第二罩幕214及DARC層208被蝕刻且從水平表面（即，分別從多晶矽層206與非晶型碳層226) 上被去除掉（第2H圖）。在步驟U6期間，該多晶矽層2〇6 亦被蝕刻至一深度2 0 3 (過度蝕刻）。在一實施例中，該第二罩幕214(如，氮化矽（Si3N4)) 係使用一包含了四氟化碳（CFO以及一鈍氣，像是氬氣 (A0 ’氦氣（He) ’氖氣（Ne)的氣體混合物而從該水平表面上被餘刻掉。此蝕刻處理可藉由提供4〇至〇〇sccm的四氟化碳（CF4)流率，40至200sccm的氬氣（Ar)流率，25〇w 至750W的電漿功率，〇至3〇〇w的偏壓功率，且晶圓托盤溫度被保持在40至85。(：，室壓力被保持在2至10mT〇rr 而在該DPS II模組中實施。該第二罩幕214蝕刻處理係藉由觀察在2880埃妁電漿發射光譜的量來終止的，其在到達底下的非晶型碳罩幕層2 2 6且進行了約2 〇〇 %的過度蝕刻之後會顯著地上升（即，持續該蝕刻處理達會導致觀 12 200402779 察到該發射光譜的量會有所改變的時間的200%)。一舉例性的第二罩幕214的蝕刻處理是在i20sccm 的四氟化碳（CF4)流率，120sccm的氬氣（Ar)流率，3 60W 的電漿功率，60W的偏壓功率，且晶圓托盤溫度被保持在65°C，室壓力被保持在4mTorr實施的。如在第21圖的頂視圖所示的，步驟116形成相鄰的壟起結構27〇及272。每一個結構27〇 , 272都具有前壁The process includes a gas (or gas mixture), which contains hydrogen bromide (ΗΒγ), oxygen (02), and at least one inert gas, such as argon (Ar), helium (He), and neon (Ne). . In this article, the terms "gas" and "gas mixture" are interchangeable. In a real shot example, step 1 10 uses a photoresist mask 2 1 2 as a spare mask and the gate electrode The layer 2 06 is used as a stop layer for a short period of time. Alternatively, an end point detection system of the remaining time can monitor the plasma emission at a specific wavelength to determine the end point of the etching process. Furthermore, step 11 〇 Both etch processes are performed in the same place (ie, in the same etch reaction chamber). In an exemplary embodiment, the DARC layer 208 containing silicon oxynitride (si0N) uses 40 to 200 sccm. Carbon tetrafluoride (CF4) flow rate, argon (Ar) flow rate of 40 to 20 sccm (ie, CF4: Ar flow rate ratio is 1: 5 to 5: 1), plasma power of 250W to 7500W, The bias power is from 0 to 300 W, and the wafer tray temperature is maintained at 40 to 85 ° C, and the chamber pressure is maintained at 2 to 10 mTorr for the rest of the time. The DARC layer 208 is processed by observation at 3865 angstroms. The amount of plasma emission spectrum is terminated, it will reach the underlying amorphous carbon cover layer 226 and after about 40% over-etching Landing drop (ie, continuing the etch process for 40% of the time that the amount of the emission spectrum is observed to change). An exemplary etch process for the silicon nitride oxide (SiON) DARC layer 208 is at 120 sccm Carbon tetrafluoride (CF4) flow rate, 120sccm gas (Ar) flow rate (ie, CF4: Ar flow rate ratio is 1: 1), plasma power of 360W, bias power of 60w, and wafer The temperature of the e-tray is maintained at 65 ° C, and the chamber pressure is maintained at 4 mTorr. In one embodiment, the amorphous carbon cover curtain layer 226 uses a flow rate of hydrogen bromide (HBr) of 20 to 10 200402779 lOOsccm. , 5 to 60 sccm of oxygen (〇2) flow rate (that is, HBr: 0, flow rate ratio of 1: 3 to 20: 1), 20 to 10 sccm of argon (Ao flow rate, 500W To a plasma power of 1500W, a bias power of 0 to 30W and the wafer tray temperature is maintained at 40 to 85, and the chamber pressure is maintained at 2 to 1 OmTorr for the rest of the time. This process has Etching directivity of at least 20: 1. The term `` etching directivity, '' as used herein, is used to describe the amorphous carbon layer 226 on a horizontal surface and on a vertical surface (such as sidewall 229). During the step, the high etching directivity of the etching process can protect the side wall 229 of the photoresist mask 2 2 and the amorphous carbon mask layer 226 from being subjected to lateral excess. So that their dimensions are maintained. At step 112, the photoresist mask 212 is removed (or peeled off) from the substrate (Figure 2F). Generally, steps 1 and 2 use conventional light p Once the stripping process is performed, it uses oxygen-based chemicals, such as a gas mixture containing oxygen and nitrogen. Alternatively, step 1 12 may use the same gas as that used for the # crystalline carbon cover curtain layer 226 # in step 丨丨〇, and may be implemented in a reactor at the same time. During step 112, the etching chemicals and processing parameters are specifically selected to provide high etching directivity to maintain the size and position of the amorphous carbon mask layer 2 2 6. In an exemplary embodiment, steps 110 and 112 are implemented in the same place using DPS II modules. An exemplary photoresist stripping process uses a hydrogen bromide (HBr) flow rate of 60 sccm to an oxygen (02) flow rate of 20 seem (ie, a HBr: 02 flow rate ratio of 3: 1), An argon (Ar) flow rate of 60 sccm, a plasma power of 600 W 'ioow's bias power, and the wafer tray temperature was maintained at 65. 〇, the chamber pressure was maintained at 4mTorr. This stripping process has a remaining directivity of at least 10: 200402779 1 and an etching selectivity of the DARC layer 208 (eg, oxynitride sand) of the photoresist mask 2 12 by at least 20: 1. In step 1 4, a second mask 2 1 4 uses a conventional deposition technique such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and enhanced CVD. (PECVD) and other techniques, and is deposited conformally on the wafer 200 (Figure 2G). The second mask 214 is deposited to a sidewall thickness 23 1 sufficient to define the width of the gate electrode. The second mask 214 is generally formed of silicon nitride (Si3N4) and silicon dioxide (si02). In step 116, the second mask 214 and the DARC layer 208 are etched and removed from the horizontal surface (ie, the polycrystalline silicon layer 206 and the amorphous carbon layer 226, respectively) (FIG. 2H). During step U6, the polycrystalline silicon layer 206 is also etched to a depth of 203 (over-etched). In one embodiment, the second mask 214 (eg, silicon nitride (Si3N4)) is made of carbon tetrafluoride (CFO) and a passivation gas, such as argon (A0 'helium (He) 'A gas mixture of neon (Ne) was left etched from the horizontal surface. This etching process can provide a flow rate of carbon tetrafluoride (CF4) from 40 to 00 sccm and argon from 40 to 200 sccm (Ar) flow rate, plasma power from 25w to 750W, bias power from 0 to 300w, and wafer tray temperature is maintained at 40 to 85. (:, chamber pressure is maintained at 2 to 10mT 〇rr and implemented in the DPS II module. The second mask 214 etching process was terminated by observing the amount of plasma emission spectrum at 2880 angstroms, which reached the amorphous carbon mask layer underneath. 2 2 6 and a significant increase after about 200% overetching (ie, continuing the etching process for 200% of the time when the amount of the emission spectrum observed by the observation 12 200402779 will be changed). An exemplary etching process of the second mask 214 is a carbon tetrafluoride (CF4) flow rate at i20sccm, an argon (Ar) flow rate at 120sccm, and a plasma power of 3 60W. Rate, a bias power of 60W, and the wafer tray temperature is maintained at 65 ° C, and the chamber pressure is maintained at 4mTorr. As shown in the top view of FIG. 21, step 116 forms an adjacent ridge structure 27〇 and 272. Each structure 27〇, 272 has a front wall

233 ’後壁235 ’及側壁237其都是由該第二罩幕層214 的垂直部分所構成。在步驟ιι6之後，該罩幕層以只留在結構270，272内部。The 233 ′ rear wall 235 ′ and the side wall 237 are both formed by the vertical portion of the second cover layer 214. After step 6 the mask layer is left inside the structures 270,272 only.

在步驟118,包含非B s并阳型碳的罩幕層226從結構270， 272上被去除掉（第閽圖）。結構270及272的前壁與後壁 233，23 5係以虛線23 “y不於第2J圖中。在一實施例中，步驟118可使用步驟〗 ^ 11 2中所用的剝除處理。在步驟 1 2 0，味 —第二圖案光阻罩幕240被形成在該晶圓200上（第2K圖）。火虽曝露出該結構270及272的研壁 233及後壁235時，今蓄吻罩幕240保護該結構270及272的侧壁2 3 7 (以虛線示出、印）的部分。罩幕240可使用一石版印刷圖案處理來形成，如如在上文中的步驟106中所述者。在步驟1 2 2，結構9 7 π 傅27〇及2 72被蝕刻且結構270及272 之沒有被保護的部分f g 刀（即’前壁23 3及後壁23 5)被去除掉 (第2 L圖）。在一 || 今W性的實施例中，步驟1 24係使用與步驟1 1 6相同的巍办丨+ ^處理來處理。步驟122使用罩幕24〇作為一餘刻罩幕且可 J使用該電極層 206作為一蝕刻停止 13 200402779 層。或者，側壁233及235的不想要部分可在多晶石夕間極 f和5如下所述地被形成之後被去除掉。在步驟124，罩幕240從基材上被剝除（第2M及2N 圖）留下多個形成在該閘極電極層206(如，多晶矽層）的第二罩幕242在通道區的上方，其為電晶體基面將被形成的所在之處《母一罩幕242的寬度都相應於將被界定在該閘極電極層206中的閘極的寬度。In step 118, the mask layer 226 containing non-B s and anodic carbon is removed from the structures 270, 272 (FIG. VII). The front and rear walls 233, 23 5 of the structures 270 and 272 are shown with a dashed line 23 "y in Fig. 2J. In one embodiment, step 118 may use the stripping process used in step ^ 11 2. Step 1 2 0. The taste-second pattern photoresist mask 240 is formed on the wafer 200 (Fig. 2K). Although the fire exposed the research wall 233 and the back wall 235 of the structures 270 and 272, the current storage The kiss mask 240 protects portions of the sidewalls 2 3 7 (shown in dashed lines, printed) of the structures 270 and 272. The mask 240 can be formed using a lithographic pattern process, as in step 106 above In step 1 2 2, the structure 9 7 π Fu 270 and 2 72 are etched and the unprotected parts of the structures 270 and 272 are fg knives (ie, 'front wall 23 3 and rear wall 23 5) are removed. (Fig. 2 L). In a modern embodiment, steps 1 to 24 are processed using the same processing as in steps 1 to 16. Step 122 uses the mask 24o as a more than one The mask can be engraved and the electrode layer 206 can be used as an etch stop 13 200402779 layer. Alternatively, the unwanted portions of the side walls 233 and 235 can be between polycrystalline silicon f and 5 After being formed as described below, it is removed. In step 124, the mask 240 is peeled from the substrate (Figures 2M and 2N), leaving a plurality of gate electrode layers 206 (eg, a polycrystalline silicon layer) formed thereon. The second mask 242 is above the channel area, which is where the base surface of the transistor will be formed. The width of the first mask 242 corresponds to the gate to be defined in the gate electrode layer 206. The width.

第二罩幕242保護閘極電極層206的區域241及拍露出層206的區域243及245。每一區域241都位在通道區 236以及將被製造之電晶體252或254的源極區與汲極區 232及234的上方。區域243與介於同一對電晶體（如，25〇或〇)的電Βθ體2 5 2及2 5 4的閘極結構之間的間隔有關。相同地，區域24 5與介於相鄰的電晶體對之間的間隔有關0 在步驟126，閘極電極層2〇6被蝕刻且在區域243及 245中被去除掉（第20圖）。因此，步驟126形成多個閘極電晶體216。一閘極電極216(如，多晶矽閘極電極）具有寬度215其&由第二罩幕242的寬度249所界定且位在個241區域中。因此，閘極電極2 1 6的寬度215是由罩幕層214的側壁厚度231所界定，其約為1()至5〇謂。 /驟2 1 6使用第_罩幕作為_钱刻罩幕且及使用閘極電極層2 0 4作為餘刻停止屬。 ^在一實施例中，步驟126係藉由提供一包含四氟化炭/臭化氫（HBr) ’氣（CD的氣體混合物而在Dps π反應 14 200402779The second mask 242 protects the region 241 of the gate electrode layer 206 and the regions 243 and 245 of the exposed layer 206. Each region 241 is located above the channel region 236 and the source and drain regions 232 and 234 of the transistor 252 or 254 to be manufactured. The region 243 is related to the interval between the gate structures of the electric Bθ bodies 2 5 2 and 2 5 4 of the same pair of transistors (eg, 25 or 0). Similarly, the region 24 5 is related to the interval between adjacent transistor pairs. In step 126, the gate electrode layer 206 is etched and removed in the regions 243 and 245 (Fig. 20). Accordingly, step 126 forms a plurality of gate transistors 216. A gate electrode 216 (e.g., a polysilicon gate electrode) has a width 215 and is defined by a width 249 of the second mask 242 and is located in a region 241. Therefore, the width 215 of the gate electrode 2 16 is defined by the thickness 231 of the sidewall of the mask layer 214, which is about 1 () to 50. / Step 2 1 6 Use the _ mask as the _ money carved mask and use the gate electrode layer 2 0 4 as the remaining stop. ^ In an embodiment, step 126 is performed at Dps π by providing a gas mixture containing carbon tetrafluoride / hydrogen odor (HBr) 'gas (CD) 14 200402779

器中實施的，且在氦中稀釋的氧（He-02)被用來蝕刻該多晶矽閘極電極層2 0 6。大體上，步驟1 2 6使用1 5至4 5 s c c m 流率的四氟化碳及15至150sccm流率的溴化氫（即，1:10 至3:1的CF4 : HBr流率比），以及30至90sccm流率的氯以及在6至18sccm流率下的70%的He及30%的02之混合物。又，步驟126施加300至1500W的電漿功率及40 至120W的偏壓功率，並在2至6mTorr的室壓力保持20 至8 0 °C的晶圓托盤溫度。一舉例性的處理提供3 5 s c c m流率的匸？4及125scc流率的HBr(即，約1:4的CF4:HBr 流率比），60sccm的氣，在8sccm流率下的70%的He及 3 0%的Ο:之混合物，600W的電漿功率及80W的偏壓功率，並在4mTon:的室壓力保持65它的晶圓托盤溫度。在步驟128第二罩幕242從該閘極電極216上被去除掉（第2P圖）。在一實施例中，步驟128使用傳統的熱磷酸（HJOJ蝕刻處理，其同步去除掉第二罩幕242以及姓刻處理步驟126的副產物（第2P圖）。在一實施例中，晶圓200被曝露在溫度約為16〇〇c的磷酸溶液中。在曝露之後，晶圓200在蒸餾水中被沖洗用以去除掉任何殘留的磷酸#刻劑。此填酸姓刻處理可使用，如一自動化的濕式清洗模組來實施，該自動化模組被描述在2〇〇 i年八月3 i曰提申之美國專利申請案第09/945,454號中，該案内容藉由此參照而被併於本Λ中。此濕式清洗模組可由設在美國加州 Santa Clara 市的 Applied Material 公司購得。在步驟130, 一在該閘極電極216底下的閘極介電質 15 200402779 247被#刻（第2Q圖）。為了要閘極電指可使用描述於2002年七月12日提申的 10/1 94,566號中的蝕刻處理，或其它適層物質且對於閘極電極216與基材2〇〇的蝕刻處理。方法100在步驟132處終止。可用來實施本發明的蝕刻步驟的一性實施例被示於第3圖中。第3圖顯示可被用來實施本發明的刻反應器300的示意圖。處理室包天線段3 1 2 ’其位在一介電質室天花板的變化可具有其它種類的天花板，如圓線段312被耦合至一射頻（RF)源318 50kHz至13·56ΜΗζ的可調式頻率之rf 經由一配接網絡3 1 9被耦合至該天線3 包括一晶圓支撐托盤（陰極）316其耦# 13·56ΜΗζ頻率的RF訊號的rf源322c 配接網絡3 2 4被耦合至該陰極3 1 6。非t 可以是一 DC或脈衝式DC源。室310 330其被連接至一地極334。一包含中央, 一記憶體342，及該CPU344的支援電路被耦合至該DPS蝕轉處理室310的不蚀刻處理。在操作時，半導體晶圓3 1 4被放在該 &層204，步驟13〇美國專利申請案第合钱刻該閘極介電具有高餘刻選擇性钱刻範應器的舉例方法之DPS II蝕含至少一電感線圈 3 20的外部。其它頂形天花板。該天其能夠產生具有約訊號。該RF源318 1 2。處理室2 1 0亦卜至一能夠產生約 > RF源3 22經由一公要地，RF源322 亦包含一導電室壁處理器（CPU)344， 346的控制器340 同構件用以控制該晶圓支撐托盤3 1 6 16 200402779 ，.·** v-，“ f V" *»·‘* 上且氣體成份從一氣體板338經由入口埠326被供應至該處理室3 1 0用以形成一氣體混合物3 5 0。該氣體混合物3 5 0 在該處理室3 1 0中利用來自於RF源3 1 8及3 2 2分別透過天線3 1 2及陰極3 1 6施加的RF功率而被點燃成為電製 355。在該餘刻室310内部的壓力係使用位在室210與一真空幫浦3 3 6之間的節流閥3 2 7來控制。在室壁3 3 0的表面處的溫度係使用位在室310的壁330中之内含液體的管子（未示出）來控制。晶圓3 1 4的溫度係藉由讓氦氣從來源3 4 8流到由晶圓 314的背面與支撐托盤表面上的溝槽（未示出）所構成的通道中來穩定該支撐托盤316的溫度來達成的。氦氣被用來促進托盤3 1 6與晶圓3 1 4之間的熱傳遞。在處理期間，晶圓314被托盤内的電阻式加熱器加熱至一穩態溫度且氦氣可促進晶圓314的均勻加熱。藉由使用天花板32〇與托盤 3 16兩者的熱控制，晶圓314被保持在介於〇至500的溫度之間。被施加至該電感線圈天線3 1 2的RF功率具有介於50kHz至13·56ΜΗζ的頻率及具有200至3000W的功率^ 0至300W的偏壓功率被施加至該托盤316，其可為DC，脈衝式DC，或rf功率。為了要如上所述地控制該室，該CPU344可以是能夠被用在一工業§曼施上用來控制不同的室及副處理器之任何形式的一般用途的電®處理器。該記憶體3 4 2被耦合至該 CPU344。該記憶體342，或電腦可讀取的媒體，可以是一或多種現有的記憶體，如隨機存取記憶體（RAm)，唯讀 17 200402779 記憶體（ROM)，軟碟機，硬碟機，或任何其它形式的，遠端的或本地的數位貯存。支援電路346被輕合至該CPU344 用以用傳統的方式來支援該處理器。這些電路包括，快取 (cache)，電源供應，時脈電路，輸入/輸出電路及子系統，及類此者。本發明的方法大體上被儲存在記憶體342中成為軟體常式。該軟體常式亦可被儲存及/或一第二CPU(未示出）所執行，該第二CPU可位在遠離CPU3 44所控制的硬體的地方。 Φ 本發明可用其它半導體晶圓處理系統來實施，其中熟悉此技藝者可藉由利用本案所揭示之不偏離本發明的精神的教導來調整處理參數用以達成可被接受的特性。雖然以上的說明係以場效電晶體的製造為例來描述’ 但使用在積體電路中的其它元件及結構的製造亦可由本發明的揭示受惠。雖然以上所述係關於本發明的舉例性實施例’但本發明之其它及進一步的實施例可在不偏離本發明的基本範 _ 圍’及由以下的申請專利範圍所界定的範園之為被完成。【圖式簡單說明】本發明的教導可藉由閱讀以下參照了附圖的詳細說明而更容易瞭解，其中：第1 A及1 B圖顯示依據本發明的一場效電晶體的閘極結構的製造方法的流程；第2A-2Q圖顯示一基材的示意，剖面及頂視圖’該 18 200402779 基材具有依據第1 A-1 B圖的方法所製造的閘極結構；及第3圖顯示一可用來實施本發明的方法的一舉例性電漿處理設備的示意圖。為了要便於瞭解，相同的標號被用來標示在各圖中之相同的元件。然而，應被暸解的是，附圖只是示出本發明的舉例性實施例，其不應被視為範圍的限制，本發明仍有許多等效的實施例。Oxygen (He-02), which is implemented in a reactor and diluted in helium, is used to etch the polysilicon gate electrode layer 206. Generally, steps 1 2 6 use carbon tetrafluoride at a flow rate of 15 to 45 sccm and hydrogen bromide at a flow rate of 15 to 150 sccm (ie, a CF4: HBr flow rate ratio of 1:10 to 3: 1), And a mixture of chlorine at a flow rate of 30 to 90 sccm and 70% He and 30% 02 at a flow rate of 6 to 18 sccm. In addition, step 126 applies a plasma power of 300 to 1500 W and a bias power of 40 to 120 W, and maintains a wafer tray temperature of 20 to 80 ° C at a chamber pressure of 2 to 6 mTorr. An exemplary treatment provides a flow rate of 3 5 s c c m? 4 and 125 scc flow rate HBr (ie, CF4: HBr flow rate ratio of about 1: 4), 60 sccm gas, 70% He and 30% 0: mixture at 8 sccm flow rate, 600 W electricity The pulp power and the bias power of 80W are maintained at a chamber pressure of 65m at a wafer tray temperature of 4mTon :. The second mask 242 is removed from the gate electrode 216 in step 128 (Fig. 2P). In one embodiment, step 128 uses a conventional thermal phosphoric acid (HJOJ etching process, which simultaneously removes the second mask 242 and the by-products of the engraving process step 126 (FIG. 2P). In one embodiment, the wafer 200 is exposed to a phosphoric acid solution at a temperature of about 160 ° C. After the exposure, wafer 200 is rinsed in distilled water to remove any remaining phosphoric acid #etching agent. This acid filling treatment can be used, such as An automated wet cleaning module is implemented, which is described in U.S. Patent Application No. 09 / 945,454 filed on August 3, 2000, the contents of which are hereby incorporated by reference This wet cleaning module can be purchased from Applied Material Company located in Santa Clara, California, USA. At step 130, a gate dielectric 15 under the gate electrode 216 15 200402779 247 被 # Engraved (Figure 2Q). In order to obtain the gate electrode, the etching process described in No. 10/1 94,566, filed on July 12, 2002, or other suitable layer materials for the gate electrode 216 and the substrate can be used. 200。 Etching process. Method 100 in step 132 Termination. An example of an etching step that can be used to implement the present invention is shown in Figure 3. Figure 3 shows a schematic view of an etch reactor 300 that can be used to implement the present invention. Processing chamber package antenna section 3 1 2 'The change in the ceiling of a dielectric chamber can have other types of ceilings, such as a circular line segment 312 coupled to a radio frequency (RF) source 318 adjustable frequency rf of 50kHz to 13.56MΗζ via a patch network 3 1 9 is coupled to the antenna 3 includes a wafer support tray (cathode) 316 and an RF source 322c coupled to the RF signal of the frequency of 13.56 MHz, 322c. The mating network 3 2 4 is coupled to the cathode 3 1 6. Non-t can It is a DC or pulsed DC source. Chamber 310 330 is connected to a ground pole 334. A support circuit including a center, a memory 342, and the CPU 344 is coupled to the non-etching process of the DPS erosion processing chamber 310 In operation, a semiconductor wafer 3 1 4 is placed on the & layer 204, step 130. The US patent application No. 30 is engraved. The gate dielectric has a high-etch selectivity engraved application. The DPS II etches the outside of the coil containing at least one inductor 3. 20 The ceiling-shaped ceiling. It can generate a signal with a signal on that day. The RF source 318 1 2. The processing chamber 2 1 0 can also generate a signal > The RF source 3 22 passes through a common ground, and the RF source 322 also contains a The controller 340 of the conductive chamber wall processor (CPU) 344, 346 and the same component are used to control the wafer support tray. 3 1 6 16 200402779, .. ** v-, "f V " *» · '* and gas Ingredients are supplied from a gas plate 338 to the processing chamber 3 1 0 through an inlet port 326 to form a gas mixture 3 5 0. The gas mixture 3 50 is ignited into an electric system 355 in the processing chamber 3 10 using RF power applied from the RF sources 3 1 8 and 3 2 2 through the antenna 3 12 and the cathode 3 1 6 respectively. The pressure inside the remaining chamber 310 is controlled using a throttle valve 3 2 7 located between the chamber 210 and a vacuum pump 3 3 6. The temperature at the surface of the chamber wall 3 3 0 is controlled using a liquid-containing tube (not shown) located in the wall 330 of the chamber 310. The temperature of wafer 3 1 4 stabilizes the support tray 316 by allowing helium to flow from source 3 4 8 into a channel formed by the back of wafer 314 and a groove (not shown) on the surface of the support tray. Temperature to reach. Helium is used to promote heat transfer between the tray 3 1 6 and the wafer 3 1 4. During processing, the wafer 314 is heated to a steady state temperature by a resistive heater in the tray and helium can promote uniform heating of the wafer 314. By using thermal control of both the ceiling 32 and the tray 3 16, the wafer 314 is maintained at a temperature between 0 and 500. The RF power applied to the inductive coil antenna 3 1 2 has a frequency between 50 kHz and 13.56 MHz and a bias power of 200 to 3000 W ^ 0 to 300 W is applied to the tray 316, which may be DC, Pulsed DC, or rf power. In order to control the chamber as described above, the CPU 344 may be any form of general-purpose electrical processor that can be used in an industry to control different chambers and sub-processors. The memory 3 4 2 is coupled to the CPU 344. The memory 342, or a computer-readable medium, may be one or more existing memories, such as random access memory (RAm), read-only 17 200402779 memory (ROM), floppy disk drive, hard disk drive , Or any other form of remote or local digital storage. The support circuit 346 is closed to the CPU 344 to support the processor in a conventional manner. These circuits include caches, power supplies, clock circuits, input / output circuits and subsystems, and the like. The method of the present invention is generally stored in the memory 342 as a software routine. The software routine may also be stored and / or executed by a second CPU (not shown), which may be located away from the hardware controlled by the CPU 344. Φ The present invention can be implemented with other semiconductor wafer processing systems, wherein those skilled in the art can adjust processing parameters to achieve acceptable characteristics by using the teachings disclosed in this case without departing from the spirit of the present invention. Although the above description is described by taking the manufacture of field effect transistors as an example ', the manufacture of other components and structures used in integrated circuits can also benefit from the disclosure of the present invention. Although the above is about the exemplary embodiments of the present invention, but other and further embodiments of the present invention can be made without departing from the basic scope of the present invention and the scope of the scope defined by the scope of the following patent applications: Was completed. [Brief description of the drawings] The teachings of the present invention can be more easily understood by reading the following detailed description with reference to the drawings, wherein: Figures 1A and 1B show the gate structure of a field effect transistor according to the present invention. Manufacturing process flow; Figures 2A-2Q show a schematic, section and top view of a substrate 'The 18 200402779 substrate has a gate structure manufactured according to the method of Figures 1 A-1 B; and Figure 3 shows A schematic diagram of an exemplary plasma processing apparatus that can be used to implement the method of the present invention. For ease of understanding, the same reference numerals are used to identify the same elements in the drawings. It should be understood, however, that the drawings are merely illustrative embodiments of the invention and should not be construed as limiting the scope, as there are still many equivalent embodiments of the invention.

【元件代表符號簡單說明】 100 處理程序 200 晶圓 202 閘極電極堆疊 232 汲極區 (井） 234 源極區 (井） 236 通道區 204 介電層 206 閘極電極層 226 第一罩幕層 208 抗反射塗層 (DARC) 212 第一圖案光阻罩幕 221 區域 207 線寬 209 空間 214 節距 25 2, 254 電晶體 250 閘極對 22 3 區域 213 空間 219 間隔 260 閘極對 229 側壁 27 0, 272 壟起結構， 237 側壁 233 前壁 235 厚壁 239 虛線 240 第圖案光阻罩幕 19 第二罩幕閘極電極寬度閘極電介質處理室介電質天花板晶圓支撐托盤（陰極）配接網絡控制器記憶體半導體晶圓入口埠電漿節流閥氦氣來源 24 1, 243, 245 區域 215 寬度 231 侧壁厚度 3 0 0 蝕刻反應器 312 電感線圈天線段 318 射頻（RF)源 322 RF 源 3 34 地極 344 中央處理器（CPU) 346 支援電路 3 38 氣體板 35 0 氣體混合物 3 3 0 室壁 33 6 真空幫浦[Simple description of component representative symbols] 100 processing program 200 wafer 202 gate electrode stack 232 drain region (well) 234 source region (well) 236 channel region 204 dielectric layer 206 gate electrode layer 226 first mask layer 208 Anti-reflective coating (DARC) 212 First pattern photoresist curtain 221 Area 207 Line width 209 Space 214 Pitch 25 2, 254 Transistor 250 Gate pair 22 3 Region 213 Space 219 Interval 260 Gate pair 229 Side wall 27 0, 272 Ridge structure, 237 Side wall 233 Front wall 235 Thick wall 239 Dotted line 240 First pattern photoresist curtain 19 Second curtain gate electrode width Gate dielectric processing chamber dielectric ceiling wafer support tray (cathode) Connected to the network controller memory Semiconductor wafer inlet port Plasma throttle valve Helium source 24 1, 243, 245 Area 215 Width 231 Side wall thickness 3 0 0 Etching reactor 312 Inductor coil antenna section 318 Radio frequency (RF) source 322 RF source 3 34 Ground 344 CPU ( CPU) 346 Support circuit 3 38 Gas plate 35 0 Gas mixture 3 3 0 Chamber wall 33 6 Vacuum pump

Claims

200402779 Patent application scope 1 · A method for defining a characteristic structure on a substrate, the method at least includes: (a) providing a substrate having a material layer formed thereon; (b) forming a first A mask on the material layer; (c) forming a second mask on one or more side walls of the first mask;

(d) removing the first mask; and (e) using a second mask to etch the material layer to define at least one feature structure thereon. 2. The method according to item 1 of the scope of patent application, wherein step (b) further comprises: (bl) depositing a first mask layer on the material layer; (b2) forming a photoresist pattern on the first On the mask layer; (b3) transferring the photoresist pattern through the first mask layer to form the first mask; and (b4) removing the photoresist pattern from the substrate. 3. The method according to item 1 of the scope of patent application, wherein the first mask comprises at least one of a dielectric anti-radiation coating (DARC) and an amorphous carbon layer. twenty one

200402779 4. The method according to item 1 of the scope of patent application, comprising: (cl) conformally placing a second cover on the first cover; (c2) placing the second cover layer on the first A horizontal surface of a curtain falls off a horizontal surface that is aligned with the side wall of the first curtain; (c3) forming a photoresist pattern on the quilt of the second curtain, exposing the conformal deposit on the ground The first area of the second cover on one of the covers; (c4) removing the first area of the two cover layers on one or more side walls of the first cover; and (c5) removing the photoresist The pattern is removed. 5. The method according to item 1 of the scope of patent application, which comprises a substance selected from the group consisting of silicon dioxide (Si 02) and nitrogen. 6. The method according to item 1 of the scope of patent application, wherein the material layer on the material comprises polycrystalline wheat. 7. A method for manufacturing a gate structure of a field effect transistor includes: step (c) further cladding is deposited on the surface and a selected area is removed from a base portion or a plurality of second and second side walls are exposed. Mask silicon (Si3N4) is formed on the substrate, and the method to 22 200402779 (a) provides a substrate having a gate electrode layer formed on a gate dielectric layer; (b) forming a first A mask on the area of the gate electrode layer; (c) forming a second mask on one or more side walls of the first mask; (d) removing the first mask; and

(d) Etching the gate electrode layer and the gate dielectric layer by using the second mask as an etching mask to complete the gate structure. 8. The method according to item 7 of the scope of patent application, wherein step (b) further comprises: (b 1) depositing a first mask layer on the gate electrode layer; (b2) forming a photoresist pattern on On the first mask layer; (b3) transferring the photoresist pattern through the first mask layer to form the first mask; and

(b4) removing the photoresist pattern from the substrate. 9. The method according to item 7 of the scope of patent application, wherein the first mask comprises at least one of a dielectric anti-reflection coating (DARC) and an amorphous carbon layer. -i; 1 10. The method as described in item 7 of the scope of patent application, wherein step (c) further comprises: 23 200402779 (cl) conformally depositing a second cover layer on the first cover (C2) removing the portion of the second cover layer on the horizontal surface of the first cover and on the horizontal surface of the substrate adjacent to the side wall of the first cover;

(c3) forming a photoresist pattern on a selected area of the second mask, exposing a first region of the second mask that is conformally deposited on one or more side walls of the ground mask; (c4) removing the first area of the second mask layer exposed on one or more side walls of the first mask; and (c5) removing the photoresist pattern. 1 1. The method according to item 7 of the scope of patent application, wherein the second mask contains a substance selected from the group consisting of silicon dioxide (Si02) and silicon nitride (Si3N4).

12. The method according to item 7 of the scope of patent application, wherein the gate dielectric layer comprises a polycrystalline dream. 1 3. A method of manufacturing a field effect transistor on a substrate, the method at least comprising: '(a) providing a substrate having a gate electrode layer formed on a gate dielectric layer; 24 200402779 (b) forming a first mask on the area of the gate electrode layer; (c) forming a second mask on one or more side walls of the first mask; (d) removing the first mask A mask; and (d) using the second mask as an etching mask to etch the gate electrode layer and the gate dielectric layer to complete the gate structure.

14. The method according to item 13 of the scope of patent application, wherein step (b) further comprises: (bl) depositing a first mask layer on the gate electrode layer; (b2) forming a photoresist pattern on On the first mask layer; (b3) transferring the photoresist pattern through the first mask layer to form the first mask; and (b4) removing the photoresist pattern from the substrate .

1 5. The method as described in item 13 of the scope of the patent application, wherein the first mask comprises at least one of a dielectric anti-reflection coating (DARC) and an amorphous carbon layer. 16. The method as described in item 13 of the scope of patent application, wherein step (c) further comprises: ~ (cl) conformally depositing a second mask layer on the first mask 25 200402779 (c2) removing the part of the second cover layer on the horizontal surface of the first cover and the horizontal surface of the substrate adjacent to the side wall of the first cover; (c 3) forming a A photoresist pattern over a selected region of the second mask, exposing a first region of the second mask that is conformally deposited on one or more side walls of the first mask;

(c4) removing the first area of the second mask layer exposed on one or more side walls of the first mask; and (c5) removing the photoresist pattern. 1 7. The method as described in item 13 of the scope of patent application, wherein the second mask contains a substance selected from the group consisting of silicon dioxide (Si02) and silicon nitride (Si3N4) .

18. The method as described in item 13 of the scope of patent application, wherein the gate dielectric layer comprises polycrystalline silicon. 26