CN102646583B - A kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall - Google Patents
A kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall Download PDFInfo
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- CN102646583B CN102646583B CN201210098261.2A CN201210098261A CN102646583B CN 102646583 B CN102646583 B CN 102646583B CN 201210098261 A CN201210098261 A CN 201210098261A CN 102646583 B CN102646583 B CN 102646583B
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Abstract
The invention provides and a kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall, first ion is injected to the silicon substrate with the pre-prepared structure of grid and form shallow junction, in the P type that grid is arranged on silicon substrate or N-type well region, between the pre-prepared structure of grid and silicon substrate, be also provided with gate oxide layers.At O
2prepare shaping grid under atmosphere, remove the gate oxide exposed in surface of silicon pickup and the shaping gate process of preparation.At surface of silicon and gate surface deposit first side wall layer and the second side wall layer, etching formation first side wall and the second side wall are carried out to side wall.
Description
Technical field
The present invention relates to a kind of cmos semiconductor device integration process, particularly relate to and a kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall.
Background technology
Chinese patent CN101593686A discloses a kind of integrated technique preparing metal gates, adopts amorphous carbon as can sacrificial gate material, forms the basal body structure needed for Gate-last technique.Concrete technology flow process comprises: in substrate, form gate dielectric layer; Described gate dielectric layer forms patterned amorphous carbon layer; Form the side wall around described patterned amorphous carbon layer; Form the interlayer dielectric layer covering described patterned amorphous carbon layer and side wall; Interlayer dielectric layer described in planarization also exposes described patterned amorphous carbon layer; Adopt oxygen ashing process to remove described patterned amorphous carbon layer, in described interlayer dielectric layer, form groove; Formed and fill described groove and the metal level covering described interlayer dielectric layer.
The flow process that above-mentioned patent provides is very simple, therefore needs to carry out refinement to a lot of processes wherein, such as: the laminated construction before grid is shaping; Sacrifice the pre-treatment that grid is shaping; Sacrifice the reprocessing of grid; The formation process of conventional sidewall structure; The preparation of matrix during ion implantation technology; The process of SPT technique; CESL process; CMP pre-treatment etc.
Summary of the invention
The present invention is directed to Chinese patent CN101593686A to provide in the integrated technique preparing metal gates and have problems, further refinement process wherein.
To achieve these goals, the invention provides and a kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall, comprise following sequential steps:
Step 1, ion is injected to the silicon substrate with the pre-prepared structure of grid and forms shallow junction, in the P type that described grid is arranged on silicon substrate or N-type well region, the pre-prepared structure of described grid is amorphous carbon material, is also provided with gate oxide layers between the pre-prepared structure of described grid and silicon substrate.
Step 2, at O
2prepare shaping grid under atmosphere, remove the gate oxide exposed in surface of silicon pickup and the shaping gate process of preparation.
Step 3, at surface of silicon and gate surface deposit first side wall layer and the second side wall layer successively.
Step 4, carries out etching formation first side wall and the second side wall to side wall.
In a preferred embodiment provided by the invention, the first side wall is oxide material.
In a preferred embodiment provided by the invention, the second side wall is silicon nitride material.
In a preferred embodiment provided by the invention, formed in shallow junction process, in P type trap zone, the pre-prepared structure of grid selects N-type ion doping, and in N-type well region, the pre-prepared structure of grid selects P type ion doping.
In a preferred embodiment provided by the invention, when carrying out N-type ion doping, block with photoresist N-type well region and on the pre-prepared structure of grid; When carrying out P type ion doping, block with photoresist P type trap zone and on the pre-prepared structure of grid.
In a preferred embodiment provided by the invention, described first side wall layer and the second side wall layer adopt dry etching to form the first side wall and the second side wall.
Preparation method provided by the invention in detail, specialized shallow junction (LDD) in Chinese patent CN101593686A and side wall technique.
Accompanying drawing explanation
Fig. 1 prepares the amorphous carbon sacrificial gate electrode structure with shallow junction and side wall by the present invention.
Fig. 2 is that intermediate ion of the present invention injects the device architecture schematic diagram after forming shallow junction.
Fig. 3 is the device architecture schematic diagram after preparing shaping grid in the present invention.
Fig. 4 is the device architecture schematic diagram after removing unnecessary pickup and gate oxide in the present invention.
Fig. 5 is the device architecture schematic diagram in the present invention after deposit first side wall layer and the second side wall layer.
Fig. 6 is the superficial view structural representation after forming the first side wall and the second side wall in the present invention.
Embodiment
The invention provides and a kind ofly prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and the method for side wall, first ion is injected to the silicon substrate with the pre-prepared structure of grid and form shallow junction, in the P type that grid is arranged on silicon substrate or N-type well region, between the pre-prepared structure of grid and silicon substrate, be also provided with gate oxide layers.At O
2prepare shaping grid under atmosphere, remove the gate oxide exposed in surface of silicon pickup and the shaping gate process of preparation.At surface of silicon and gate surface deposit first side wall layer and the second side wall layer successively, etching formation first side wall and the second side wall are carried out to side wall.
By the following examples the method for the shallow junction and side wall of preparing amorphous carbon sacrificial gate electrode structure provided by the invention is described in further details; better to understand the content of the invention, but the content of embodiment does not limit the protection range of the invention.
Select the silicon substrate 1 with the pre-prepared structure 31 of grid, the pre-prepared structure 31 of grid is amorphous carbon material, between the pre-prepared structure 31 of grid and silicon substrate 1, be also provided with gate oxide layers 5, the silicon substrate under the pre-prepared structure 31 of grid has P type or N-type well region.
As shown in Figure 2, first injecting in ion formation shallow junction 41,42, Fig. 2 to the silicon substrate 1 with the pre-prepared structure 31 of grid is N-type well region.
As shown in Figures 3 and 4, at O
2prepare shaping grid 3 under atmosphere, the size of sacrificing grid is narrowed down to designed size.Adopt the pickup staying surface of silicon in shaping grid 3 process of wet etching removing preparation and the gate oxide 5 exposed in shaping grid 3 process of preparation.
As illustrated in Figures 5 and 6, at surface of silicon 1 and grid 3 surface the first side wall layer 6 of deposited oxide and the second side wall layer 7 of silicon nitride successively.Employing dry etching is carved to the two-layer side wall that deposit is formed, and forms the first side wall and the second side wall.
Prepare as shown in Figure 1 there is the amorphous carbon sacrificial gate electrode structure of shallow junction and side wall time, in formation shallow junction process, in P type trap zone, the pre-prepared structure of grid selects N-type ion doping, and in N-type well region, the pre-prepared structure of grid selects P type ion doping.When carrying out N-type ion doping, block with photoresist N-type well region and on the pre-prepared structure of grid; When carrying out P type ion doping, block with photoresist P type trap zone and on the pre-prepared structure of grid.21 be N-type well region, 22 be P type trap zone in Fig. 1,9 for STI.
In basal body structure of the present invention, it is all large than desired value a certain amount of that the size (width and height) of sacrificing grid makes.After formation shallow junction, at O
2under atmosphere, the size of sacrificing grid is changed to desired value.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (6)
1. prepare the shallow junction of amorphous carbon sacrificial gate electrode structure and a method for side wall, it is characterized in that, comprise following sequential steps:
Step 1, ion is injected to the silicon substrate with the pre-prepared structure of grid and forms shallow junction, the pre-prepared vibrational power flow of described grid is in the P type or N-type well region of silicon substrate, and the pre-prepared structure of described grid is amorphous carbon material, is also provided with gate oxide layers between the pre-prepared structure of described grid and silicon substrate;
Step 2, at O
2described amorphous carbon sacrificial gate electrode structure is prepared under atmosphere, the size of pre-prepared for described grid structure to be narrowed down to the size needed for described amorphous carbon sacrificial gate electrode structure, and remove the gate oxide exposed in surface of silicon pickup and the described amorphous carbon sacrificial gate electrode structure process of preparation;
Step 3, at surface of silicon and gate surface deposit first side wall layer and the second side wall layer successively;
Step 4, carries out etching formation first side wall and the second side wall to side wall.
2. method according to claim 1, is characterized in that, described first side wall is oxide material.
3. method according to claim 1, is characterized in that, described second side wall is silicon nitride material.
4. method according to claim 1, is characterized in that, in described formation shallow junction process, in P type trap zone, the pre-prepared structure of grid selects N-type ion doping, and in N-type well region, the pre-prepared structure of grid selects P type ion doping.
5. method according to claim 1, is characterized in that, when carrying out N-type ion doping, block with photoresist N-type well region and on the pre-prepared structure of grid; When carrying out P type ion doping, block with photoresist P type trap zone and on the pre-prepared structure of grid.
6. method according to claim 1, is characterized in that, described first side wall layer and the second side wall layer adopt dry etching to form the first side wall and the second side wall.
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| CN101593686B (en) * | 2008-05-30 | 2011-10-05 | 中芯国际集成电路制造(北京)有限公司 | Metal grid forming method |
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| US6924191B2 (en) * | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method for fabricating a gate structure of a field effect transistor |
| CN101197282A (en) * | 2006-12-04 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
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