TW201537691A - Memory device and method for fabricating the same - Google Patents

Abstract

Provided is a method for fabricating a memory device. A first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer, a buffer layer and a first dielectric layer are formed on the substrate. A portion of the first dielectric layer, a portion of the buffer layer, a portion of the first conductive layer and a portion of the second gate dielectric layer on the substrate in the second region are removed. A third gate dielectric layer and a second conductive layer are formed on the substrate in the second region. The buffer layer is removed. A third conductive layer and a second gate dielectric layer are formed on the substrate. Isolations are penetrated through the second dielectric layer and into the substrate so as to be formed in the substrate. A memory device is also provided.

Description

Memory element and method of manufacturing same

The present invention relates to a memory element and a method of fabricating the same, and more particularly to a non-volatile memory element and method of fabricating the same.

Memory can be divided into two types: volatile memory (Volatile Memory) and non-volatile memory (Non-Volatile Memory). Volatile memory will disappear after the power supply is interrupted. The non-volatile memory will not disappear after the power supply is interrupted. After re-powering, it will be able to Read the data in the memory. Therefore, non-volatile memory can be widely used in electronic products, especially portable products.

However, in order to reduce the cost and simplify the process steps of semiconductor components, it has become a trend to integrate components of the Cell Region and the Periphery Region on the same wafer. The Triple Gate Oxide process is one of the ways to integrate the two on the same wafer.

At present, the triple oxide layer can be implanted with nitrogen (Nitrogen Implantation) The method is formed to delay the formation of yttrium oxide by nitrogen, thereby controlling the rate of yttrium oxide formation to form oxide layers of different thicknesses. Although the growth of cerium oxide by the furnace tube oxidation method can be effectively suppressed by nitrogen implantation, the growth rate of the furnace tube oxidation method is too slow. If the wet oxidation process is used to grow cerium oxide, nitrogen implantation cannot effectively inhibit the growth rate of cerium oxide.

The present invention provides a memory element and a method of manufacturing the same, which can simplify the process and reduce the production cost.

The present invention provides a method of fabricating a memory device comprising providing a substrate having a first region, a second region, and a third region. Next, a first gate dielectric layer is formed on the substrate of the first region. A second gate dielectric layer is formed on the substrates of the second region and the third region. The first conductor layer and the first dielectric layer are sequentially formed on the substrate. A first isolation structure is formed between the first region and the third region and extends through the first dielectric layer and into the substrate. A buffer layer is formed on the substrate. Then, the buffer layer of the third region, the first dielectric layer, the first conductor layer, and the second gate dielectric layer are sequentially removed to expose the surface of the substrate. A third gate dielectric layer is formed on the substrate of the third region. A second conductor layer and a second dielectric layer are sequentially formed on the substrate. A plurality of trenches are formed in the second dielectric layer, the second conductor layer, the third gate dielectric layer, and the substrate in the third region. A plurality of second isolation structures are formed on the substrate of the third region, and the second isolation structure fills the trenches. Thereafter, the buffer layers of the first zone and the second zone are removed.

The invention provides a memory element, comprising a substrate, a first gate structure, a second gate structure, a third conductor layer, a third gate dielectric layer, a first isolation structure, a plurality of second isolation structures, and a third isolation structure. The substrate has a first zone, a second zone, and a third zone. The first gate structure is located on the substrate of the first region, wherein the first gate structure comprises: the first gate dielectric layer is on the substrate of the first region; and the first conductor layer is located on the first gate dielectric layer. The second gate structure is located on the substrate of the second region, wherein the second gate structure comprises: the second gate dielectric layer is on the substrate of the second region; and the second conductor layer is located on the second gate dielectric layer. The third conductor layer is on the substrate of the third zone. The third gate dielectric layer is located between the substrate of the third region and the third conductor layer, wherein the thickness of the third conductor layer is greater than the thickness of the first conductor layer, and the thickness of the third conductor layer is greater than the thickness of the second conductor layer. The first isolation structure is located in the substrate between the third zone and the first zone. A plurality of second isolation structures are located in the substrate of the third zone. The third isolation structure covers a portion of the first isolation structure, and the bottom of the third isolation structure is stepped.

The present invention further provides a method of fabricating a memory device, comprising providing a substrate having a first region, a second region, and a third region. Next, a first gate dielectric layer is formed on the substrate of the first region. A second gate dielectric layer is formed on the substrates of the second region and the third region. Forming a first conductor layer, a buffer layer, and a first dielectric layer on the substrate. Then, a portion of the first dielectric layer, a portion of the buffer layer, a portion of the first conductor layer, and a portion of the second gate dielectric layer of the second region are removed to expose the surface of the substrate. Forming a third gate dielectric layer and a second conductor layer on the substrate of the second region. After that, remove the buffer layer. A third conductor layer and a second dielectric layer are sequentially formed on the substrate. A plurality of isolation structures are formed in the substrate, wherein a plurality of isolation structures extend through the second dielectric layer into the substrate.

In summary, the present invention provides a memory device and a method of fabricating the same that utilizes a triple gate oxide process to integrate components of a cell region and a peripheral region on a same wafer. The triple gate oxide process can be compatible with existing high quality wet oxidation processes to increase the rate of formation of high quality yttrium oxide and speed up the overall memory device process to reduce production costs and simplify process efficiency.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧First isolation structure

12, 16, 126, 126c‧‧ ‧ cover layer

14, 14a, 14b, 18, 19‧‧‧ Ditch

20‧‧‧Second isolation structure

30‧‧‧ Third isolation structure

40, 50, 490‧‧ ‧ isolation structure

100, 400‧‧‧ base

110, 510‧‧‧High-voltage gate dielectric layer

112, 560‧‧‧ low-voltage gate dielectric layer

114, 122, 132, 134‧‧‧ conductor layers

116, 550‧‧‧ first dielectric layer

118, 540‧‧‧ buffer layer

120, 520‧‧‧ Tunneling dielectric layer

124, 590‧‧‧ second dielectric layer

126a, 136‧‧‧ hard mask layer

126b‧‧‧ bottom anti-reflection layer

130‧‧‧Interruptor dielectric layer

140, 142‧‧ ‧ gate structure

144‧‧‧Control gate

200, 500‧‧‧cell area, third zone

300, 600‧‧‧ surrounding area

310, 610‧‧‧High-voltage component area, first district

320, 620‧‧‧Low-voltage component area, second zone

410‧‧‧Shenjing District

420‧‧‧First Well Area

430‧‧‧First high pressure well area

440, 442‧‧‧ second high pressure well area

444‧‧‧Second high pressure well area

450‧‧‧First low pressure well area

460‧‧‧ second low pressure well area

470, 480‧‧ ‧ cover layer

485, 485a, 485b‧‧‧ stepped openings

530‧‧‧First conductor layer

570‧‧‧Second conductor layer

580‧‧‧3rd conductor layer

D1, D2‧‧‧ distance

R1, R3‧‧‧ dent

R2, R4‧‧‧ groove

S201~S207, S301~S307‧‧‧ steps

1A to 1R are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

2A to 2L are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

3A to 3L are schematic cross-sectional views showing a manufacturing process of a memory element according to a third embodiment of the present invention.

4 is a flow chart showing the manufacture of a memory element in accordance with a second embodiment of the present invention.

Figure 5 is a flow chart showing the manufacture of a memory element in accordance with a third embodiment of the present invention.

1A to 1R are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The material of the substrate 100 is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 100 can also be a blanket insulating (SOI) substrate. The above substrate 100 includes a cell region 200 (which may be regarded as a third region) and a peripheral region 300. The peripheral zone 300 includes a high voltage component region 310 (which may be considered a first zone) and a low voltage component zone 320 (which may be considered a second zone).

Next, a high voltage thyristor layer 110 (which may be regarded as a first gate dielectric layer) is formed on the substrate 100 of the high voltage device region 310. A low voltage gate dielectric layer 112 (which may be considered a second gate dielectric layer) is formed on the substrate 100 of the low voltage device region 320. A low voltage gate dielectric layer 112 is formed on the substrate 100 of the cell region 200. The material of the high voltage gate dielectric layer 110 and the low voltage gate dielectric layer 112 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer. The method of forming the high voltage thyristor layer 110 can utilize localized local thermal oxidation (LOCOS). The method of forming the low-voltage gate dielectric layer 112 can be formed by chemical vapor deposition, in-situ steam generation (ISSG), low-pressure radical oxidation (LPRO) or furnace tube oxidation. In an embodiment, the high voltage gate dielectric layer 110 has a thickness of 30 nm to 70 nm. In one embodiment, the low voltage gate dielectric layer 112 has a thickness of 2 nm to 9 nm.

Next, the conductor layer 114 is sequentially formed on the high voltage gate dielectric layer 110 of the high voltage device region 310, the low voltage gate dielectric layer 112 of the low voltage device region 320, and the low voltage gate dielectric layer 112 of the cell region 200. A dielectric layer 116. The material of the conductor layer 114 is, for example, doped polysilicon, non-doped polysilicon or a combination thereof, and the formation method thereof can be performed by chemical vapor deposition. In an embodiment, the conductor layer 114 has a thickness of 20 nm to 50 nm. In an embodiment, the first dielectric layer 116 has a thickness of 20 nm to 60 nm.

Then, a first isolation structure 10 is formed in the substrate 100 between the cell region 200 and the high voltage device region 310, an isolation structure 40 is formed in the substrate 100 of the high voltage device region 310, and isolation is formed in the substrate 100 of the low voltage device region 320. Structure 50. The materials of the first isolation structure 10, the isolation structure 40 and the isolation structure 50 are, for example, doped or undoped cerium oxide, high-density plasma oxide, cerium oxynitride or a combination thereof, and the formation method thereof can utilize shallow trench isolation method. (Shallow Trench Isolation Process) to form. More specifically, taking the first isolation structure 10 as an example, in an embodiment, a patterned mask layer (not shown) is first formed on the substrate 100, and a dry etching process is performed, for example, reactive ion etching ( Reactive Ion Etching, RIE), removing a portion of the first dielectric layer 116, the conductor layer 114, the low-voltage gate dielectric layer 112, the high-voltage gate dielectric layer 110, and the substrate 100 between the cell region 200 and the peripheral region 300 to form a trench . Next, a high density plasma oxide layer is formed on the substrate 100 to fill the trenches. Thereafter, a high density plasma oxide layer on the substrate 100 is planarized by chemical mechanical polishing (CMP) to expose a portion of the first dielectric layer 116 of the perimeter region 300. In one embodiment, after the chemical mechanical polishing, a portion of the high density plasma oxide layer remains on the first dielectric layer 116 of the cell region 200.

Referring to FIG. 1B, a buffer layer 118 is formed on the substrate 100. The material of the buffer layer 118 is, for example, yttrium oxide (SiO ₂ ), lanthanum carbide (SiC), lanthanum carbonitride (SiCN), lanthanum oxynitride (SiON), lanthanum oxynitride (SiCON) or a combination thereof, and the formation method thereof can be It is formed by a chemical vapor deposition method, a thermal oxidation method, a spin coating method, or the like. In an embodiment, the buffer layer 118 has a thickness of 100 nm to 300 nm. The buffer layer 118 can be used to protect the substrate 100, the high voltage gate dielectric layer 110 and the low voltage gate dielectric layer 112 underneath, so as to prevent the subsequent microlithography process from damaging the quality of the three surfaces, thereby improving product reliability. Thereafter, a patterned mask layer 12 is formed on the substrate 100 of the peripheral region 300. The patterned mask layer 12 is, for example, a patterned photoresist layer.

Next, referring to FIG. 1C, the patterned mask layer 12 is used as a mask, and a dry etching process such as reactive ion etching is performed to remove the buffer layer 118 on the cell region 200. Then, referring to FIG. 1D, the patterned mask layer 12 is used as a mask to perform a dry or wet etching process to remove the first dielectric layer 116 and the conductor layer 114 on the cell region 200. Thereafter, the patterned mask layer 12 and the low voltage gate dielectric layer 112 on the cell region 200 are removed to expose the surface (not shown) of the substrate 100 of the cell region 200.

Referring to FIG. 1E, a tunneling dielectric layer 120 (which may be regarded as a third gate dielectric layer) is formed on the substrate 100 of the cell region 200. The material of the tunneling dielectric layer 120 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, which can be formed by chemical vapor deposition, in situ steam generation, low pressure radical oxidation or furnace tube oxidation. Law is formed. In an embodiment, the tunneling dielectric layer 120 has a thickness of 5 nm to 9 nm. In one embodiment, the thickness of the high voltage gate dielectric layer 110 of the high voltage device region 310, the thickness of the low voltage gate dielectric layer 112 of the low voltage device region 320, and the thickness of the tunnel dielectric layer 120 of the cell region 200 may be different from each other. . In other words, the thickness of the above three can be adjusted by the method of manufacturing the memory element of the present invention. Since the original triple gate oxide process is an extremely complicated process, including the deposition and removal of most layers, it has to go through multiple lithography processes, so the cost is high, the process is difficult to control, and the component performance is degraded. However, the method of manufacturing the memory element of the present invention does not need to be increased. Additional reticles simplify process, reduce cost and reduce damage to components.

Referring to FIG. 1F, a conductor layer 122 (for example, as a floating gate) and a second dielectric layer 124 are sequentially formed on the substrate 100. The material of the conductor layer 122 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition. In an embodiment, the conductor layer 122 has a thickness of 80 nm to 150 nm, and the conductor layer 122 has a thickness greater than the thickness of the conductor layer 114. The thinner thickness of the conductor layer 114 can reduce the problem of excessive breakage caused by subsequent processes, which will be described in detail in subsequent paragraphs. The material of the second dielectric layer 124 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, which may be formed by chemical vapor deposition, thermal oxidation or plasma enhanced chemical vapor deposition (PECVD). Wait to form. In an embodiment, the second dielectric layer 124 has a thickness of 30 nm to 100 nm.

Referring to FIG. 1G, a patterned mask layer 126 is formed on the second dielectric layer 124 of the cell region 200. The patterned mask layer 126 includes a hard mask layer 126a, a bottom anti-reflective (BARC) layer 126b, and a mask layer 126c. The material of the hard mask layer 126a is, for example, a tantalum material, a metal material or a carbon material. The material of the bottom anti-reflection layer 126b is, for example, an organic polymer, carbon or bismuth oxynitride or the like. The material of the mask layer 126c is, for example, carbon, a photoresist material, or an oxynitride.

Then, referring to FIG. 1H, the buffer layer 118 is used as an etch stop layer, and an etching process (for example, reactive ion etching) is performed to remove a portion of the second dielectric layer 124, the conductor layer 122, and the substrate of the cell region 200. 100. The substrate 100 is exposed to a side of a portion of the first isolation structure 10 to form a plurality of trenches 14. During the etching process, the mask layer 118 of the peripheral region 300 is completely patterned by the mask The layer 12 is covered (as shown in FIG. 1B to FIG. 1D) and still exists on the peripheral region 300. Therefore, when the second dielectric layer 124 and the conductor layer 122 of the peripheral region 300 are removed, the buffer layer 118 can be regarded as the peripheral region 300. The etch stop layer. Next, the ashing treatment after the etching process is performed to remove the remaining mask layer 126 on the cell region 200, and then the wet cleaning process is performed. The trench 14 may include a trench 14a and a trench 14b. The trench 14b exposes a portion of the side of the first isolation structure 10, the side of which is not a flat surface, but a surface having a gap (for example, a stepped shape). The above-mentioned gap refers to the distance D1 between the first surface S1 of the first isolation structure 10 and the second surface S2 of the buffer layer 118 after the above etching process. When the gap is too large, that is, the distance D1 becomes larger, after the subsequent etching process, the side surface of the first isolation structure 10 is likely to generate particles or concave and convex trenches, and the particles or trenches are difficult to be removed by a general etching method, so that residual Particles or trenches can affect the operation of the memory component and the reliability of the product. In order to avoid the problem that the above-mentioned fault is too large, in the present embodiment, the conductor layer 114 having a relatively small thickness is deposited first, so that the etching process of the conductor layer 114 for removing the cell region 200 is not subsequently consumed. Isolation structure 10. Therefore, when the trench 14b is formed, the distance D1 is not excessively large, so that the side surface of the first isolation structure 10 does not cause particles or irregularities which are difficult to remove. In other words, the present invention can utilize an etching process that originally forms a memory array in the cell region 200 to solve the above problem of excessively large variations. Therefore, the present invention requires an additional mask or a special process to perform a triple gate oxide process to reduce cost and simplify process.

Referring to FIG. 1I, a plurality of second isolation structures 20 are formed in the trenches 14a and a third isolation structure 30 is formed in the trenches 14b. a plurality of second isolation structures 20 The material of the third isolation structure 30 is, for example, doped or undoped yttrium oxide, high-density plasma oxide, spin-on glass, ytterbium oxynitride or a combination thereof, which can be formed by shallow trench isolation or spin Formed by a glass method. More specifically, in one embodiment, the spin-on glass is first applied to the surface of the substrate 100 by a coating method, and then subjected to a curing process, that is, heat treatment is performed at a high temperature. The solvent is driven out to fix it to form a spin-on glass layer. Since the spin-on glass has a better step coverage capability and a Gap Fill capability, the gap of the trench 14 can be filled. A chemical mechanical polishing process is then performed to planarize the surfaces of the second isolation structure 20 and the third isolation structure 30 to expose the surface of the second dielectric layer 124. In an embodiment, the third isolation structure 30 covers a portion of the first isolation structure 10, and the bottom of the third isolation structure 30 is stepped. In an embodiment, the bottom of the first isolation structure 10 and the plurality of second isolation structures 20 are planar.

Referring to FIG. 1J, a patterned mask layer 16 is formed on the partial cell region 200 and the substrate 100 of the peripheral region 300. Next, referring to FIG. 1K, an etching process is performed, such as reactive ion etching, to remove a portion of the second isolation structure 20 and a portion of the second dielectric layer 124 of the cell region 200. Then, referring to FIG. 1L, the patterned mask layer 16 is removed. In one embodiment, the method of removing the patterned mask layer 16 may be to first pattern the mask layer 16 with high density plasma ashing, followed by a wet cleaning process.

Referring to FIG. 1M, the buffer layer 118 of the peripheral region 300 is removed. In an embodiment, the buffer layer 118 on the peripheral region 300 may be on the surface of the dielectric layer 124 removed. The original oxide layer (Native Oxide) is removed at the same time, and part of the above second isolation structure 20 is also removed at the same time. In an embodiment, the method of removing the original oxide layer may be a wet etching method, and the etching liquid used is, for example, hydrofluoric acid, hydrofluoric acid vapor, a mixed solution of nitric acid and hydrofluoric acid, sulfuric acid and hydrofluoric acid. Mixed solution or hot phosphoric acid (150 ° C ~ 200 ° C) and so on. Then, referring to FIG. 1N, the first dielectric layer 116 and the second dielectric layer 124 are removed. The original oxide layer on the sidewall of the conductor layer 122 is then removed, and the removal method may be a dry etching method (for example, a sputtering etching method, a reactive ion etching method) or a wet etching using hydrofluoric acid vapor.

Referring to FIG. 10, a gate dielectric layer 130 and a conductor layer 132 (eg, a control gate) are sequentially formed on the substrate 100. In an embodiment, the inter-gate dielectric layer 130 is, for example, a composite layer comprising an Oxide-Nitride-Oxide (ONO) material, which may be formed by chemical vapor deposition. , thermal oxidation, in situ steam generation, or low pressure radical oxidation. The material of the conductor layer 132 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition. In an embodiment, the conductor layer 132 has a thickness of 10 nm to 40 nm.

Referring to FIG. 1P, an opening 18 is formed in the inter-gate dielectric layer 130, the conductor layer 132, and the conductor layer 114 of the high voltage device region 310. More specifically, a patterned mask layer (not shown) is formed on the inter-gate dielectric layer 130, and then an etching process is performed, such as reactive ion etching to remove the high voltage device region 310. A portion of the conductor layer 132, the inter-gate dielectric layer 130, and the conductor layer 114 are exposed to expose the conductor layer 114. Next, an ashing process and a wet cleaning process are performed to remove the patterned mask layer.

Referring to FIG. 1Q, a conductor layer 134 (eg, a control gate) and a hard mask layer 136 are sequentially formed on the substrate 100 to fill the opening 18. Conductor layer 134 can include a polysilicon layer, a deuterated metal layer, or a combination thereof. The material of the polysilicon layer is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition. The material of the deuterated metal layer is, for example, tungsten telluride, titanium telluride, cobalt telluride, antimony telluride, nickel telluride, platinum telluride or palladium telluride. The formation method can be formed by a chemical vapor deposition process. The material of the hard mask layer 136 is, for example, yttrium oxide (SiO ₂ ), tantalum nitride (SiN), tantalum material, metal material or carbon material.

Referring to FIG. 1R, the hard mask layer 136 is patterned. Then, using the patterned hard mask layer 136 as a mask, an etching process is performed to remove a portion of the conductor layer 134, a portion of the conductor layer 132, a portion of the inter-gate dielectric layer 130, a portion of the conductor layer 114, and a portion of the high voltage thyristor. The electric layer 110 forms the inter-gate dielectric layer 130 and the control gate 144 in the cell region 200; the first gate structure 140 and the second gate structure 142 are formed in the high voltage device region 310 and the low voltage device region 320, respectively.

In summary, the method of fabricating the memory device of the present invention avoids the problem of excessively large variations in the side faces of the first isolation structure 10 by forming a thinner conductor layer 114 on the peripheral region 300. On the other hand, the buffer layer 118 is used as an etch stop layer for protecting the substrate 100 under the buffer layer 118, the high voltage gate dielectric layer 110 (which can be regarded as the first gate dielectric layer), and the low voltage gate dielectric layer 112 (visible For the second gate dielectric layer), the damage of the subsequent majority of the lithography process is avoided, thereby improving the reliability of the product. In addition, the above manufacturing method requires an additional mask or special process to perform a triple gate oxide layer process, which reduces cost, simplifies the process, and is compatible with existing ones. Bit steam generation method, low pressure radical oxidation method and furnace tube oxidation method.

In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic.

2A to 2L are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention. 4 is a flow chart showing the manufacture of a memory element in accordance with a second embodiment of the present invention.

Referring to FIG. 2A and FIG. 4, step S201 is performed to provide a substrate 400. The material of the substrate 400 is, for example, selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. At least one material. Substrate 400 can also be a blanket insulating substrate. The substrate 400 has a cell region 500 (which may be regarded as a third region) and a peripheral region 600. In more detail, the peripheral zone 600 includes a high voltage component region 610 (which may be considered a first zone) and a low voltage component zone 620 (which may be considered a second zone).

A deep well region 410 having a first conductivity type is formed in the substrate 400 of the cell region 500. The deep well region 410 can be formed by forming a patterned mask layer and performing an ion implantation process. In an embodiment, the doping implanted in the deep well region 410 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , and the implanted energy is, for example, 1000KeV to 4000KeV.

A first well region 420 having a second conductivity type is formed in the deep well region 410. The first well region 420 can be formed by forming a patterned mask layer and performing an ion implantation process. In an embodiment, the doping implanted in the first well region 420 is, for example, boron, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , and the implanted energy is, for example, 10 KeV. Up to 1000KeV.

A first high voltage well region 430 having a second conductivity type is formed in the substrate 400 of the high voltage element region 610. The first high voltage well region 430 can be formed by forming a patterned mask layer and performing an ion implantation process. In an embodiment, the doping of the first high voltage well region 430 is, for example, boron, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , and the implanted energy is, for example, 10KeV to 1000KeV.

A second high pressure well region 440 having a first conductivity type is formed in the substrate 400 between the deep well region 410 and the first high voltage well region 430. More specifically, two second high pressure well regions 442, 444 having a first conductivity type are formed on both sides of the deep well region 410, and the second high pressure well region 442 is on one side of the deep well region 410 and the first well region 420. Adjacent to the deep well zone 410 and the first well zone 420. The second high pressure well zone 444 is between the deep well zone 410 and the first high pressure well zone 430. The second high pressure well region 440 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the second high voltage well region 440 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , implanted. The energy is, for example, 10 KeV to 2000 KeV.

A first low pressure well region 450 having a first conductivity type is formed in the substrate 400 of the low voltage component region 620. The first low pressure well region 450 can be formed by forming a patterned mask layer and performing an ion implantation process. In an embodiment, the doping of the first low-pressure well region 450 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , implanted. The energy is, for example, 1 KeV to 1000 KeV.

A second low pressure well region 460 having a second conductivity type is formed in the substrate 400 between the first high pressure well region 430 and the first low pressure well region 450. The second low pressure well region 460 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the second low-pressure well region 460 is, for example, boron, and the doping dose is, for example, 1×10 ¹⁰ /cm ² to 1×10 ¹⁴ /cm ² , and the implanted energy is, for example, 1KeV to 1000KeV.

Next, in step S202, a high voltage gate dielectric layer 510 (which may be regarded as a first gate dielectric layer) is formed on the substrate 400 of the high voltage device region 610. The material of the high voltage gate dielectric layer 510 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, and the formation method thereof can be formed by a partial region thermal oxidation method. In an embodiment, the high voltage gate dielectric layer 510 has a thickness of 30 nm to 70 nm.

Proceeding to step S202, a tunneling dielectric layer 520 (which may be regarded as a second gate dielectric layer) is formed on the substrate 400 of the cell region 500 and the low voltage device region 620. The material of the tunneling dielectric layer 520 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, and the formation method thereof may be performed by chemical vapor deposition, in situ steam generation, low pressure radical oxidation or furnace tube oxidation. Law is formed. In an embodiment, the tunneling dielectric layer 520 has a thickness of 5 nm to 9 nm.

Step S203 is performed to form a first conductor layer 530 on the substrate 400. The first conductor layer 530 material is, for example, a doped polysilicon, an undoped polysilicon or a combination thereof, and the formation method thereof can be formed by a chemical vapor deposition method, a low pressure chemical vapor deposition method, or a furnace tube oxidation method. In an embodiment, the first conductor layer 530 has a thickness of 10 nm to 40 nm.

Step S203 is performed to form a buffer layer 540 on the first conductor layer 530. The material of the buffer layer 540 is, for example, yttrium oxide (SiO ₂ ), lanthanum carbide (SiC), lanthanum carbonitride (SiCN), lanthanum oxynitride (SiON), lanthanum oxynitride (SiCON) or a combination thereof, and the formation method thereof may be It is formed by a chemical vapor deposition method, a thermal oxidation method, a furnace tube oxidation method, or the like. In an embodiment, the buffer layer 540 has a thickness of 10 nm to 40 nm. The buffer layer 540 can be used to protect the underlying substrate 400, the high voltage thyristor layer 510, and the tunneling dielectric layer 520, so as to prevent the subsequent lithography process from damaging the quality of the three surfaces, thereby improving product reliability.

Step S203 is performed to form a first dielectric layer 550 on the buffer layer 540. The material of the first dielectric layer 550 is different from the buffer layer 540. The material of the first dielectric layer 550 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, and the formation method thereof can be formed by a chemical vapor deposition method, a thermal oxidation method, or a low pressure chemical vapor deposition method. In an embodiment, the first dielectric layer 550 has a thickness of 10 nm to 40 nm.

Referring to FIG. 2B, a patterned mask layer 470 is formed on the substrate 400. The material of the patterned mask layer 470 is, for example, a carbon or photoresist type material or the like. The patterned mask layer 470 exposes a portion of the surface of the first dielectric layer 550 of the low voltage device region 620.

Referring to FIG. 2C and FIG. 4, step S204 is performed to perform an etching process to sequentially remove portions of the first dielectric layer 550, the portion of the buffer layer 540, and a portion of the first conductor layer 530 on the low voltage device region 620 to expose tunneling. The surface of the dielectric layer 520. The patterned mask layer 470 is then removed. In one embodiment, the method of removing the patterned mask layer 470 may be followed by a high-density plasma ashing of the patterned mask layer 470 followed by a wet cleaning process.

Referring to FIG. 2D and FIG. 4, step S204 is performed to perform a wet etching process to remove the tunneling dielectric layer 520 on the low voltage device region 620. In one embodiment, the etching solution used in the wet etching process is, for example, hydrofluoric acid, hydrofluoric acid vapor, a mixed solution of nitric acid and hydrofluoric acid, hot phosphoric acid (150 ° C to 200 ° C) or sulfuric acid and hydrofluoric acid. Mixed solution, etc. More specifically, a portion of the buffer layer 540 may be worn out in the wet etching process described above such that the side of the buffer layer 540 forms a recess R1.

Referring to FIG. 2E and FIG. 4, step S204 is performed to form a low-voltage gate dielectric layer 560 (which may be regarded as a third gate dielectric layer) on the substrate 400. The material of the low-voltage gate dielectric layer 560 is, for example, a hafnium oxide layer, a hafnium oxynitride layer or a tantalum nitride layer, and the formation method thereof may be performed by chemical vapor deposition, in-situ steam generation, low-pressure radical oxidation or furnace tube oxidation. Law is formed. In an embodiment, the low voltage gate dielectric layer 560 has a thickness of 2 nm to 9 nm.

Referring to FIG. 2F and FIG. 4, step S204 is performed to form a second conductor layer 570 on the substrate 400. Specifically, the second conductor layer 570 is overlaid on the side of the low voltage gate dielectric layer 560 and the buffer layer 540. The second conductor layer 570 material is, for example, a doped polysilicon, an undoped polysilicon or a combination thereof, and the formation method thereof can be formed by a chemical vapor deposition method, a low pressure chemical vapor deposition method, or a furnace tube oxidation method. In an embodiment, the second conductor layer 570 has a thickness of 10 nm to 40 nm.

Referring to FIG. 2G, a patterned mask layer 480 is formed on the substrate 400. The material of the patterned mask layer 480 is, for example, a carbon material or a photoresist type material. In an embodiment, the patterned mask layer 480 is spaced from the adjacent second conductor layer 570 by a distance of D2. The distance of D2 is, for example, 100 nm to 300 nm.

Referring to FIG. 2H, an etching process is performed to sequentially remove the second conductor layer 570, the low voltage gate dielectric layer 560, and the first dielectric layer 550 on the cell region 500 and the high voltage device region 610 to expose the buffer layer 540. surface. During the etching process, in order to completely remove the second conductor layer 570 conforming to the sidewall of the buffer layer 540, a portion of the substrate 400 of the first low-pressure well region 450 that is not covered by the patterned mask layer 480 is etched away. And the groove R2 is formed. The patterned mask layer 480 is then removed. In one embodiment, the method of removing the patterned mask layer 480 may be followed by a high density plasma ashing of the patterned mask layer 480 followed by a wet cleaning process.

Referring to FIG. 2I and FIG. 4, step S205 is performed to perform a wet etching process to remove the buffer layer 540 and the low-voltage gate dielectric layer 560 not covered by the second conductor layer 570 to expose the sidewall of the second conductor layer 570. And a stepped opening 485 formed by the sidewall of the tunneling dielectric layer 520 and the surface of the first low-pressure well region 450 and the recess R2. In one embodiment, the etching solution used in the wet etching process is, for example, a mixed solution of hydrofluoric acid, nitric acid, and hydrofluoric acid, hot phosphoric acid (150 ° C to 200 ° C), or a mixed solution of phosphoric acid and hydrofluoric acid.

Referring to FIG. 2J and FIG. 4, in step S206, a third conductor layer 580 and a second dielectric layer 590 are sequentially formed on the substrate 400 to fill the stepped opening 485. The material of the third conductor layer 580 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by a chemical vapor deposition method, a low pressure chemical vapor deposition method, or a furnace tube oxidation method. In an embodiment, the third conductor layer 580 has a thickness of 50 nm to 150 nm. The material of the second dielectric layer 590 is, for example, a ruthenium oxide layer, a ruthenium oxynitride layer or a tantalum nitride layer, and the formation method thereof can be performed by chemical vapor deposition, Formed by physical vapor deposition, thermal oxidation or furnace tube oxidation. In an embodiment, the second dielectric layer 590 has a thickness of 10 nm to 100 nm.

Referring to FIG. 2K and FIG. 4 , step S207 is performed to form a plurality of trenches 19 in the substrate 400 , wherein a plurality of trenches 19 extend through the second dielectric layer 590 into the substrate 400 . More specifically, a plurality of trenches 19 are formed in the substrate 400 around the cell region 500, the high voltage device region 610, and the low voltage device region 620. Taking a trench between the cell region 500 and the high voltage device region 610 as an example, in one embodiment, a patterned mask layer (not shown) is first formed on the substrate 400, and a dry etching process such as reactive ions is performed. A portion of the second dielectric layer 590, the third conductor layer 580, the first conductor layer 530, the high voltage thyristor layer 510, the tunneling dielectric layer 520, the low voltage gate dielectric layer 560, and the substrate on the substrate 400 are removed by etching. 400 to form a trench 19.

Referring to FIG. 2L and FIG. 4, step S207 is performed to form a plurality of isolation structures 490 in the trench 19. More specifically, a layer of insulating material, such as a high density plasma oxide layer or spin-on glass, is formed on substrate 400 to fill a plurality of trenches 19. Thereafter, the layer of isolation material on substrate 400 is planarized by chemical mechanical polishing to expose second dielectric layer 590 on substrate 400. Next, following the manufacturing flow of FIG. 1G to FIG. 1I described above, a memory array is formed on the cell region 400, and details are not described herein again.

3A to 3L are schematic cross-sectional views showing a manufacturing process of a memory element according to a third embodiment of the present invention. Figure 5 is a flow chart showing the manufacture of a memory element in accordance with a third embodiment of the present invention. In the following embodiments, the same or similar elements, members, and layers are denoted by like reference numerals. For example, the deep well region 410 of FIG. 2A is the same or similar member as the deep well region 410 of FIG. 3A; the first well region 420 of FIG. 2A and FIG. 3A The first well zone 420 is the same or similar component. This will not be repeated here.

Referring to FIG. 3A, FIG. 5, FIG. 2A and FIG. 4, the manufacturing process of the memory element of the third embodiment of the present invention is substantially similar to the manufacturing process of the memory element of the second embodiment of the present invention (ie, step S201 and S301 is similar, step S202 is similar to S302, and steps S203 are similar to S303. The steps have been described in the above paragraphs, and will not be described in detail herein. The difference between the above two is that the manufacturing process of the memory element of the second embodiment is to form a tunnel on the substrate 400 of the low voltage element region 620 (which can be regarded as the second region) and the cell region 500 (which can be regarded as the third region). The dielectric layer 520 (as shown in step S202); and the manufacturing process of the memory element of the third embodiment is a substrate in the low voltage element region 620 (which can be regarded as the second region) and the cell region 500 (which can be regarded as the third region). A low voltage gate dielectric layer 560 is formed over 400 (as shown in step S302).

Next, referring to FIG. 3B, a patterned mask layer 470 is formed on the substrate 400. The material of the patterned mask layer 470 is, for example, a carbon or photoresist type material or the like. The patterned mask layer 470 exposes the surface of the cell region 500 and portions of the first dielectric layer 550 of the low voltage device region 620.

Referring to FIG. 3C and FIG. 5, step S304 is performed to perform an etching process to sequentially remove a portion of the first dielectric layer 550, the buffer layer 540, and the first conductor layer 530 on the cell region 500 and the low voltage device region 620. The surface of the low voltage gate dielectric layer 560 (which may be considered a second gate dielectric layer) is exposed. The patterned mask layer 470 is then removed.

Referring to FIG. 3D and FIG. 5, step S304 is performed to perform a wet etching process to remove the cell region 500 and the low voltage gate dielectric layer 560 on the low voltage device region 620. A portion of the buffer layer 540 may be worn out in the wet etching process described above, such that the side of the buffer layer 540 The face forms a recess R3.

Referring to FIG. 3E and FIG. 5, step S304 is performed to form a tunneling dielectric layer 520 (which may be regarded as a third gate dielectric layer) on the substrate 400. The material, the formation method, and the thickness of the tunneling dielectric layer 520 are as described above for the tunneling dielectric layer 520 of the second embodiment, and will not be described in detail herein.

Referring to FIG. 3F and FIG. 5, step S304 is performed to form a second conductor layer 570 on the substrate 400. Specifically, the second conductor layer 570 covers the surface of the tunnel dielectric layer 520 and the side of the buffer layer 540. The material, formation method, and thickness of the second conductor layer 570 are as described in the second conductor layer 570 of the second embodiment described above, and will not be described in detail herein.

Referring to FIG. 3G, a patterned mask layer 480 is formed on the substrate 400. In detail, the patterned mask layer 480 covers the surface of the cell region 500 and a portion of the second conductor layer 570 of the low voltage device region 620. In one embodiment, the patterned mask layer 480 is spaced from the adjacent second conductor layer 570 by a distance of D3. The distance of D3 is, for example, 100 nm to 300 nm.

Referring to FIG. 3H, an etching process is performed to sequentially remove the second conductor layer 570, the tunneling dielectric layer 520, and the first dielectric layer 550 that are not covered by the patterned mask layer 480 to expose the buffer layer 540. surface. During the etching process, the second well layer 570 conforming to the sidewall of the buffer layer 540 is completely removed, and the first well region 420 and the first low pressure well region 450 are covered by the unpatterned mask layer 480. Part of the substrate 400 is etched to form a recess R4. The patterned mask layer 480 is then removed.

Referring to FIG. 3I and FIG. 5, step S305 is performed to perform a wet etching process. The sidewalls of the second conductor layer 570, the sidewalls of the tunnel dielectric layer 520, and the surface and recess of the first well region 420 are exposed by removing the buffer layer 540 and the tunneling dielectric layer 520 not covered by the second conductor layer 570. A stepped opening 485a formed by R4, and a stepped opening 485b formed by the sidewall of the second conductor layer 570, the sidewall of the tunneling dielectric layer 520, and the surface of the first low-pressure well region 450 and the recess R4 are exposed.

Referring to FIG. 3J and FIG. 5, in step S306, a third conductor layer 580 and a second dielectric layer 590 are sequentially formed on the substrate 400 to fill the stepped openings 485a and 485b. The materials, formation methods, and thicknesses of the third conductor layer 580 and the second dielectric layer 590 are as described in the third conductor layer 580 and the second dielectric layer 590 of the second embodiment described above, and will not be described in detail herein.

Referring to FIG. 3K and FIG. 5 , step S307 is performed to form a plurality of trenches 19 in the substrate 400 , wherein a plurality of trenches 19 extend through the second dielectric layer 590 into the substrate 400 . More specifically, a plurality of trenches 19 are formed in the substrate 400 around the cell region 500, the high voltage device region 610, and the low voltage device region 620.

Referring to FIG. 3L and FIG. 5, step S307 is performed to form a plurality of isolation structures 490 in the trench 19. The isolation structure 490 is located in the substrate 400 around the cell region 500, the high voltage device region 610, and the low voltage device region 620, which can be used to electrically isolate each of the cell region 500, the high voltage device region 610, and the low voltage device region 620. Next, following the manufacturing flow of FIG. 1G to FIG. 1I described above, a memory array is formed on the cell region 400, and details are not described herein again.

It should be noted that the manufacturing process of the memory device of the third embodiment of the present invention first forms the high voltage gate dielectric layer 510, and then forms the low voltage gate dielectric layer 560 (step). Step S302 is shown). Then, a tunneling dielectric layer 520 is formed (as shown in step S304). The formation of the higher-voltage gate dielectric layer 510 and the low-voltage gate dielectric layer 560, the tunneling dielectric layer 520 is formed later, so that most of the lithography process can be prevented from damaging the surface of the tunneling dielectric layer 520. Quality, which in turn increases product reliability.

In addition, the manufacturing process sequence of the memory element of the present invention is not limited in terms of the process flow. For example, the method for fabricating the memory device of the present invention may first form a high voltage gate dielectric layer 510, form a low voltage gate dielectric layer 560, and then form a tunnel dielectric layer 520; or form a high voltage gate dielectric first. The electrical layer 510 is further formed with a tunneling dielectric layer 520, and then a low voltage gate dielectric layer 560 is formed.

In summary, the method of manufacturing the memory device of the present invention can form a memory element of a triple oxide layer without passing through the current nitrogen implantation process. Therefore, due to the poor interface between the ruthenium substrate and the ruthenium oxide layer due to nitrogen implantation, the problem of reducing the ion migration (Ion Mobility) at this interface and delaying the rate of yttrium oxide formation can be solved. Moreover, the present invention can also be compatible with existing high-quality wet oxidation processes, such as in-situ steam generation and low-pressure radical oxidation, thereby increasing the rate of formation of high-quality cerium oxide and increasing the processing rate of the overall memory device. To reduce production costs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

400‧‧‧Base

410‧‧‧Shenjing District

420‧‧‧First Well Area

430‧‧‧First high pressure well area

440, 442, 444‧‧‧ second high pressure well area

450‧‧‧First low pressure well area

460‧‧‧ second low pressure well area

490‧‧‧Isolation structure

500‧‧‧cell area, third zone

510‧‧‧High-voltage gate dielectric layer

520‧‧‧Tunnel dielectric layer

530‧‧‧First conductor layer

560‧‧‧Low-voltage gate dielectric layer

570‧‧‧Second conductor layer

580‧‧‧3rd conductor layer

590‧‧‧Second dielectric layer

600‧‧‧ surrounding area

610‧‧‧High-voltage component area, first district

620‧‧‧Low-voltage component area, second zone

Claims (18)

A method of fabricating a memory device, comprising: providing a substrate having a first region, a second region, and a third region; forming a first gate dielectric layer on the substrate of the first region; a second gate dielectric layer is formed on the substrate of the second region and the third region; a first conductor layer and a first dielectric layer are sequentially formed on the substrate; and the first region and the first region Forming a first isolation structure between the three regions through the first dielectric layer and extending into the substrate; forming a buffer layer on the substrate; sequentially removing the buffer layer of the third region, the first a dielectric layer, the first conductor layer and the second gate dielectric layer to expose a surface of the substrate; forming a third gate dielectric layer on the substrate of the third region; sequentially on the substrate Forming a second conductor layer and a second dielectric layer; forming a plurality of trenches in the second dielectric layer, the second conductor layer, the third gate dielectric layer, and the substrate in the third region; a plurality of second isolation structures are formed on the substrate of the third region, and the second isolation structures fill the trenches; In addition to the buffer layer of the first region and the second region. The method of manufacturing a memory device according to claim 1, wherein the materials of the second isolation structures comprise spin-on glass or high-density plasma oxide. The method of manufacturing the memory device of claim 1, wherein the forming the second isolation structure further comprises: Forming a third isolation structure on a side of the first isolation structure, wherein the third isolation structure covers a portion of the first isolation structure, and a bottom portion of the third isolation structure is stepped. The method of manufacturing the memory device of claim 1, wherein the removing the buffer layer further comprises: removing the first dielectric layer and the first dielectric layer and the third region on the second region The second dielectric layer; a gate dielectric layer and a third conductor layer are sequentially formed on the substrate; the third conductor layer, the gate dielectric layer, and the first region of the first region Forming an opening in a conductor layer; sequentially forming a fourth conductor layer and a patterned hard mask layer on the substrate to fill the opening; and performing an etching process to remove a portion of the fourth conductor layer The third conductor layer, the inter-gate dielectric layer and the first conductor layer to leave the inter-gate dielectric layer in the third region and form a control gate, and form a gate in the first region structure. The method for manufacturing a memory device according to claim 1, wherein the buffer layer material comprises cerium oxide (SiO ₂ ), cerium carbide (SiC), lanthanum carbonitride (SiCN), cerium oxynitride (SiON). , bismuth carbonitride (SiCON) or a combination thereof. The method of manufacturing a memory device according to claim 1, wherein the second conductor layer has a thickness greater than a thickness of the first conductor layer. The method of manufacturing the memory device of claim 1, wherein the material of the first conductor layer and the second conductor layer comprises doped polysilicon, non-doped Crystalline or a combination thereof. The method of manufacturing a memory device according to claim 1, wherein the thickness of the first gate dielectric layer, the thickness of the second gate dielectric layer, and the thickness of the third gate dielectric layer are different from each other. The method of fabricating a memory device according to claim 1, wherein the third gate dielectric layer of the third region is a tunneling dielectric layer. A memory device comprising: a substrate having a first region, a second region, and a third region; a first gate structure on the substrate of the first region, wherein the first gate structure comprises a first gate dielectric layer on the substrate of the first region; and a first conductor layer on the first gate dielectric layer; and a second gate structure located in the second region On the substrate, wherein the second gate structure comprises: a second gate dielectric layer on the substrate of the second region; and a second conductor layer on the second gate dielectric layer; a conductor layer on the substrate of the third region; a third gate dielectric layer between the substrate and the third conductor layer of the third region, wherein the third conductor layer has a thickness greater than the first a thickness of the conductor layer, and a thickness of the third conductor layer is greater than a thickness of the second conductor layer; a first isolation structure in the substrate between the third region and the first region; a plurality of second isolation a structure located in the substrate of the third region; and a third isolation structure covering the portion Isolation structure, and the bottom of the third isolation structure is stepped. The memory device of claim 10, further comprising: a gate dielectric layer on the third conductor layer of the third region, the first conductor layer of the first region, and the first The second conductor layer of the second region; and a fourth conductor layer are disposed on the inter-gate dielectric layer. A method of fabricating a memory device, comprising: providing a substrate having a first region, a second region, and a third region; forming a first gate dielectric layer on the substrate of the first region; Forming a second gate dielectric layer on the substrate of the second region and the third region; forming a first conductor layer, a buffer layer and a first dielectric layer on the substrate; removing the first a portion of the first dielectric layer, a portion of the buffer layer, a portion of the first conductor layer, and a portion of the second gate dielectric layer of the second region to expose a portion of the surface of the second region; Forming a third gate dielectric layer and a second conductor layer on the substrate; removing the buffer layer; sequentially forming a third conductor layer and a second dielectric layer on the substrate; A plurality of isolation structures are formed in the substrate, wherein the isolation structures extend through the second dielectric layer into the substrate. The method of manufacturing the memory device of claim 12, wherein when the third gate dielectric layer and the second conductor layer are formed, a recess is simultaneously formed in the substrate of the second region, and A method of forming one of the isolation structures includes removing The substrate around the recess, the first conductor layer and the third conductor layer and the second dielectric layer above the recess to form a trench; and the trench is filled with a layer of insulating material. The method of fabricating a memory device according to claim 12, wherein the second gate dielectric layer of the third region is a tunneling dielectric layer. The method of manufacturing a memory device according to claim 12, wherein the first dielectric layer, a portion of the buffer layer, a portion of the first conductor layer, and a portion of the second gate are removed at a portion of the second region. The step of the dielectric layer further includes: removing a portion of the first dielectric layer, a portion of the buffer layer, a portion of the first conductive layer, and a portion of the second gate dielectric layer of the third region to expose the first portion The portion of the three regions is the surface of the substrate. The method of manufacturing the memory device of claim 15, wherein the step of sequentially forming the third gate dielectric layer and the second conductor layer on the substrate of the second region further comprises: The third gate dielectric layer and the second conductor layer are sequentially formed on the substrate of the third region. The method of fabricating a memory device according to claim 16, wherein the third gate dielectric layer of the third region is a tunneling dielectric layer. The method of manufacturing the memory device of claim 16, wherein the third gate dielectric layer and the second conductor layer are formed on the substrate of the second region and the third region, Forming two recesses in the base of the second zone and the third zone, respectively, and forming a method of one of the isolation structures includes removing the grooves The substrate, the first conductor layer and the third conductor layer and the second dielectric layer above the recesses respectively form two trenches; and the trenches are filled with a layer of insulating material.