CN107799528B - Method for manufacturing memory element - Google Patents

Method for manufacturing memory element Download PDF

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Publication number
CN107799528B
CN107799528B CN201610764693.0A CN201610764693A CN107799528B CN 107799528 B CN107799528 B CN 107799528B CN 201610764693 A CN201610764693 A CN 201610764693A CN 107799528 B CN107799528 B CN 107799528B
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dielectric layer
region
layer
substrate
gate dielectric
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CN107799528A (en
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陈俊旭
卓旭棋
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN201610764693.0A priority Critical patent/CN107799528B/en
Priority to US15/353,717 priority patent/US10157930B2/en
Priority to JP2017024270A priority patent/JP6302107B2/en
Priority to KR1020170044733A priority patent/KR101989921B1/en
Publication of CN107799528A publication Critical patent/CN107799528A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

The invention provides a manufacturing method of a storage element, which comprises the step of forming a first gate dielectric layer on a substrate in a first area. And forming a second gate dielectric layer on the substrate of the second region and the third region. A first conductive layer is formed on a substrate. A first dielectric layer is directly formed on the first conductive layer. And removing part of the first dielectric layer, part of the first conductor layer and part of the second gate dielectric layer in the second region. And sequentially forming a third gate dielectric layer and a second conductor layer on the substrate in the second region. A third conductive layer and a second dielectric layer are sequentially formed on the substrate. A plurality of isolation structures are formed in the substrate, wherein the isolation structures extend through the second dielectric layer into the substrate. The invention can reduce the resistance of the floating grid and the contact window, thereby improving the efficiency, the reliability and the yield of the product.

Description

Method for manufacturing memory element
Technical Field
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a memory device.
Background
With the increasing development of technology, in order to reduce the cost and simplify the process steps of semiconductor devices, it is becoming a trend to integrate the devices in the Cell Region (Cell Region) and the peripheral Region (peripheral Region) on the same chip. Triple Gate Oxide (Triple Gate Oxide) is one of the methods that can integrate the above two on the same chip.
However, in the conventional triple gate oxide process, the buffer oxide layer is easily remained between the floating gates, which causes the problems of increasing the resistance of the floating gates, increasing the resistance of the contact windows formed on the floating gates, and the like, thereby affecting the performance, reliability and yield of the product.
Disclosure of Invention
The invention provides a manufacturing method of a storage element without a step of forming a buffer oxide layer, which can reduce the resistance values of a floating grid and a contact window, and further improve the efficiency, the reliability and the yield of products.
The invention provides a method for manufacturing a memory element without a step of forming a buffer oxide layer, which can simplify the process and reduce the production cost.
The invention provides a method for manufacturing a memory element, which comprises the following steps. A substrate is provided, the substrate having a first region, a second region, and a third region. A first gate dielectric layer is formed on the substrate in the first region. And forming a second gate dielectric layer on the substrate of the second region and the third region. A first conductive layer is formed on a substrate. A first dielectric layer is directly formed on the first conductive layer. And removing part of the first dielectric layer, part of the first conductor layer and part of the second gate dielectric layer in the second region to expose part of the surface of the substrate in the second region. And sequentially forming a third gate dielectric layer and a second conductor layer on the substrate in the second region. A third conductive layer and a second dielectric layer are sequentially formed on the substrate. A plurality of isolation structures are formed in the substrate, wherein the isolation structures extend through the second dielectric layer into the substrate.
In view of the above, the present invention provides a method for manufacturing a memory device, which integrates devices in a cell area and a peripheral area on the same chip by using a triple gate oxide process. In addition, the triple gate oxide layer process does not have the step of forming the buffer oxide layer, so the problem of residual buffer oxide layer between the floating gates can be avoided. Therefore, the manufacturing method of the memory element can reduce the resistance values of the floating grid and the contact window, and further improve the efficiency, the reliability and the yield of products. In addition, compared with a technology, the manufacturing method of the memory element omits the step of forming the buffer oxide layer, so the manufacturing method of the memory element can simplify the process and reduce the production cost.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIGS. 1A to 1K are schematic cross-sectional views illustrating a manufacturing process of a memory device according to a first embodiment of the invention;
FIGS. 2A to 2K are schematic cross-sectional views illustrating a manufacturing process of a memory device according to a second embodiment of the present invention;
FIG. 3 is a flow chart of the fabrication of a memory device according to a first embodiment of the present invention;
fig. 4 is a flow chart of a manufacturing method of a memory device according to a second embodiment of the present invention.
Reference numerals:
19: a trench;
400: a substrate;
410: a deep well region;
420: a first well region;
430: a first high-pressure well region;
440. 442, 444: a second high-pressure well region;
450: a first low pressure well region;
460: a second low pressure well region;
470. 480: a mask layer;
485. 485a, 485 b: a stepped opening;
490: an isolation structure;
500: a cell area;
510: a high voltage gate dielectric layer;
520: a tunneling dielectric layer;
530: a first conductor layer;
550: a first dielectric layer;
560: a low voltage gate dielectric layer;
570: a second conductor layer;
580: a third conductor layer;
590: a second dielectric layer;
600: a peripheral zone;
610: a high voltage element region;
620: a low voltage device region;
d1, D2: a distance;
r1, R3: recessing;
r2, R4: a groove;
s101 to S107, S201 to S207: and (5) carrying out the following steps.
Detailed Description
In the following embodiments, when the first conductive type is N-type, the second conductive type is P-type; when the first conductive type is P type, the second conductive type is N type. In the present embodiment, the first conductive type is N-type, and the second conductive type is P-type, but the invention is not limited thereto. P-type doping is, for example, boron; the N-type dopant is, for example, phosphorus or arsenic.
Fig. 1A to fig. 1K are schematic cross-sectional views illustrating a manufacturing process of a memory device according to a first embodiment of the invention. Fig. 3 is a flow chart of manufacturing a memory device according to a first embodiment of the present invention.
Referring to fig. 1A and fig. 3, a step S101 is performed to provide a substrate 400, wherein the substrate 400 is made of at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In one embodiment, substrate 400 may also be a Silicon On Insulator (SOI) substrate. The substrate 400 has a cell area 500 (which can be regarded as a third area) and a peripheral area 600. In more detail, the peripheral region 600 includes a high voltage device region 610 (which may be referred to as a first region) and a low voltage device region 620 (which may be referred to as a second region).
In one embodiment, the substrate 400 in the cell area 500 may include a deep well region 410 having a first conductivity type, a first well region 420 having a second conductivity type, and a second high-pressure well region 440 having the first conductivity type. The substrate 400 of the high-voltage device region 610 may include a first high-voltage well region 430 having a second conductivity type therein. The substrate 400 of the low-voltage device region 620 may include a first low-voltage well 450 having a first conductive type and a second low-voltage well 460 having a second conductive type. However, the invention is not limited thereto, and in other embodiments, the substrate 400 in the cell region 500, the high voltage device region 610 and the low voltage device region 620 may also include various well regions and combinations thereof.
In detail, the deep well region 410 may be located in the substrate 400 of the cell region 500. the deep well region 410 may be formed by forming a patterned mask layer and performing an ion implantation process, in one embodiment, the deep well region 410 is implanted with a dopant, such as phosphorous or arsenic, at a dose of, for example, 1 × 1010/cm2To 1 × 1014/cm2The implantation energy is, for example, 1000KeV to 4000 KeV.
The first well region 420 may be located above the deep well region 410, which may be formed by forming a patterned mask layer and performing an ion implantation process, hi one embodiment, the first well region 420 is implanted with a dopant, such as boron, at a dose of, for example, 1 × 1010/cm2To 1 × 1014/cm2The implanted energy is, for example, 10KeV to 1000 KeV.
The second high-voltage well region 440 may include two regions having the first conductivityThe second high-pressure well region 442, the second high-pressure well region 444, the second high-pressure well region 442, the second high-pressure well region 444 are respectively located on two sides of the deep well region 410 and the first well region 420, in other words, the deep well region 410 and the first well region 420 are located between the second high-pressure well region 442 and the second high-pressure well region 444, the second high-pressure well region 442, the second high-pressure well region 444 may be formed by forming a patterned mask layer and performing an ion implantation process, in one embodiment, the second high-pressure well region 442, the second high-pressure well region 444 is implanted with a dopant, such as phosphorus or arsenic, at a dose of, for example, 1 ×10/cm2To 1 × 1014/cm2The implanted energy is, for example, 10KeV to 2000 KeV.
The first high-voltage well region 430 is located in the substrate 400 of the high-voltage device region 610. the first high-voltage well region 430 may be formed by forming a patterned mask layer and performing an ion implantation process, hi one embodiment, the first high-voltage well region 430 is implanted with a dopant, such as boron, at a dose of, for example, 1 × 1010/cm2To 1 × 1014/cm2The implanted energy is, for example, 10KeV to 1000 KeV.
The first low-pressure well region 450 is located in the substrate 400 of the low-pressure device region 620. the first low-pressure well region 450 may be formed by forming a patterned mask layer and performing an ion implantation process, in one embodiment, the first low-pressure well region 450 is implanted with a dopant such as phosphorus or arsenic at a dose of, for example, 1 × 1010/cm2To 1 × 1014/cm2The implanted energy is, for example, 1KeV to 1000 KeV.
The second low-pressure well region 460 is located in the substrate 400 between the first high-pressure well region 430 and the first low-pressure well region 450. the second low-pressure well region 460 may be formed by forming a patterned mask layer and performing an ion implantation process10/cm2To 1 × 1014/cm2The implanted energy is, for example, 1KeV to 1000 KeV.
Next, referring to fig. 1A and fig. 3, step S102 is performed to form a high voltage gate dielectric layer 510 (which may be regarded as a first gate dielectric layer) on the substrate 400 of the high voltage device region 610. The material of the high-voltage gate dielectric layer 510 is, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, and the formation method thereof may be a local area thermal oxidation method. In one embodiment, the thickness of high voltage gate dielectric layer 510 is 30nm to 70 nm.
Continuing to step S102, a tunneling dielectric layer 520 (which may be regarded as a second gate dielectric layer) is formed on the substrate 400 in the cell region 500 and the low-voltage device region 620. The tunnel dielectric layer 520 is made of a material such as a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, and can be formed by chemical vapor deposition, in-situ steam generation, low-pressure radical oxidation, or furnace oxidation. In one embodiment, the thickness of the tunneling dielectric layer 520 is 5nm to 9 nm.
Then, step S103 is performed to form a first conductive layer 530 on the substrate 400. The first conductive layer 530 is made of, for example, doped polysilicon, undoped polysilicon, or a combination thereof, and can be formed by cvd, lpcvd, or furnace oxidation. In one embodiment, the thickness of the first conductive layer 530 is 10nm to 40 nm.
Continuing to step S103, a first dielectric layer 550 is directly formed on the first conductive layer 530. In detail, the first dielectric layer 550 is in direct contact with the first conductive layer 530, and there is no oxide layer therebetween. In one embodiment, the material of the first dielectric layer 550 is, for example, a silicon nitride layer, and the forming method thereof can be performed by using a chemical vapor deposition method. In one embodiment, the thickness of the first dielectric layer 550 is 10nm to 40 nm. Since the thickness of the first dielectric layer 550 is thin enough, the stress effect of the first dielectric layer 550 of the present embodiment is negligible.
Referring to fig. 1B, a patterned mask layer 470 is formed on the substrate 400. The material of the patterned mask layer 470 is, for example, carbon or a photoresist material. The patterned mask layer 470 exposes a portion of the surface of the first dielectric layer 550 of the low voltage device region 620.
Referring to fig. 1C and fig. 3, in step S104, an etching process is performed to sequentially remove a portion of the first dielectric layer 550 and a portion of the first conductive layer 530 on the low voltage device region 620 to expose the surface of the tunneling dielectric layer 520. The patterned masking layer 470 is then removed. In one embodiment, the patterned mask layer 470 is removed by ashing the patterned mask layer 470 with a high density plasma followed by a wet clean process.
Referring to fig. 1D and fig. 3, in step S104, a wet etching process is performed to remove a portion of the tunneling dielectric layer 520 on the low voltage device region 620. In one embodiment, the etching solution used in the wet etching process is, for example, hydrofluoric acid vapor, a mixed solution of nitric acid and hydrofluoric acid, hot phosphoric acid (150 ℃ to 200 ℃), a mixed solution of sulfuric acid and hydrofluoric acid, or the like. More specifically, portions of the first conductive layer 530 and portions of the tunneling dielectric layer 520 under the first conductive layer 530 may be consumed in the wet etching process, such that the recess R1 is formed on the side of the remaining first conductive layer 530 and the side of the remaining tunneling dielectric layer 520.
Referring to fig. 1E and fig. 3, step S104 is performed to form a low-voltage gate dielectric layer 560 (which may be regarded as a third gate dielectric layer) on the substrate 400. The low voltage gate dielectric layer 560 covers the surface of the first dielectric layer 550 and a portion of the top surface of the substrate 400 of the low voltage device region 620. That is, the low-voltage gate dielectric layer 560 does not cover the sides of the remaining first conductive layer 530 and the sides of the remaining tunneling dielectric layer 520. In one embodiment, the material of the low-voltage gate dielectric layer 560 is, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, and the formation method thereof can be chemical vapor deposition, in-situ vapor deposition, low-voltage radical oxidation, or furnace oxidation. In one embodiment, the thickness of the low voltage gate dielectric layer 560 is 2nm to 9 nm.
Referring to fig. 1E, fig. 1F and fig. 3, step S104 is performed to form a second conductive layer 570 on the substrate 400. Specifically, the second conductor layer 570 covers the surface of the low voltage gate dielectric layer 560, the sides of the remaining first conductor layer 530, and the sides of the remaining tunneling dielectric layer 520. That is, the second conductive layer 570 is conformally formed on the surface of the low-voltage gate dielectric layer 560 and also fills the recess R1. In one embodiment, the second conductive layer 570 is, for example, doped polysilicon, undoped polysilicon, or a combination thereof, and can be formed by cvd, lpcvd, or furnace oxidation. In one embodiment, the thickness of the second conductive layer 570 is 10nm to 40 nm.
Referring to fig. 1G, a patterned mask layer 480 is formed on the substrate 400. The material of the patterned mask layer 480 is, for example, a carbon material or a photoresist material. In one embodiment, the patterned mask layer 480 is separated from the adjacent second conductive layer 570 by a distance D1. The distance of D1 may be, for example, 100nm to 300 nm.
Referring to fig. 1G, fig. 1H and fig. 3, step S105 is performed to perform an etching process to sequentially remove the second conductive layer 570, the low-voltage gate dielectric layer 560 and the first dielectric layer 550 on the cell region 500 and the high-voltage device region 610, so as to expose the surface of the first conductive layer 530. During the etching process, in order to completely remove the second conductive layer 570 conformal on the surface of the low-voltage gate dielectric layer 560, the portion of the first low-voltage well 450 (i.e., the substrate 400) not covered by the patterned mask layer 480 is consumed by the etching process, thereby forming the recess R2. At this time, the sidewalls of the first conductive layer 530, the sidewalls of the tunneling dielectric layer 520, the top surface of the first low-voltage well 450 and the recess R2 form a step-shaped opening 485. The patterned masking layer 480 is then removed. In one embodiment, the patterned mask layer 480 may be removed by ashing the patterned mask layer 480 with a high density plasma followed by a wet clean process.
Referring to fig. 1I and 3, step S106 is performed to sequentially form a third conductive layer 580 and a second dielectric layer 590 on the substrate 400 to fill the step-shaped opening 485. The third conductive layer 580 is made of, for example, doped polysilicon, undoped polysilicon, or a combination thereof, and can be formed by cvd, lpcvd, or furnace oxidation. In one embodiment, the thickness of the third conductive layer 580 is 50nm to 150 nm. The second dielectric layer 590 may be made of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, and the formation method thereof may be chemical vapor deposition, physical vapor deposition, thermal oxidation, furnace oxidation, or the like. In one embodiment, the thickness of the second dielectric layer 590 is 10nm to 100 nm.
Referring to fig. 1I, 1J and 3, step S107 is performed to form a plurality of trenches 19 in the substrate 400, wherein the plurality of trenches 19 extend into the substrate 400 through the second dielectric layer 590. More specifically, a plurality of trenches 19 are formed in the substrate 400 around the cell area 500, the high voltage device area 610, and the low voltage device area 620. Taking the trench between the cell area 500 and the high voltage device area 610 as an example, in one embodiment, a patterned mask layer (not shown) is formed on the substrate 400, and a dry etching process, such as a reactive ion etching, is performed to remove a portion of the second dielectric layer 590, a portion of the third conductive layer 580, a portion of the first conductive layer 530, a portion of the high voltage gate dielectric layer 510, a portion of the tunneling dielectric layer 520, a portion of the low voltage gate dielectric layer 560, and a portion of the substrate 400 on the substrate 400 to form the trench 19.
Referring to fig. 1J, fig. 1K and fig. 3, step S107 is performed to form a plurality of isolation structures 490 in the trenches 19. More specifically, a layer of isolation material, such as a high density plasma oxide or spin-on glass, is formed over the substrate 400 to fill the plurality of trenches 19. Thereafter, the isolation material layer on the substrate 400 is planarized by chemical mechanical polishing to expose the second dielectric layer 590 on the substrate 400. Next, a memory array is formed on the cell area 400, which is well known to those skilled in the art and will not be described in detail herein. Although the top surface of the isolation structure 490 and the top surfaces of the second dielectric layers 590 on both sides thereof are not coplanar as shown in FIG. 1K, the invention is not limited thereto. In other embodiments, the top surface of the isolation structure 490 and the top surfaces of the second dielectric layers 590 on both sides thereof may be coplanar, for example.
Fig. 2A to fig. 2K are schematic cross-sectional views illustrating a manufacturing process of a memory device according to a second embodiment of the invention. Fig. 4 is a flow chart of a manufacturing method of a memory device according to a second embodiment of the present invention. In the following embodiments, the same or similar elements, members, layers are denoted by similar reference numerals. For example, the deep-well area 410 of fig. 1A is the same or similar component as the deep-well area 410 of fig. 2A. And are not described in detail herein.
Referring to fig. 2A, fig. 4, fig. 1A and fig. 3, the manufacturing process of the memory device according to the second embodiment of the present invention is substantially similar to the manufacturing process of the memory device according to the first embodiment of the present invention (i.e., step S101 is similar to step S201, step S102 is similar to step S202, and step S103 is similar to step S203), and the steps thereof have been described in the above paragraphs, and thus, will not be described in detail herein. The difference between the two is as follows: the manufacturing process of the memory device of the first embodiment is to form a tunneling dielectric layer 520 on the substrate 400 in the low-voltage device region 620 (which can be regarded as the second region) and the cell region 500 (which can be regarded as the third region) (step S202); the manufacturing process of the memory device of the second embodiment is to form a low-voltage gate dielectric layer 560 on the substrate 400 in the low-voltage device region 620 (which can be regarded as the second region) and the cell region 500 (which can be regarded as the third region) (step S202).
Next, referring to fig. 2B, a patterned mask layer 470 is formed on the substrate 400. The material of the patterned mask layer 470 is, for example, carbon or a photoresist material. The patterned mask layer 470 exposes the surface of the cell region 500 and a portion of the first dielectric layer 550 of the low voltage device region 620.
Referring to fig. 2C and fig. 4, in step S204, an etching process is performed to sequentially remove portions of the first dielectric layer 550 and the first conductive layer 530 on the cell region 500 and the low-voltage device region 620, so as to expose the surface of the low-voltage gate dielectric layer 560 (which may be regarded as a second gate dielectric layer). The patterned masking layer 470 is then removed.
Referring to fig. 2D and fig. 4, in step S204, a wet etching process is performed to remove the low-voltage gate dielectric layer 560 on the cell region 500 and the low-voltage device region 620. A portion of the first conductive layer 530 and a portion of the low-voltage gate dielectric layer 560 under the first conductive layer 530 may be consumed in the wet etching process, such that a recess R3 is formed on the side of the remaining first conductive layer 530 and the side of the remaining low-voltage gate dielectric layer 560.
Referring to fig. 2E and fig. 4, in step S204, a tunneling dielectric layer 520 (which may be regarded as a third gate dielectric layer) is formed on the substrate 400. Tunneling dielectric layer 520 covers the surface of first dielectric layer 550 and a portion of the top surface of substrate 400. In other words, the tunneling dielectric layer 520 does not cover the side surfaces of the remaining first conductive layer 530. The materials, formation method and thickness of the tunneling dielectric layer 520 are as described above for the tunneling dielectric layer 520 of the first embodiment, and are not described in detail herein.
Referring to fig. 2E, fig. 2F and fig. 4, step S204 is performed to form a second conductive layer 570 on the substrate 400. Specifically, second conductor layer 570 covers the surface of tunneling dielectric layer 520 and the sides of the remaining first conductor layer 530. That is, the second conductive layer 570 is not only conformally formed on the surface of the tunneling dielectric layer 520, but also fills the recess R3. The material, forming method and thickness of the second conductive layer 570 are as described above for the second conductive layer 570 of the first embodiment, and are not described in detail herein.
Referring to fig. 2G, a patterned mask layer 480 is formed on the substrate 400. In detail, the patterned mask layer 480 covers the surface of the cell area 500 and a portion of the second conductive layer 570 of the low-voltage device area 620. In one embodiment, the patterned mask layer 480 is separated from the adjacent second conductive layer 570 by a distance D2. The distance of D2 may be, for example, 100nm to 300 nm.
Referring to fig. 2G, fig. 2H and fig. 4, step S205 is performed to perform an etching process to sequentially remove the second conductive layer 570, the tunneling dielectric layer 520 and the first dielectric layer 550, which are not covered by the patterned mask layer 480, so as to expose the surface of the first conductive layer 530. During the etching process, in order to completely remove the second conductive layer 570 conformal to the sidewalls of the first conductive layer 530, the portion of the first well region 420 not covered by the patterned mask layer 480, the first low-pressure well region 450 and the second low-pressure well region 460 (i.e., the substrate 400) are consumed by the etching process, thereby forming the recess R4. At this time, the sidewall of the second conductive layer 570, the sidewall of the tunneling dielectric layer 520, and the step-shaped opening 485a formed by the surface of the first well 420 and the recess R4; the sidewall of the second conductive layer 570, the sidewall of the tunneling dielectric layer 520, and the step-shaped opening 485b formed by the surface of the first low-voltage well 450 and the recess R4. The patterned masking layer 480 is then removed.
Referring to fig. 2I and 4, in step S206, a third conductive layer 580 and a second dielectric layer 590 are sequentially formed on the substrate 400 to fill the stepped openings 485a and 485 b. The materials, forming methods and thicknesses of the third conductive layer 580 and the second dielectric layer 590 are as described above for the third conductive layer 580 and the second dielectric layer 590 of the first embodiment, and will not be described in detail herein.
Referring to fig. 2J and fig. 4, step S207 is performed to form a plurality of trenches 19 in the substrate 400, wherein the plurality of trenches 19 extend into the substrate 400 through the second dielectric layer 590. More specifically, a plurality of trenches 19 are formed in the substrate 400 around the cell area 500, the high voltage device area 610, and the low voltage device area 620.
Referring to fig. 2K and fig. 4, step S207 is performed to form a plurality of isolation structures 490 in the trenches 19. The isolation structure 490 is located in the substrate 400 around the cell area 500, the high voltage device area 610 and the low voltage device area 620, and can be used to electrically isolate each device in the cell area 500, the high voltage device area 610 and the low voltage device area 620. Next, a memory array is formed on the cell area 400, which is well known to those skilled in the art and will not be described in detail herein.
It is noted that the present embodiment provides a method for fabricating a memory device without the step of forming a buffer oxide layer. Therefore, the present embodiment can avoid the problem of the remaining buffer oxide layer between the first conductive layer 530 and the third conductive layer 580 (i.e., the floating gate). Meanwhile, the embodiment can also simplify the process and reduce the production cost.
In addition, the manufacturing process of the memory device according to the second embodiment of the present invention is to form the high voltage gate dielectric layer 510 first and then form the low voltage gate dielectric layer 560 (step S202). Then, a tunnel dielectric layer 520 is formed (step S204). Compared with the formation sequence of the high-voltage gate dielectric layer 510 and the low-voltage gate dielectric layer 560, the tunneling dielectric layer 520 is formed later, so that the damage of the surface quality of the tunneling dielectric layer 520 caused by multiple photolithography processes can be avoided, and the product reliability is improved.
In addition, the order of the manufacturing process of the memory device of the present invention is not limited in terms of the process flow. For example, the method for manufacturing the memory device of the present invention may form the high voltage gate dielectric layer 510, then form the low voltage gate dielectric layer 560, and then form the tunneling dielectric layer 520; alternatively, high voltage gate dielectric layer 510 is formed first, followed by tunnel dielectric layer 520, and then low voltage gate dielectric layer 560.
In summary, the present invention provides a method for manufacturing a memory device, which integrates devices in a cell area and a peripheral area on the same chip by using a triple gate oxide process. In addition, the triple gate oxide layer process has no step of forming a buffer oxide layer, so that the problem of residual buffer oxide layer between floating gates can be avoided. Therefore, the manufacturing method of the memory element can reduce the resistance values of the floating grid and the contact window, and further improve the efficiency, the reliability and the yield of products. In addition, compared with the prior art, the manufacturing method of the memory element omits the step of forming the buffer oxide layer, so the manufacturing method of the memory element can simplify the process and reduce the production cost.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments disclosed, but rather, may be embodied in many other forms without departing from the spirit or scope of the present invention.

Claims (9)

1. A method of manufacturing a memory element, comprising:
a substrate having a first region, a second region, and a third region;
forming a first gate dielectric layer on the substrate in the first region;
forming a second gate dielectric layer on the substrate of the second region and the third region;
forming a first conductor layer on the substrate;
directly forming a first dielectric layer on the first conductor layer, wherein the first dielectric layer is made of a silicon nitride layer, and no oxide layer is formed between the first conductor layer and the first dielectric layer;
removing a portion of the first dielectric layer, a portion of the first conductor layer, and a portion of the second gate dielectric layer of the second region to expose a portion of the surface of the substrate of the second region;
removing a portion of the first dielectric layer, a portion of the first conductor layer, and a portion of the second gate dielectric layer of the third region to expose a portion of the surface of the substrate of the third region, wherein the step of removing the second region and the portion of the second gate dielectric layer of the third region comprises: performing a wet etching process to further remove a portion of the first conductive layer and the second gate dielectric layer under the portion of the first conductive layer, so that a recess is formed on a side surface of the remaining first conductive layer and a side surface of the remaining second gate dielectric layer;
sequentially forming a third gate dielectric layer and a second conductor layer on the substrate of the second region;
sequentially forming a third conductor layer and a second dielectric layer on the substrate; and
a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend through the second dielectric layer into the substrate.
2. The method for manufacturing a memory element according to claim 1, wherein the first conductor layer is in direct contact with the first dielectric layer.
3. The method of claim 1, wherein a recess is formed in the substrate in the second region simultaneously with the formation of the third gate dielectric layer and the second conductor layer, and the forming of one of the isolation structures comprises removing the substrate around the recess, the first conductor layer, and the third conductor layer and the second dielectric layer over the recess to form a trench; and filling an isolation material layer in the trench.
4. The method of manufacturing a memory element according to claim 1, wherein the second gate dielectric layer of the third region is a tunneling dielectric layer.
5. The method according to claim 1, wherein the step of sequentially forming the third gate dielectric layer and the second conductor layer on the substrate in the second region further comprises:
and sequentially forming the third gate dielectric layer and the second conductor layer on the substrate of the third region, wherein the third gate dielectric layer of the third region is a tunneling dielectric layer.
6. The method according to claim 5, wherein when the third gate dielectric layer and the second conductor layer are formed on the substrate in the second region and the third region, two grooves are simultaneously formed in the substrate in the second region and the third region, respectively, and the method of forming one of the plurality of isolation structures comprises: removing the substrate, the first conductor layer, the third conductor layer and the second dielectric layer around the grooves to form two trenches respectively; and filling an isolation material layer in the trenches.
7. The method of manufacturing a memory element according to claim 1, further comprising, before forming the first gate dielectric layer:
forming a deep well region with a first conductivity type in the substrate of the third region;
forming a first well region with a second conductive type on the deep well region; and
and forming two high-voltage well regions with the first conduction type on two sides of the deep well region respectively.
8. The method of manufacturing a memory element according to claim 1, wherein a thickness of the first gate dielectric layer, a thickness of the second gate dielectric layer, and a thickness of the third gate dielectric layer are different from each other.
9. The method of manufacturing a memory element according to claim 1, wherein a thickness of the first dielectric layer is 10nm to 40 nm.
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