CN114497211A

CN114497211A - Semiconductor structure and forming method thereof

Info

Publication number: CN114497211A
Application number: CN202011148796.7A
Authority: CN
Inventors: 蔡巧明
Original assignee: Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
Current assignee: Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2022-05-13

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate comprising a first region; forming a first gate on the first region; more than two second grid structures are formed on the first grid, the second grid structures comprise second grids, the materials of the second grids are different from those of the first grids, the second grid structures are located on the upper portion of the first grids and used for protecting the first grids, and in the mechanical chemical polishing process, the 'sinking' defect is not easy to generate, the purpose of improving the structural integrity of the first grids is achieved, and therefore the grid structures with more optimized performance are obtained.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the continuous development of integrated circuit manufacturing technology, in order to achieve faster operation speed, larger data storage capacity and more functions, integrated circuit chips are developed towards higher device density and higher integration level. Generally, a complete set of integrated circuits includes at least one first area device and at least one second area device integrated on the same semiconductor substrate, the second area device is formed in a second area for implementing the main functions of the integrated circuit, the input/output device is used for providing corresponding input signals for the second area device or outputting corresponding signals of the second area device, and the operating voltage of the input/output device is higher than that of the second area device. Due to the difference of the working voltages of the devices in the first area and the devices in the second area, the structures of the corresponding devices are different.

As integrated circuit technology continues to advance to the nanometer level or below, the design requirements of integrated circuits may become incompatible with the existing device processes, for example, the existing device performance cannot meet the circuit design requirements, and therefore new advanced processes are required to be introduced continuously to improve the device performance continuously.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.

To solve the above technical problem, the present invention provides a semiconductor structure, comprising: a substrate comprising a first region; a first gate electrode on the first region; and more than two second gate structures positioned on part of the first gate, wherein the second gate structures comprise second gates, and the materials of the second gates and the first gates are different.

Optionally, the resistivity of the material of the second gate is lower than the resistivity of the material of the first gate.

Optionally, the material of the second gate includes a metal; the metal comprises copper, aluminum or tungsten; the material of the first gate comprises polysilicon.

Optionally, the first gate has first doped ions therein; the first doping ions are N-type ions or P-type ions.

Optionally, the method further includes: and the modified layer is positioned on the surface of the first grid electrode and positioned between the second grid electrode structures.

Optionally, the material of the modification layer includes a metal silicide.

Optionally, the method further includes: the first source drain region is positioned in the first region on two sides of the first grid electrode; and second doped ions are arranged in the first source drain region.

Optionally, the substrate further comprises a second region.

Optionally, the method further includes: a third gate structure located over the second region; the third gate structure includes a third gate, the material of the third gate including a metal.

Optionally, the third gate structure further includes: and the third gate dielectric layer is positioned between the third gate and the second region.

Optionally, the material of the third gate dielectric layer includes a high-K dielectric material.

Optionally, the third gate structure further includes: the oxide layer is positioned between the second area and the third gate dielectric layer; and the metal compound layer is positioned between the third gate dielectric layer and the third gate.

Optionally, the method further includes: the second source drain regions are respectively positioned in the second regions at two sides of the third gate structure; and third doped ions are arranged in the second source drain region.

Optionally, a dimension of the second gate structure along a gate width direction is less than or equal to 2 micrometers.

Optionally, the method further includes: and the first gate dielectric layer is positioned between the first gate and the first region.

Optionally, the material of the first gate dielectric layer includes silicon oxide.

Optionally, the method further includes: and the second gate dielectric layer is positioned between the second gate and the first gate.

Optionally, the material of the second gate dielectric layer includes a high-K dielectric material.

Optionally, the method further includes: the oxide layer is positioned between the first grid electrode and the second grid electrode dielectric layer; and the metal compound layer is positioned between the second gate dielectric layer and the second gate.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising a first region; forming a first gate on the first region; and forming more than two second gate structures on the first gate, wherein the second gate structures comprise second gates, and the materials of the second gates and the first gates are different.

Optionally, the material of the first gate includes polysilicon.

Optionally, the method further includes: and forming a first gate dielectric layer between the first gate and the first region.

Optionally, the method for forming the first gate includes: forming a first gate layer on the first region; and patterning the first gate layer to form a first gate.

Optionally, the method for forming the first gate further includes: doping first doping ions in the first grid layer; the first doping ions are of an N type or a P type.

Optionally, the material of the second gate includes a metal.

Optionally, the second gate structure further includes a second gate dielectric layer located between the second gate and the first gate.

Optionally, the second gate structure further includes: the oxide layer is positioned between the first grid electrode and the second grid electrode dielectric layer; and the metal compound layer is positioned between the second gate dielectric layer and the second gate.

Optionally, the forming method of the second gate structure includes: forming more than two first dummy gate structures on the first gate, wherein the first dummy gate structures comprise first dummy gates; replacing the first dummy gate with the second gate.

Optionally, the method for forming the second gate structure further includes: forming an interlayer dielectric layer on the surface of the substrate, wherein the interlayer dielectric layer is also positioned on the side wall and the surface of the first grid electrode and the side wall of the first dummy grid electrode, and the interlayer dielectric layer exposes out of the first dummy grid electrode; etching to remove the first dummy gate, and forming a plurality of first grooves in the interlayer dielectric layer; and filling the first groove to form a second grid.

Optionally, a first dummy gate structure is formed while a first gate is formed; the method for forming the first gate and the first dummy gate structure comprises the following steps: forming a first gate layer on the first region; and etching part of the first gate layer to form the first gate and more than two first dummy gates on the first gate.

Optionally, the method for forming the first dummy gate structure includes: forming a first gate layer on the first region, and forming a first dummy gate layer on the surface of the first gate layer; and patterning the first dummy gate layer and the first gate layer to form a first gate and more than two first dummy gates on the first gate.

Optionally, the first dummy gate structure further includes: a first hard mask layer located on the first dummy gate; the method for forming the first dummy gate structure and the first gate further comprises: forming the first hard mask layer on the first dummy gate layer; etching the first pseudo gate layer by taking the first hard mask layer as a mask until the surface of the first gate layer is exposed to form a first pseudo gate; and etching the first gate layer exposed by the first dummy gate layer by using the first hard mask layer as a mask until the surface of the first region is exposed to form a first gate.

Optionally, the method for forming the first hard mask layer includes: and forming an initial first hard mask layer on the surface of the first pseudo gate layer, and etching the initial first hard mask layer until part of the surface of the first pseudo gate layer is exposed.

Optionally, after forming the first gate and before forming the second gate structure, the method further includes: and forming a first source drain region in the first region on two sides of the first grid electrode, wherein the first source drain region is internally provided with second doped ions.

Optionally, after forming the first dummy gate structure and before forming the second gate structure, the method further includes: and forming a modified layer on the surface of the first gate, wherein the modified layer is positioned between the first dummy gate structures.

Optionally, the material of the modification layer includes metal silicide; the forming process of the modified layer comprises a self-aligned metal silicification process.

Optionally, the substrate further comprises a second region; the forming method further includes: and forming a third gate structure on part of the second region, wherein the third gate structure comprises a third gate, and the material of the third gate is the same as that of the second gate.

Optionally, the forming method of the third gate structure includes: forming a second groove in the interlayer dielectric layer on the second area; and forming a third gate in the second groove.

Optionally, the forming method of the second trench includes: forming a second dummy gate structure on the second region before forming the interlayer dielectric layer, wherein the second dummy gate structure comprises a second dummy gate; the interlayer dielectric layer is also positioned on the side wall of the second dummy gate structure and exposes the top surface of the second dummy gate structure; and removing the second dummy gate, and forming the second groove in the interlayer dielectric layer.

Optionally, a third gate is formed in the second trench while a second gate is formed; the forming method of the second grid and the third grid comprises the following steps: forming a third grid material layer in the surface of the interlayer dielectric layer, the first groove and the second groove; and flattening the third grid material layer until the surface of the interlayer dielectric layer is exposed, and forming the second grid and the third grid.

Optionally, the process of planarizing the third gate material layer is a mechanical chemical polishing process.

Optionally, the second dummy gate structure forming method includes: and forming a second dummy gate material layer in the second region, and patterning the second dummy gate material layer to form the second dummy gate.

Optionally, the first dummy gate structure and the first gate are formed while the second dummy gate is formed; the first dummy gate structure, the first gate and the second dummy gate are formed by a method comprising: forming a first gate layer on the first region; forming a first dummy gate material layer on the first gate layer and on the second region; forming a first hard mask material layer on the first dummy gate material layer; etching the first hard mask material layer until part of the first dummy gate layer on the first region and part of the second region are exposed to form an initial first hard mask layer; etching the first dummy gate material layer on the first region by using the initial first hard mask layer until the surface of the first gate layer is exposed, forming a first dummy gate layer on a part of the first gate layer, and forming a second dummy gate layer on the second region; after forming a first dummy gate layer and a second dummy gate layer, removing part of the initial first mask layer, exposing part of the first dummy gate layer and part of the surface of the second dummy gate layer, and respectively forming a first hard mask layer on a first area and a second hard mask layer on a second area; etching the first pseudo gate layer by taking the first hard mask layer as a mask until part of the surface of the first gate layer is exposed to form a first pseudo gate; etching the first gate layer exposed by the first dummy gate layer by using the first hard mask layer as a mask until the surface of the first region is exposed to form a first gate; and etching the second pseudo gate layer by taking the second hard mask layer as a film plate until the surface of the second area is exposed to form a second pseudo gate.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

according to the forming method of the semiconductor structure in the technical scheme, the first grid electrode is formed on the first area, the more than two second grid electrode structures are formed on the first grid electrode, each second grid electrode structure comprises the second grid electrode, the materials of the second grid electrode and the first grid electrode are different, the second grid electrode structures are located on the upper portion of the first grid electrode and used for protecting the first grid electrode, in the mechanical chemical grinding process, the 'sinking' defect is not prone to being generated, the purpose of improving the integrity of the first grid electrode structure is achieved, and therefore the grid electrode structure with the optimized performance is obtained.

Furthermore, the size of the second gate structure along the width direction of the gate is less than or equal to 2 microns, so that the size of the second gate structure is smaller, and when the second gate material is planarized by adopting a mechanical chemical polishing process, a 'depression' defect is not easily generated on the surface of the second gate structure, so that the second gate is not abraded, the first gate below the second gate is further protected, and the performance of the first gate in the first region is improved.

Further, the material of the first gate electrode comprises polysilicon, and the material of the first gate dielectric layer comprises silicon oxide, so that the threshold voltage of the first gate electrode structure is lower.

Further, a modified layer is formed on the surface of the first gate, the modified layer is located between the second gate structures, and the modified region can reduce the contact resistance between the first gate and a subsequently formed conductive plug. In the planarization process, the modification layer is covered by the interlayer dielectric layer, and the dimension of the second grid structure along the width direction of the grid is less than or equal to 2 microns, so that the defect of 'depression' is not easy to generate, the modification layer is not easy to expose, and the abnormal occurrence of metal silicide polluting a mechanical chemical polishing machine and further polluting the performance of a device is avoided.

Drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure;

fig. 2 to 10 are schematic cross-sectional views corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention;

fig. 11 to 19 are schematic cross-sectional views illustrating steps of a semiconductor structure forming method according to another embodiment of the present invention.

Detailed Description

As described in the background, the performance of semiconductor structures formed in the prior art is subject to improvement. The description will be made with reference to the structure of a semiconductor.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure.

Referring to fig. 1, a substrate 100, the substrate 100 includes a base 101, a first region i and a second region ii on the base 101, and an isolation structure 102 in the substrate 100; a polysilicon gate 103 positioned on the first region I, and a metal gate 104 positioned on the second region II; a first source drain region 105 located in the first region i on both sides of the polysilicon gate 103, and a second source drain region 106 located in the second region ii on both sides of the metal gate 104; and the interlayer dielectric layer 107 is positioned on the substrate 100, and the interlayer dielectric layer 107 is also respectively positioned on the sidewalls of the polysilicon gate 103 and the metal gate 104.

When the structure is used in a circuit integrating low-voltage, medium-voltage and high-voltage devices, the second area II is used for forming the low-voltage devices, the low-voltage devices adopt metal gates due to small sizes, the first area I is used for the medium-voltage and high-voltage devices, the size of the polysilicon gate 103 on the first area I is usually larger than 2 micrometers, and the size of the metal gate is usually smaller than 2 micrometers. Forming the metal gate 104 generally requires first planarizing to form a gate opening in the interlayer dielectric layer 107, forming a metal material layer on the gate opening and the surface of the interlayer dielectric layer 107, and planarizing the metal material layer until the interlayer dielectric layer 107 and the polysilicon gate 103 are exposed to form the metal gate 104. In the planarization process, the polysilicon gate 103 is easy to form a 'recess' defect due to a large size, and even the polysilicon gate 103 is worn out, so that the polysilicon gate 103 is damaged or failed, and the performance of the device is affected. The "dishing" defect refers to the phenomenon that the middle part of a large-sized pattern is easily over-grinded to generate "dishing" in the mechanochemical grinding process.

In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a first gate is formed on a first region, two or more second gate structures are formed on the first gate, the second gate structures include a second gate, the materials of the second gate and the first gate are different, the second gate structure is located above the first gate and is used for protecting the first gate, and in the process of mechanochemical polishing, a "dishing" defect is not easily generated, so as to achieve the purpose of improving the integrity of the first gate structure, thereby obtaining a gate structure with more optimized performance.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 10 are schematic cross-sectional views corresponding to steps in a semiconductor structure forming method according to an embodiment of the invention.

Referring to fig. 2, a substrate 200 is provided, the substrate including a first region 201.

In this embodiment, the substrate 200 further includes: a base 202, an isolation structure 203 located on the upper portion of the substrate 200, and a deep well 204 located in the substrate 200. The isolation structure 203 is used to electrically isolate different devices of the semiconductor. The deep well 204 is used for isolating noise generated by the outside on devices formed on a subsequent substrate.

The material of the substrate 202 comprises monocrystalline silicon and the material of the isolation structure 203 comprises silicon oxide.

In this embodiment, the deep well 204 is an N-type well, and the forming method thereof includes: implanting phosphorus as ions into the substrate along a direction perpendicular to the substrate 200 at an implantation energy of 10KeV to 3000KeV and an implantation dose of 10KeV¹²cm^-2To 10¹⁴cm^-2To form the deep well 204. In other embodiments, the deep well implants boron ions into the substrate to form a P-well.

Referring to fig. 3, a first gate layer 205 is formed on the first region 201.

The material of the first gate layer 205 comprises polysilicon.

In this embodiment, the first gate layer 205 further has first doping ions therein, and the first doping ions are N-type or P-type. The doping method of the doping ions comprises ion implantation. In this embodiment, the first gate layer 205 is used for forming a first gate later. In other embodiments, the first gate layer is further used to form a first dummy gate over the first gate. The first doping ions can adjust the threshold voltage of the first grid electrode and reduce the resistance value of the first grid electrode.

In this embodiment, before forming the first gate layer 205, forming a first gate dielectric material layer 206 on the surface of the first region 201 is further included.

The material of the first gate dielectric material layer 206 includes silicon oxide. The first gate dielectric material layer 206 is used for forming a first gate dielectric layer.

Referring to fig. 4, a first dummy gate layer 207 is formed on the surface of the first gate layer 205.

The method of the first dummy gate layer 207 comprises: forming a first dummy gate material layer on the surface of the first gate layer 205, and patterning the first dummy gate material layer to form the first dummy gate layer 207. The first dummy gate layer 207 is used for forming a first dummy gate.

The material of the first dummy gate layer 207 includes silicon.

In this embodiment, the first dummy gate layer 207 further has an initial first hard mask layer 208 thereon; an initial second gate dielectric layer 209 is also located between the first gate layer 205 and the first dummy gate layer 207. The method for forming the initial first hard mask layer 208, the first dummy gate layer 207 and the initial second gate dielectric layer 209 includes: before forming the first dummy gate material layer, forming a second gate dielectric material layer on the surface of the first gate layer 205; forming a first hard mask material layer on the first dummy gate material layer; and etching the first hard mask material layer to form an initial first hard mask layer 208, etching the first dummy gate material layer by using the initial first hard mask layer 208 as a mask until the surface of the first gate layer 205 is exposed to form the first dummy gate layer 207, and etching the second gate dielectric material layer to form the initial second gate dielectric layer 209.

In other embodiments, an initial second gate dielectric layer is located between the first gate layer and the first dummy gate layer, and the initial first hard mask layer is not included on the first dummy gate layer; or the first dummy gate layer is positioned between the first gate layer and the first dummy gate layer and is not provided with an initial second gate dielectric layer, and the first dummy gate layer is provided with an initial first hard mask layer; or only the first dummy gate layer is positioned on the first gate layer, and the initial first hard mask layer and the initial second gate dielectric layer are not included.

And the process for etching the first hard mask material layer, the first dummy gate material layer and the second gate dielectric material layer comprises a dry etching process.

The material of the initial first hard mask layer 208 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. The initial first hard mask layer 208 is subsequently used to form a first hard mask layer 214.

The material of the second gate dielectric layer 209 includes a high-K dielectric material. The high-K (dielectric constant K ≧ 3.9) dielectric material comprises HfO₂。

Referring to fig. 5, the first dummy gate layer 207 (shown in fig. 4) and the first gate layer 205 are patterned to form a first gate 210 and two or more first dummy gates 212 on the first gate 210.

The first dummy gate structure 213 includes a first dummy gate 212.

In this embodiment, the first dummy gate structure 213 further includes: a first hard mask layer 214 on the first dummy gate 212, and a second gate dielectric layer 215 between the first gate 210 and the first dummy gate 212. In other embodiments, the first dummy gate structure includes a first dummy gate and a first hard mask layer on the first dummy gate, but does not include a second gate dielectric layer between the first dummy gate and the first gate; or the first dummy gate and the second gate dielectric layer positioned between the first dummy gate and the first gate are included, but the first hard mask layer positioned on the first dummy gate is not included; or the first dummy gate structure comprises a first dummy gate, but does not comprise a second gate dielectric layer positioned between the first dummy gate and the first gate and a first hard mask layer positioned on the first dummy gate.

The forming method of the first hard mask layer 214 comprises the following steps: the initial first hard mask layer 208 is etched (as shown in fig. 4) until a portion of the surface of the first dummy gate layer 207 is exposed.

The process of etching the initial first hard mask layer 208 includes a dry etch process.

The method for forming the first dummy gate structure 213 and the first gate 210 includes: etching the first dummy gate layer 207 (as shown in fig. 4) by using the first hard mask layer 214 as a mask until a part of the surface of the first gate layer 205 (as shown in fig. 4) is exposed, so as to form the first dummy gate 212; after the first dummy gate 212 is formed, etching the initial second gate dielectric layer 209 (as shown in fig. 4) to form a second gate dielectric layer 215; and etching the first gate layer 205 exposed by the first dummy gate layer 207 by using the first hard mask layer 214 as a mask until the surface of the first region 201 is exposed, thereby forming a first gate 210. In this embodiment, the first gate 210 and the first dummy gate 212 are etched and formed at the same time, so that the production process is saved.

In other embodiments, the method for forming the first dummy gate and the first gate includes: and etching part of the first gate layer to form a first gate and more than two first dummy gates on the first gate.

Referring to fig. 6, first source-drain regions 216 are formed in the first region 201 on both sides of the first gate 210, and the first source-drain regions 216 have second doped ions therein.

The second doped ions are N-type or P-type ions.

A channel of the first region device is formed in a region between the first source-drain regions 216 and below the first gate 210, and the direction of the gate width refers to the channel length direction.

Referring to fig. 7, a modified layer 217 is formed on the surface of the first gate 210, and the modified layer 217 is located between the first dummy gate structures 213.

In this embodiment, a contact layer 218 is further formed on the surface of the first source drain region 216.

The material of the modified layer 217 and the contact layer 218 is metal silicide. The resistance of the modification layer 217 and the contact layer 218 is small. The contact layer 218 can reduce contact resistance between the first source drain region 216 and a subsequently formed conductive plug; the modified layer 217 may reduce contact resistance between the first gate 210 and a subsequently formed conductive plug.

The forming process of the modified layer 217 and the contact layer 218 includes a salicidation process. In this embodiment, the modification layer 217 and the contact layer 218 are formed simultaneously.

Referring to fig. 8, an interlayer dielectric layer 219 is formed on the surface of the substrate 200, the interlayer dielectric layer 219 is further located on the sidewall and the surface of the first gate 210 and the sidewall of the first dummy gate 212, and the interlayer dielectric layer 219 exposes the first dummy gate 212.

The forming method of the interlayer dielectric layer 219 comprises the following steps: forming an interlayer dielectric material film on the surface of the substrate 200, the side wall of the first gate 210, the side wall and the top of the dummy gate structure 213; and flattening the interlayer dielectric material film until the top surface of the first dummy gate 212 is exposed to form the interlayer dielectric layer 219. In this embodiment, the interlayer dielectric layer 320 is further located on the surface of the contact layer 218 and the sidewall of the first gate dielectric layer 211. In this embodiment, the planarization process exposes the top surface of the first dummy gate 212. In other embodiments, the planarization process may thin the first dummy gate.

The interlayer dielectric layer 219 is used for isolating a metal interconnection line and a device in a subsequent device manufacturing process, reducing parasitic capacitance between metal and a substrate, and improving the phenomenon that the metal crosses different regions to form a parasitic field effect transistor.

The planarization process includes a mechanochemical polishing process.

Referring to fig. 9, the first dummy gate 212 is etched away (as shown in fig. 8), and a plurality of first trenches 220 are formed in the interlayer dielectric layer 219.

The method for removing the first dummy gate 212 by etching includes one or both of dry etching and wet etching.

In this embodiment, the second gate dielectric layer 215 is exposed at the bottom of the first trench 220, and the interlayer dielectric layer 219 is exposed at the sidewall. In other embodiments, the bottom of the first trench exposes the first gate, and the sidewall exposes the interlayer dielectric layer.

In this embodiment, the method for removing the first dummy gate 212 by etching is a wet etching process.

The solution adopted by the wet etching process includes a tetramethylammonium hydroxide or potassium hydroxide solution, so that the first dummy gate 212 has a larger etching selectivity relative to the interlayer dielectric layer 219 and the second gate dielectric layer 215 in the etching process of removing the dummy gate 212.

Referring to fig. 10, a second gate 221 is formed by filling the first trench 220 (shown in fig. 9).

The second gate structure 222 includes a second gate 221. In this embodiment, the second gate structure 222 further includes a second gate dielectric layer 215 between the second gate 221 and the first gate 210. In other embodiments, the second gate structure includes the second gate 221, but does not include the second gate dielectric layer 215 between the second gate 221 and the first gate 210.

The method for forming the second gate 221 includes: filling the first trench 220 with a second gate material layer; and planarizing the second gate material layer to form the second gate 221 until the surface of the interlayer dielectric layer 219 is exposed. During the planarization process, the interlevel dielectric layer 219 may be lossy.

The process of filling the first trench 220 with the second gate material layer includes an atomic layer deposition process, a physical vapor deposition process, or an electroplating process. In this embodiment, the process of filling the first trench 220 with the second gate material layer is a physical vapor deposition process.

The material of the second gate 221 includes metals, such as: copper, aluminum or tungsten.

The dimension of the second gate structure 222 along the gate width direction is less than or equal to 2 microns.

The process for planarizing the second gate material layer includes a mechanochemical polishing process. Because the second gate structure 222 is small in size, the surface of the second gate structure 222 is not prone to generate a 'concave' defect, so that the first gate 210 below the second gate structure is protected, the situation that the first gate 210 is worn out does not occur, and the performance of the device is improved.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 10, including: a substrate 200, said substrate 200 comprising a first region 201; a first gate 210 on the first region 201; and two or more second gate structures 222 located on a portion of the first gate 210, wherein the second gate structures 222 include a second gate 221, and the second gate 221 and the first gate 210 are made of different materials.

The resistivity of the material of the second gate 221 is lower than the resistivity of the material of the first gate 210.

The material of the second gate electrode 221 includes a metal; the metal comprises copper, aluminum or tungsten; the material of the first gate 210 comprises polysilicon.

The first gate 210 has first doped ions therein; the first doping ions are N-type ions or P-type ions.

A modified layer 217 on the surface of the first gate 210, the modified layer being located between the second gate structures 222.

The material of the modified layer 217 comprises a metal silicide.

The first source-drain regions 210 are positioned in the first regions 200 at two sides of the first gate 210; the first source drain region 210 has second doped ions therein.

The semiconductor structure further includes: a first gate dielectric layer 211 located between the first gate 210 and the first region 201.

The material of the first gate dielectric layer 211 includes silicon oxide.

The semiconductor structure further includes: a second gate dielectric layer 215 between the second gate 221 and the first gate 210.

The material of the second gate dielectric layer 215 includes a high-K dielectric material.

The semiconductor structure further includes: an oxide layer between the first gate 210 and the second gate dielectric layer 215; a metal compound layer between the second gate dielectric layer 215 and the second gate electrode 221.

Fig. 11 to 18 are schematic cross-sectional views of semiconductor structures formed in the method of forming a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 11, a substrate 300 is provided, the substrate 300 including a first region 301 and a second region 302.

In this embodiment, the first region 301 is used to form first region devices; the second region 302 is used to form second region devices.

The substrate 300 further includes: a base 303, a deep well 304 in the substrate 300 and an insulating isolation structure 305 on top of the substrate 300. The isolation structure is used for realizing electric insulation between different devices of the semiconductor. The deep well 304 is used to isolate noise generated by the outside world for devices formed on subsequent substrates.

The material of the substrate 303 comprises monocrystalline silicon and the material of the isolation structure 305 comprises silicon oxide.

In this embodiment, the deep well 304 is an N-type well, and the forming method thereof includes: implanting ions of phosphorus into the substrate along the direction vertical to the substrate 200, with the implantation energy of 10 KeV-3000 KeV and the implantation dosage of 10KeV¹²cm^-2～10¹⁴cm^-2To form the deep well 304. In other embodiments, the deep well implants boron ions into the substrate to form a P-well.

Subsequently forming a first gate on the first region 301, and forming more than two first dummy gate structures on the first gate, wherein the first dummy gate structures comprise first dummy gates; a second dummy gate structure is formed on the second region 302, the second dummy gate structure including a second dummy gate. The formation processes of the first gate, the first dummy gate structure and the second dummy gate structure are as shown in fig. 12 to 15.

Referring to fig. 12, a first gate layer 306 is formed on the first region 301.

The material of the first gate layer 306 comprises polysilicon. In other embodiments, the first gate layer is further covered on the second region and is used for forming a second dummy gate on the second region.

In this embodiment, the first gate layer 306 further has first doping ions therein, and the first doping ions are N-type or P-type. The doping method of the doping ions comprises ion implantation. The first dopant ions may adjust a threshold voltage of a subsequently formed semiconductor device.

In this embodiment, the first gate layer 306 is used for forming a first gate. In other embodiments, the first gate layer is further used to form a first dummy gate layer on the first gate and a second dummy gate on the second region.

In this embodiment, before forming the first gate layer 306, forming a first gate dielectric material layer 307 on the surface of the first region 301 is further included.

The material of the first gate dielectric material layer 307 comprises silicon oxide. The first gate dielectric material layer 307 is used for forming a first gate dielectric layer subsequently.

Referring to fig. 13, a first dummy gate material layer 308 is formed on the first gate layer 306 and on the second region 302; a first hard mask material layer 401 is formed on the first dummy gate material layer 308.

The material of the first dummy gate material layer 308 includes silicon. The first dummy gate material layer 308 is used to subsequently form a first dummy gate on the first region 301 and a second dummy gate on the second region 302.

In this embodiment, the method further includes: before forming the first dummy gate material layer 308, a second gate dielectric material layer 310 is formed on the first gate layer 306 and on the second region 302.

The material of the second gate dielectric material layer 310 includes a high-K dielectric material. The second gate dielectric material layer 310 is used for forming a second gate dielectric layer and a third gate dielectric layer in a subsequent step. The high-K (dielectric constant K ≧ 3.9) material comprises HfO₂. The third gate dielectric layer can obviously reduce the quantum tunneling effect of the gate dielectric layer, so that the leakage current of the third gate and the power consumption caused by the leakage current can be effectively improved. In other embodiments, an oxide layer is further disposed between the second region and the second gate dielectric material layer, and the material of the oxide layer includesAnd the aim of the silicon oxynitride is to improve the interface state of the second gate dielectric material layer and the second region. In other embodiments, the metal compound layer is located between the second gate dielectric material layer and the first dummy gate material layer, and the material of the metal compound layer includes titanium nitride for adjusting the threshold voltage of a subsequently formed device.

The hard mask material layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and other insulating materials. The hard mask material layer 401 is used for the subsequent formation of a first hard mask layer and a second hard mask layer.

In this embodiment, the first gate dielectric material layer 307 for forming the first gate dielectric layer and the second gate dielectric material layer 310 for forming the third gate dielectric layer are formed twice, and the materials used are different, the first gate dielectric material layer 307 is an oxide layer, that is, the first gate dielectric layer formed subsequently is an oxide layer, so that the threshold voltage of the first gate structure formed subsequently is lower. If the first gate dielectric material layer 307 and the second gate dielectric material layer 310 are formed simultaneously by using the same material, and if both high-K dielectric materials are used as gate dielectric layers, the threshold voltage of the first gate structure is higher, which cannot meet the requirements of devices.

Referring to fig. 14, the first hard mask material layer 401 is etched until a portion of the first dummy gate material layer 308 on the first region 301 and a portion of the second region 302 are exposed to form an initial first hard mask layer 309; and etching the first dummy gate material layer 308 on the first region 301 by using the initial first hard mask layer 309 until the surface of the first gate layer 306 is exposed, forming a first dummy gate layer 311 on a portion of the first gate layer 306, and forming a second dummy gate layer 312 on the second region 302.

The process of etching the first hard mask material layer 401 includes a dry etching process.

The process of etching the first dummy gate material layer 308 on the first region 301 includes a dry etching process.

The first dummy gate layer 311 is used for forming a first dummy gate. The second dummy gate layer 312 is used to subsequently form a second dummy gate.

In this embodiment, the second gate dielectric material layer 310 is etched to form an initial second gate dielectric layer 313, and an initial third gate dielectric layer 314 on the second region 302 is formed at the same time.

Referring to fig. 15, the first dummy gate layer 311 (shown in fig. 14) and the first gate layer 306 (shown in fig. 14) are patterned to form a first gate 315 and two or more first dummy gates 316 on the first gate 315; the second dummy gate layer 312 is patterned (as shown in fig. 14) to form a second dummy gate 317.

The first dummy gate structure 318 includes a first dummy gate 316.

In this embodiment, the first dummy gate structure 318 further includes: a first hard mask layer 319 on the first dummy gate 316, and a second gate dielectric layer 320 between the first gate 315 and the first dummy gate 316. In other embodiments, the first dummy gate structure includes a first dummy gate and a first hard mask layer on the first dummy gate, but does not include a second gate dielectric layer between the first dummy gate and the first gate; or the first dummy gate and the second gate dielectric layer positioned between the first dummy gate and the first gate are included, but the first hard mask layer positioned on the first dummy gate is not included; or the first dummy gate is included, but the second gate dielectric layer positioned between the first dummy gate and the first hard mask layer positioned on the first dummy gate are not included.

The second dummy gate structure 321 includes a second dummy gate 317.

In this embodiment, the second dummy gate structure 321 further includes: a second hard mask layer 322 on the second dummy gate 317, and a third gate dielectric layer 323 between the second region 302 and the second dummy gate 317. In other embodiments, the second dummy gate structure includes a second dummy gate and the second hard mask layer located on the second dummy gate, but does not include the third gate dielectric layer located between the second region and the second dummy gate; or the second dummy gate structure includes a second dummy gate and the third gate dielectric layer between the second region and the second dummy gate, but does not include a second hard mask layer on the second dummy gate, or the second dummy gate structure includes a second dummy gate, but does not include the second hard mask layer and the third gate dielectric layer.

The formation of the first hard mask layer 319 and the second hard mask layer 322 may include: a portion of the initial first mask layer 309 is removed to expose a portion of the first dummy gate layer 311 and a portion of the second dummy gate layer 312, and a first hard mask layer 319 on the first region 301 and a second hard mask layer 322 on the second region 302 are formed, respectively.

The forming method of the first dummy gate structure 318, the second dummy gate structure 321 and the first gate 315 includes: etching the first dummy gate layer 311 (as shown in fig. 14) by using the first hard mask layer 319 as a mask until a portion of the surface of the first gate layer 306 (as shown in fig. 14) is exposed, so as to form the first dummy gate 316; etching the first gate layer 306 exposed by the first dummy gate layer 311 by using the first hard mask layer 319 as a mask until the surface of the first region 301 is exposed, so as to form a first gate 315; and etching the second dummy gate layer 312 by using the second hard mask layer 322 as a mask until the surface of the second region 302 is exposed, thereby forming a second dummy gate 317. In this embodiment, the first dummy gate 316, the first gate 315, and the second dummy gate 317 are formed by etching at the same time, so that the production process is saved, and the production cost is reduced.

In this embodiment, the method further includes: the first gate dielectric material layer 307 (shown in fig. 14) is etched to form a first gate dielectric layer 324; the initial second gate dielectric layer 313 (shown in fig. 14) is etched to form a second gate dielectric layer 320; the initial third gate dielectric layer 314 (shown in fig. 14) is etched to form a third gate dielectric layer 323.

The process of forming the first gate 315, the first dummy gate structure 318, and the second dummy gate structure 321 by etching is a dry etching process.

Referring to fig. 16, forming first source drain regions 325 in the first region 301 on two sides of the first gate 315, where the first source drain regions 325 have second doped ions therein; forming second source and drain regions 326 in the second region 302 on two sides of the second dummy gate structure 321, wherein the second source and drain regions 326 have third doped ions therein; modified layers 327 are formed on the surface of the first gate 315, and the modified layers 327 are located between the first dummy gate structures 318.

In this embodiment, the method further includes: and forming a contact layer 328 on the surfaces of the first source drain region 325 and the second source drain region 326.

The material of the modified region 327 is a metal silicide. The first gate 315 is connected to an external circuit through a conductive plug formed subsequently on the modified region 327. The modified region 327 has a smaller resistance, and the modified region 327 can reduce the contact resistance between the first gate 315 and a conductive plug to be formed later.

The material of the contact layer 328 is a metal silicide. The contact layer 328 has a lower resistance, which can reduce the contact resistance between the first source drain region 325 and the second source drain region 326 and the subsequently formed conductive plug.

The formation process of the modified layer 327 and the contact layer 328 includes a salicidation process. In this embodiment, the modified layer 327 and the contact layer 328 are formed by a single process, which saves process steps and reduces production cost. Forming an interlayer dielectric layer on the surface of the substrate 300; and after the interlayer dielectric layer is formed, flattening the interlayer dielectric layer until the second dummy gate is exposed. In the planarization process, since the modified layer 327 and the contact layer 328 are covered by the interlayer dielectric layer, and the size of the first dummy gate structure 318 along the gate width direction is less than or equal to 2 μm, a "dishing" defect is not easily generated, so that the modified layer 327 and the contact layer 328 are not easily exposed, and an abnormal occurrence of metal silicide contaminating a mechanical chemical polishing machine and further contaminating the device performance is avoided.

Referring to fig. 17, an interlayer dielectric layer 329 is formed on the surface of the substrate 300, the interlayer dielectric layer 329 is further disposed on the sidewall and the surface of the first gate 315 and the sidewall of the first dummy gate 316, the interlayer dielectric layer 329 exposes the first dummy gate 316, and the interlayer dielectric layer 329 is further disposed on the sidewall of the second dummy gate 317 and exposes the top surface of the second dummy gate 317.

The forming method of the interlayer dielectric layer 329 comprises the following steps: forming a film of interlayer dielectric material on the surface of the substrate 300, on the sidewalls of the first gate 315, on the sidewalls and tops of the dummy gate structures 318 (shown in FIG. 16), and on the sidewalls and tops of the second dummy gate structures 321 (shown in FIG. 16); the interlayer dielectric material film is planarized until the top surfaces of the first dummy gate 316 and the second dummy gate 317 are exposed, forming the interlayer dielectric layer 329. In this embodiment, the interlayer dielectric layer 329 is further disposed on the surface of the contact layer 328 and the surface of the modified region 327.

The interlayer dielectric layer 329 is used for isolating a metal interconnection line and a device in a subsequent device manufacturing process, reducing the parasitic capacitance between the metal and the substrate and improving the parasitic field effect transistor formed by the metal crossing different areas.

In other embodiments, the planarization process may cause the first dummy gate to be thinned.

In this embodiment, the planarization process is a mechanical chemical polishing process. In the mechanochemical polishing process, the larger the size of the polished area, the more easily the "dishing" defect is generated, and the deeper the "dishing" defect is, even leading to a situation that the polished area is partially worn out. The dimension of the first gate 315 in the gate width direction is greater than 10 μm, and the dimension of the first dummy gate structure 318 in the gate width direction is less than or equal to 2 μm. In the planarization process, the first hard mask layer 319 on the first dummy gate structure 318 has a higher wear resistance than the interlayer dielectric layer 329, and protects the first dummy gate structure 318. Moreover, because the first dummy gate structure 318 has a small size, a 'recess' defect is not easily generated on the surface of the first dummy gate structure 318, so that the first gate 315 therebelow is protected, and the situation that the first gate 315 is worn down cannot occur. During the planarization process, the first dummy gate structure 318 may be thinned, but as long as a portion of the first dummy gate structure 318 remains, the first gate 315 is not worn down.

Referring to fig. 18, the first dummy gate 316 is etched away, and a plurality of first trenches 330 are formed in the interlayer dielectric layer 329; and removing the second dummy gate 317, and forming the second trench 331 in the interlayer dielectric layer.

The method for removing the first dummy gate 316 and the second dummy gate 317 by etching includes one or both of dry etching and wet etching. In this embodiment, the method for removing the first dummy gate 316 and the second dummy gate 317 by etching is a wet etching process.

In this embodiment, the second gate dielectric layer 320 is exposed at the bottom of the first trench 330; the third gate dielectric layer 323 is exposed at the bottom of the second trench 331.

The solution adopted by the wet etching process comprises a tetramethyl ammonium hydroxide or potassium hydroxide solution. Therefore, in the etching process of removing the first dummy gate 316, the first dummy gate 316 can have a larger etching selection ratio relative to the interlayer dielectric layer 329 and the second gate dielectric layer 320; in the etching process of removing the second dummy gate 316, the second dummy gate 317 can have a larger etching selection ratio relative to the interlayer dielectric layer 329 and the third gate dielectric layer 323.

Referring to fig. 19, a second gate 332 is formed by filling the first trench 330; a third gate 333 is formed in the second trench 331 at the same time as the second gate 332 is formed.

The second gate structure 334 of this embodiment includes a second gate 332 and a second gate dielectric layer 320 located between the second gate 332 and the first gate 315. In other embodiments, the second gate structure includes a second gate but does not include a second gate dielectric layer.

The third gate structure 336 of this embodiment includes a third gate 333 and a third gate dielectric layer 323 located on the third gate 333 and the second region 302. In other embodiments, the third gate structure includes a third gate but does not include a third gate dielectric layer.

Forming a third gate material layer on the surface of the interlayer dielectric layer 329, in the first trench 330 and in the second trench 331; and flattening the third gate material layer until the surface of the interlayer dielectric layer 329 is exposed to form the second gate 332 and the third gate 333. During the planarization process, the interlayer dielectric layer 329 may be thinned.

The process of planarizing the third gate material layer is a mechanochemical grinding process.

The process of filling the first trench 330 and the second trench 331 with the second gate material layer includes an atomic layer deposition process or a physical vapor deposition process.

The materials of the second gate 332 and the third gate 333 include metals, such as: copper, aluminum or tungsten.

The size of the first gate 315 in the gate width direction is greater than 10 μm, and the size of the second gate 332 in the gate width direction is less than or equal to 2 μm.

The process for planarizing the second gate material layer includes a mechanochemical polishing process. Because the second gate 332 is small in size, a 'recess' defect is not easily generated in the second gate 332, so that the first gate 315 below the second gate is protected, the situation that the first gate 315 is worn out does not occur, and the performance of the device is improved.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 19, including: a substrate 300 comprising a first region 301 and comprising a second region 302; a first gate 315 located on the first region 301; two or more second gate structures 334 on a portion of the first gate 315, the second gate structures 334 including a second gate 332, the second gate 332 and the first gate 315 being of different materials; a third gate structure 335 on the second region 302, the third gate structure 335 comprising a third gate 333, the material of the third gate 333 comprising a metal.

The resistivity of the material of the second gate 332 is lower than the resistivity of the material of the first gate 315.

The material of the second gate 332 includes a metal; the metal comprises copper, aluminum or tungsten; the material of the first gate 315 comprises polysilicon.

The first gate 315 has first doped ions therein; the first doping ions are N-type ions or P-type ions.

The semiconductor structure further includes: and the modified layer 327 is positioned on the surface of the first gate 315, and the modified layer 327 is positioned between the second gate structures 334.

The material of the modified layer 327 includes a metal silicide.

The semiconductor structure further includes: the first source drain region 325 is located in the first region 301 on two sides of the first gate 315, and the first source drain region 325 has second doped ions therein.

The first source-drain region 325 is made of silicon carbide, and the second doped ions are N-type ions; the material of the first source drain region 325 includes silicon germanium, and the second dopant ions are P-type ions.

The third gate structure 335 further comprises: and a third gate dielectric layer 323 positioned between the third gate 333 and the second region 302.

The material of the third gate dielectric layer 323 comprises a high-K dielectric material.

The third gate structure 335 further comprises: an oxide layer located between the second region 302 and the third gate dielectric layer 323; and the metal compound layer is positioned between the third gate dielectric layer 323 and the third gate 333.

The semiconductor structure further comprises: second source-drain regions 326 in the second region 302 at two sides of the third gate structure 335, respectively; the second source drain region 326 has third doping ions therein.

A contact layer 328 positioned on the surfaces of the first source drain region 325 and the second source drain region 326; the material of the contact layer 328 is a metal silicide.

The dimension of the second gate structure 334 along the gate width direction is less than or equal to 2 microns.

The semiconductor structure further comprises: a first gate dielectric layer 324 between the first gate 315 and the first region 301.

The material of the first gate dielectric layer 324 comprises silicon oxide.

The semiconductor structure further comprises: and a second gate dielectric layer 320 between the second gate 332 and the first gate 315.

The material of the second gate dielectric layer 320 includes a high-K dielectric material.

The semiconductor structure further comprises: the oxide layer is positioned between the first grid electrode 315 and the second grid electrode dielectric layer 320; a metal compound layer between the second gate dielectric layer 320 and the second gate 332.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first region;

a first gate located on the first region;

and more than two second gate structures positioned on part of the first gate, wherein the second gate structures comprise second gates, and the materials of the second gates and the first gates are different.

2. The semiconductor structure of claim 1, wherein a material of the second gate has a lower resistivity than a material of the first gate.

3. The semiconductor structure of claim 2, wherein a material of the second gate comprises a metal; the metal comprises copper, aluminum or tungsten; the material of the first gate comprises polysilicon.

4. The semiconductor structure of claim 3, wherein the first gate has first dopant ions therein; the first doping ions are N-type ions or P-type ions.

5. The semiconductor structure of claim 1, further comprising: and the modified layer is positioned on the surface of the first grid electrode and positioned between the second grid electrode structures.

6. The semiconductor structure of claim 5, in which a material of the modification layer comprises a metal silicide.

7. The semiconductor structure of claim 1, further comprising: the first source drain region is positioned in the first region on two sides of the first grid electrode; and second doped ions are arranged in the first source drain region.

8. The semiconductor structure of claim 1, wherein the substrate further comprises a second region.

9. The semiconductor structure of claim 8, further comprising: a third gate structure located over the second region; the third gate structure includes a third gate, the material of the third gate including a metal.

10. The semiconductor structure of claim 9, wherein the third gate structure further comprises: and the third gate dielectric layer is positioned between the third gate and the second region.

11. The semiconductor structure of claim 10, wherein a material of the third gate dielectric layer comprises a high-K dielectric material.

12. The semiconductor structure of claim 11, wherein the third gate structure further comprises: the oxide layer is positioned between the second area and the third gate dielectric layer; and the metal compound layer is positioned between the third gate dielectric layer and the third gate.

13. The semiconductor structure of claim 9, further comprising: the second source drain regions are respectively positioned in the second regions at two sides of the third gate structure; and third doped ions are arranged in the second source drain region.

14. The semiconductor structure of claim 1, wherein a dimension of the second gate structure along a gate width direction is less than or equal to 2 microns.

15. The semiconductor structure of claim 1, further comprising: and the first gate dielectric layer is positioned between the first gate and the first region.

16. The semiconductor structure of claim 1, wherein a material of the first gate dielectric layer comprises silicon oxide.

17. The semiconductor structure of claim 1, further comprising: and the second gate dielectric layer is positioned between the second gate and the first gate.

18. The semiconductor structure of claim 17, wherein the material of the second gate dielectric layer comprises a high-K dielectric material.

19. The semiconductor structure of claim 19, further comprising: the oxide layer is positioned between the first grid electrode and the second grid electrode dielectric layer; and the metal compound layer is positioned between the second gate dielectric layer and the second gate.

20. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first region;

forming a first gate on the first region;

and forming more than two second gate structures on the first gate, wherein the second gate structures comprise second gates, and the materials of the second gates and the first gates are different.

21. The method of forming a semiconductor structure of claim 20, wherein a material of the first gate comprises polysilicon.

22. The method of forming a semiconductor structure of claim 20, further comprising: and forming a first gate dielectric layer between the first gate and the first region.

23. The method of forming a semiconductor structure of claim 22, wherein a material of the first gate dielectric layer comprises silicon oxide.

24. The method of forming a semiconductor structure of claim 20, wherein the method of forming the first gate comprises: forming a first gate layer on the first region; and patterning the first gate layer to form a first gate.

25. The method of forming a semiconductor structure of claim 24, wherein the method of forming the first gate further comprises: doping first doping ions in the first grid layer; the first doping ions are of an N type or a P type.

26. The method of forming a semiconductor structure of claim 20, wherein a material of the second gate comprises a metal.

27. The method of forming a semiconductor structure of claim 20, wherein the second gate structure further comprises a second gate dielectric layer between the second gate and the first gate.

28. The method of forming a semiconductor structure of claim 27, wherein a material of the second gate dielectric layer comprises a high-K dielectric material.

29. The method of forming a semiconductor structure of claim 28, wherein the second gate structure further comprises: the oxide layer is positioned between the first grid electrode and the second grid electrode dielectric layer; and the metal compound layer is positioned between the second gate dielectric layer and the second gate.

30. The method of forming a semiconductor structure of claim 20, wherein the method of forming the second gate structure comprises: forming more than two first dummy gate structures on the first gate, wherein the first dummy gate structures comprise first dummy gates; replacing the first dummy gate with the second gate.

31. The method of forming a semiconductor structure of claim 30, wherein the method of forming the second gate structure further comprises: forming an interlayer dielectric layer on the surface of the substrate, wherein the interlayer dielectric layer is also positioned on the side wall and the surface of the first grid electrode and the side wall of the first dummy grid electrode, and the interlayer dielectric layer exposes out of the first dummy grid electrode; etching to remove the first dummy gate, and forming a plurality of first grooves in the interlayer dielectric layer; and filling the first groove to form a second grid.

32. The method of forming a semiconductor structure of claim 20, wherein forming the first gate is performed while forming the first dummy gate structure; the method for forming the first gate and the first dummy gate structure comprises the following steps: forming a first gate layer on the first region; and etching part of the first gate layer to form the first gate and more than two first dummy gates on the first gate.

33. The method of forming a semiconductor structure of claim 20, wherein the method of forming the first dummy gate structure comprises: forming a first gate layer on the first region, and forming a first dummy gate layer on the surface of the first gate layer; and patterning the first dummy gate layer and the first gate layer to form a first gate and more than two first dummy gates on the first gate.

34. The method of forming a semiconductor structure of claim 33, wherein the first dummy gate structure further comprises: a first hard mask layer located on the first dummy gate; the method for forming the first dummy gate structure and the first gate further comprises: forming the first hard mask layer on the first dummy gate layer; etching the first pseudo gate layer by taking the first hard mask layer as a mask until the surface of the first gate layer is exposed to form a first pseudo gate; and etching the first gate layer exposed by the first dummy gate by using the first hard mask layer as a mask until the surface of the first region is exposed to form a first gate.

35. The method of forming a semiconductor structure of claim 33, wherein the method of forming the first hard mask layer comprises: and forming an initial first hard mask layer on the surface of the first pseudo gate layer, and etching the initial first hard mask layer until part of the surface of the first pseudo gate layer is exposed.

36. The method of forming a semiconductor structure of claim 20, wherein after forming the first gate and before forming the second gate structure, further comprising: and forming a first source drain region in the first region on two sides of the first grid electrode, wherein the first source drain region is internally provided with second doped ions.

37. The method of forming a semiconductor structure of claim 30, wherein after forming the first dummy gate structure and before forming the second gate structure, further comprising: and forming a modified layer on the surface of the first gate, wherein the modified layer is positioned between the first dummy gate structures.

38. The method of forming a semiconductor structure of claim 37, wherein a material of the modification layer comprises a metal silicide; the forming process of the modified layer comprises a self-aligned metal silicification process.

39. The method of forming a semiconductor structure of claim 31, wherein the substrate further comprises a second region; the forming method further includes: and forming a third gate structure on part of the second region, wherein the third gate structure comprises a third gate, and the material of the third gate is the same as that of the second gate.

40. The method of forming a semiconductor structure of claim 39, wherein the method of forming the third gate structure comprises: forming a second groove in the interlayer dielectric layer on the second area; and forming a third gate in the second groove.

41. The method of forming a semiconductor structure of claim 40, wherein the method of forming the second trench comprises: forming a second dummy gate structure on the second region before forming the interlayer dielectric layer, wherein the second dummy gate structure comprises a second dummy gate; the interlayer dielectric layer is also positioned on the side wall of the second dummy gate structure and exposes the top surface of the second dummy gate structure; and removing the second dummy gate, and forming the second groove in the interlayer dielectric layer.

42. The method for forming a semiconductor structure according to claim 40, wherein a third gate is formed in the second trench at the same time as the second gate; the second grid and the third grid are formed by the method which comprises the following steps: forming a third grid material layer in the surface of the interlayer dielectric layer, the first groove and the second groove; and flattening the third grid material layer until the surface of the interlayer dielectric layer is exposed, and forming the second grid and the third grid.

43. The method of claim 42, wherein the process of planarizing the third gate material layer is a mechanochemical polishing process.

44. The method of forming a semiconductor structure of claim 41, wherein the second dummy gate structure forming method comprises: and forming a second dummy gate material layer in the second region, and patterning the second dummy gate material layer to form the second dummy gate.

45. The method of forming a semiconductor structure of claim 41, wherein the first dummy gate structure and the first gate are formed at the same time as the second dummy gate is formed; the first dummy gate structure, the first gate and the second dummy gate are formed by a method comprising: forming a first gate layer on the first region; forming a first dummy gate material layer on the first gate layer and on the second region; forming a first hard mask material layer on the first dummy gate material layer; etching the first hard mask material layer until part of the first dummy gate layer on the first region and part of the second region are exposed to form an initial first hard mask layer; etching the first dummy gate material layer on the first region by using the initial first hard mask layer until the surface of the first gate layer is exposed, forming a first dummy gate layer on a part of the first gate layer, and forming a second dummy gate layer on the second region; after forming a first dummy gate layer and a second dummy gate layer, removing part of the initial first mask layer, exposing part of the first dummy gate layer and part of the surface of the second dummy gate layer, and respectively forming a first hard mask layer on a first area and a second hard mask layer on a second area; etching the first pseudo gate layer by taking the first hard mask layer as a mask until part of the surface of the first gate layer is exposed to form a first pseudo gate; etching the first gate layer exposed by the first dummy gate layer by using the first hard mask layer as a mask until the surface of the first region is exposed to form a first gate; and etching the second pseudo gate layer by taking the second hard mask layer as a film plate until the surface of the second area is exposed to form a second pseudo gate.