128771* 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種顯示器的驅動電路，且特別是 有關於一種液晶顯示器的閘極驅動電路。 【先前技術】 隨著平面顯示器技術進步與逐漸突破尺寸限制，電 視機(TV)由以往的陰極射線映像管(cath〇(ie ray tube，CRT) 電視逐漸演進至各種乎面面板(f]at panel display，FPD)電 視，較為熟知的有液晶電視(liqUid crystal display，LCD)與 電漿電視(plasma display panel，PDP)兩種，平面面板電視 由於體積輕薄、色彩鮮豔等原因，因此逐漸取代以往的陰 極射線映像管電視。而上述各種不同種類的FPD中，其 原理大多利用多數個電晶體之掃描（閘極）訊號配合資料 (源極)訊號以便於讓面板顯示由電晶體等驅動之像素而合 併成影像。 以往的陰極射線映像管顯示器傳送的顯示訊號為交 錯式訊號。也就是說’當陰騎線映鮮顯示器欲接收並 顯示一個晝面的影像時，會先從顯示訊號的第一個訊框 伽㈣中依序接㈣第丨、3、5、7...等之奇數條掃描線 =不貧料簡㈣分晝面。待完成奇數條掃減之接收 〇颂不之後，再於第二個訊框中接收到第2、4、6、8 等之偶數條掃描線之顯示資料以顯示成—個完整的晝面。 ，，示器的顯示訊號係為—個非交錯式訊號。也就是 况’吾液晶顯示器欲接收並且顯示—個畫面的影像時，會 I287lM。, ^序收到第i、2、3、4···等掃描線之顯示資料訊號而直 輪出顯示。因此’若將陰極映像管電視之顯示訊號輸入 至液日日顯示器以顯示影像時，則必須先將顯示訊號的交錯 式汛就轉變為非交錯式訊號，才可以經由液晶顯示器顯示 影像。 、圖1是習知技術之將交錯式顯示訊號轉變為非交錯 式顯示訊號的轉換電路方塊圖。請參照圖i，此電路包含 衫像解碼器1〇1、定標(scaler)電路1〇5以及同步動態隨機 存取記憶體(synchronous dynamic random access memoiy， SDRAM) 110。影像解碼器ιοί將類比之顯示訊號丨⑻轉 換成數位顯示訊號103。同步動態隨機存取記憶體11〇是 定標電路(scalar 1C )1〇5用來作訊框速率控制(Fr_咖 contrd，FRC)之用，係由於美國國家電視系統委員會 (National Television System Committee，NTSC)所制吖^ 交錯式訊號的60Hz掃描頻率標準與歐洲國家電視標準 (PAL)制訂之交錯式訊號的50 Hz掃描頻率互不相同二 此利用SDRAM、11〇與定標電路1〇5將上述之兩種頻率統 一為60Hz’以作為統一頻率的顯示訊號，因此需要 110以作為暫存。定標電路1()5除了可將交錯 示訊號103調整解析度讓顯示訊號成為與顯示面: 之訊號外’某些習知之定標電路105還可利用某此=5 交錯式的數位顯示訊號103轉換成非交錯式的數二，術將 號107以輸出，讓影像顯示於液晶顯示器。灸 員示几 液晶顯示H，請參㈣2。 “、、更清楚說明 12877?! 9twf.doc 圖2為習知液晶顯示考 圖中液晶顯示面板2H)上^^動電路結構的方塊圖。 線與源極驅動線215 j有^固縱橫交錯的閘極驅動 驅動線215相交之處均有閑極驅動線犯與源極 . n ^ ^個由電晶體與液晶電容等所组 ϋΓ 多像素以合併成整個影像。其中、、’ 母-個，素電晶體之閑極與對應之其中—條間極驅動線 213相連結，而每-個像素電晶體之源極則與對應之且中 -條源極驅動線2i5相連結。當其卜條閘極驅動線接收 閘極訊號而致能(enable)時，與祕___連接之 所有像素之電晶體均胡啟(tum⑽），此時這些像素即透 過電晶體從各自之源極驅動線輸人像素齡喊以控制液 時序控制器240接收由圖1產生之數位顯示訊號 207(於圖1時係標示為數位顯示訊號1〇7)，並且產生掃描 訊號243、水平同步訊號245、與顯示資料247。源極驅 動器200接收水平同步訊號245、顯示資料247以依時序 產生像素顯示訊號215。當閘極驅動電路220内之移位暫 存器(shift register)221接收掃描訊號243後，會將掃描訊 號逐級傳遞以使第一條閘極驅動線213到最後一條閘極驅 動線213依序致能(enabie)。於實作上，上述源極驅動器 200與閘極驅動電路220係分別由多顆源極驅動積體電路 以及多顆閘極驅動積體電路所組成。 依上述可知，傳統平面顯示器需將交錯式之數位顯 示訊號103事先轉換為非交錯式之數位顯示訊號 Ι2877^9ίλνί(ΐ0ς 107/207 ’然後一條一條地顯示於顯示面板2ΐ〇上。習知 技術#用之將顯示影像的交錯式訊號轉變為非交錯式訊號 有二種方式，以下大略介紹之。 、圖3為習知技術之將交錯式顯示訊號轉變為非交錯 ^顯:，號的概念圖。請參照圖3，圖3左上方之訊框傳 送的疋可數條掃描線的顯示訊號訊框，圖3右上方之 ，框傳送的是偶數條掃描線的顯示訊號訊框320,由於液 二曰顯不态每次接收的顯示訊號皆必須是完整的一個顯示訊 號^框，因此定標電路(圖1之105)將每一條掃描線的資 =描兩次(line dQuble)，使得原本為奇數掃描線的訊框 310之顯示資料能夠成為一個影像咖示訊號訊框330, 320 1但為使掃描線數足夠成為—個影像而將晝面的 ::析掃描兩次’因此畫面 、成牛而且晝面會有鋸齒狀的情況產生。 非六^1衫—制知技狀將交錯絲賴號轉變為 非又!曰式頌不訊號的概念圖。請 描線掃描兩次會讓解析声读纟田於將條知 生，因此另一種習知轉換電路 么 7用内差法等軟體運算方法將4=二： 貧料f擬出-條偶數條掃描線的資料。因== 此類推。將偶數條掃綱沾次⑴讀狱“的貝科，依 4、s r = 線的雜模擬後便料1、2'、3、 •條掃描線的方柄描摘㈣料赌。圖 4右上方之汛框42〇再以偶數條掃描線的資料模擬出奇數 條資料，依此類推’將偶數條掃描線的資料模擬後用第1、、 2、3、、4、5、6···的方式掃描成顯示資料訊框44〇。此習 知技術由於係經由軟體模擬出來的訊號，因此具有畫面失 真之缺點’尤其是在影像靜止時相當顯著。 圖5是再一種習知技術之將交錯式顯示訊號轉變為 非交錯式顯示訊號的轉換電路方塊圖。請參照圖5，與圖 1的電路架構相比，此電路除了包括影像解碼器5〇1、定 標電路505與SDRAM 510外，多增加一個解交錯電路 (De-interlace IC) 530 以及第二 SDRAM 54〇。當數位交錯 式之顯示訊號503傳送至解交錯電路53〇時，解交錯電路 53〇會先將第一個奇數掃描線的訊框與第二個偶數掃描線 =訊框之資料暫存至第二SDRAM 54G，再將這兩個訊框 3併成個元整的框，並將此完整的顯示資料訊框傳送 至液晶顯示器的驅動電路以顯示影像。此習知技術雖能夠 使平面顯示器之晝質清晰且不失真，但必須增加解交錯電 路53〇以及第二SDRAM 540的成本花費。 曰 【發明内容】 、 本發明的目的之一就是在提供一種平面顯示器，以 解決父錯式顯示訊號轉換成非交錯式顯示訊號的問題，並 且讓平面顯示器得以顯示晝質清晰的影像。 本發明的另一目的是提供一種閘極驅動電路，以解 決父錯式顯示訊號轉換成非交錯式顯示訊號的問題，並且 讓顯示面板得以顯示晝質清晰的影像。 I2877§i9twf.doc ! - Ύ的再一目的疋提供—種閘極驅動方法，用於 顯示面板中’以解決交錯式顯示訊號轉 示 訊號的問題，讓平面顯示器得以顯示晝質清晰的影i 本發明提出—種平面顯示器，用以接收m顯 不减以顯不-影像，此平面顯示器包括時序控制器、顯 不面板、源極驅動電路以及閘極驅動電路。時序控制套 收-個交錯式顯示訊號’並且產生奇數掃描訊號、偶數掃 描訊號、顯示資料與水平同步訊號，其中依據交錯式顯示 訊號係為奇數訊框(frame)與偶數訊框而分別依序致能 (enable)奇數掃描訊號與偶數掃描訊號。顯示面板具有多 個閘極驅動線以及多個源極驅動線，顯示面板内的源極驅 動線接收像素顯示訊號並配合間極驅動線以顯示影像。源 極驅動電路接收顯示資料與水平同步訊號，用以根據水平 同^^之時序依序輸出像素顯示訊號。間極驅動電路接 ，奇數訊號與偶數掃描喊，#奇數掃描訊號致能 時’將奇數條的閘極驅動線依序致能，當偶數掃描訊號致 能時，將偶數條之閘極驅動線依序致能。 依照本發明的較佳實施例所述之平面顯示器，上述 之間極驅動電路包括奇數移位暫存器與偶歸位暫存器。 奇數移，暫存器係用以接收奇數掃描訊號，當奇數掃描 訊，致能時，將奇數條間極驅動線依序致能。偶數移位暫 存益係用以接收此偶數掃描訊號，當偶數掃描訊號致能 時，將偶數條閘極驅動線依序致能。 依照本發明的較佳實施例所述之平面顯示器，上述 12877財 9twf.doc 之平面顯示器係為液晶顯示器。 ”依照本發明的較佳實施例所狀平面顯示器 ，上述 平面顯示态之更新頻率大於等於120MHz。 本發明提出另一種閘極驅動電路，用於具有多條閘 極驅動線之顯示面板。關極軸電路包括奇數移位暫存 =以及偶數移位暫抑。奇歸位暫存ϋ接收奇數掃描訊 ^ ’當奇數掃描訊號致能時，將奇數條的閘極驅動線依 能。偶數移位暫存器接收此偶數掃描訊號，當偶數 知描訊號致鱗，將偶數條的閘極驅動線依序致能。 ^發明再提出—種閘極驅動方法，係用於具有多條問 i f線之顯示面板。首先，根據交錯式顯示訊號係為奇 味ί f酬6)與偶數訊框而分別產生對應之奇數掃描訊 ^ ^翻訊號。當奇數掃描訊號致能時，依序致能奇 致::傜Li驅動線。以及’當偶數掃描訊號致能時，依序 夂月匕偶數條的閘極驅動線。 奇盤ίϊ明因在平面顯示器中依照交錯式顯示訊號係為 極瓶與偶數訊框之不同而分職奇數條之閘 或偶數條之閘極魏線依序致能，所以可以直接 不訊號輸入至面板驅動電路以顯示影像，而不 ^ t ί»其他枝將交錯絲示訊_為非交錯式顯示 知:二=但可以降低裝置電路的成本，更可以解決習 要灰二：：失真與解析度減半之缺點。對於平面顯示器 價格兼顧的今日有實質上的幫助。 …義本發明之上述和纟他㈣、特徵和優點能更明 I2877§〇Lfdoc 圖式，作詳細 2日=了文特舉較佳實施例，並配合所附 【實施方式】 電路習^^^"?於㈣電路結構前增加某些轉換 習知技術由於;;交錯式訊號。此 者而且姐…， 摘不R造成晝質不清晰、失真、 旦八鋸《狀、或者增加成本等問題。本發明 巾之閘極㈣電__,_方式，讓顯示訊號 呈，以乂錯式方法顯示於平面顯示器、上，因此較習知技術 ^能保持影像的晝質，降低轉換電路之成本。對於可將液 晶電視的成本降低、維持影像晝質有實質性的效果。 在此列舉一較佳實施例以說明本發明，請同時參照 圖1與圖6。圖6係依照本發明一較佳實施例所繪示的一 種平面顯示器之驅動電路結構的方塊圖。圖1之電路包含 影像解碼器1〇1、定標電路1〇5、以及同步動態隨機存取 石己 fe 體（synchronous dynamic random access memory， SDRAM) lio。影像解碼器101將類比之交錯式顯示訊號 100轉換成數位之交錯式顯示訊號103。同步動態隨機存 取記憶體110是定標電路(scalar 1C ) 105用來作訊框速率 控制(Frame rate control，FRC)之用，係由於美國國家電 視糸統委員會(National Television System Committee， NTSC)所制訂之交錯式訊號的60Hz掃描頻率標準與歐洲 國家電視標準(PAL)制訂之交錯式訊號的50 Hz掃描頻率 互不相同，因此利用SDRAM 110與定標電路105將上述 之兩種頻率統一為60Hz，以作為統一頻率的顯示訊號， 12 1287781 140o9twf.doc 因此需要SDRAM 110以作為暫存。 在此需強調，定標電路105在本實施例中僅用於調 整交錯式的數位顯示訊號103的解析度而已’並無將交錯 式顯示訊號轉換為非交錯式顯示訊號之功能。因此，定標 電路105將交錯式的數位顯示訊號103作適當調整後輸出 交錯式之數位顯示訊號107。於此實施例中，一個晝面之 解析度為640χ 480，也就是具有640x 480=307200個晝 素，這些畫素排成64Q行與480列以形成一個顯示面板之 影像。 而圖6之平面顯示器的驅動電路結構中的時序控制 器640從圖1接收交錯式之數位顯示訊號607 (於圖1時 係標示為數位顯示訊號107)，並且依時序產生奇數掃描 訊號641、偶數掃描訊號643、水平同步訊號645、與顯 示資料647。其中，奇數掃描訊號641或偶數掃描訊號643 之產生係由於接收之交錯式的數位顯示訊號607所傳送的 顯示訊號訊框(fl a m e)係為奇數條掃描線或者偶數條掃描線 而定。源極驅動器600與顯示面板610分別與圖2之源極 驅動器200與顯示面板210相似，故不在此贅述。此時之 像素顯示訊號615由源極驅動器600所提供。為了便於說 明本發明，顯示面板610具有480條閘極驅動線613與640 條源極線615 ,以及僅以兩組移位暫存器代表說明閘極驅 動電路620。凡熟習此技藝者可依本實施例之啟示而修改 圖6之電路，故不應以此限制本發明之範疇。 奇數移位暫存器621依照時序控制器64〇所產生之 I2877?l9twfd〇c 奇數掃描訊號641來控制奇數條閘極驅動線613，偶數移 位暫存器621則依照時序控制器640所產生之偶數掃描訊 號643來控制偶數條閘極驅動線613。當閘極驅動電路62〇 内之奇數移位暫存器621接收奇數掃描訊號641後，會讓 第1、3、5、7···至479條閘極驅動線613依序致能(enable)， 以便於將交錯式之數位顯示訊號6〇7中奇數條掃描線之顯 不訊號訊框一條一條地顯示於顯示面板610之奇數條掃描 線上。當閘極驅動電路620内之偶數移位暫存器623接收 奇數掃描訊號643後，會讓第2、4、6、8…至480條閘 極驅動線613依序致能，以便於將交錯式之數位顯示訊號 6〇7中偶數條掃描線之顯示訊號訊框一條一條地顯示於顯 示面板610之偶數條掃描線上。 ， 因此，當一個交錯式顯示訊號100想要顯示於顯示 面板610時，先經由影像解碼器1〇1將類比之交錯式顯示 =唬100轉換成數位之交錯式顯示訊號1〇3，再經由定標 ，路105 (不具有將交錯式訊賴換為非交錯式訊號之功 二)將數位之交錯式齡織1G3調整解析度成為640χ 〇而輸出為父錯式之顯示訊號1〇7(即目6中為顯示訊號 一 而圖6中之時序控制器640接收並依照交錯式之顯 H607戶斤傳送的顯示訊號訊框(flame)係為奇數條掃描 ;，^偶數條掃描線而分職生奇數掃描訊號641與偶數 :虎643 ’以及產生水平同步訊號645與像素顯示訊 。間極驅動電路620内之奇數移位暫存器、621接收 可數掃描訊號641後，依序將第卜3、5、7···至479條 14 1287781^ 閘極驅動，613致能，讓顯示訊號6G7顯示影像於顯示面 板610之可數條掃描線上。相反地，閘極驅動電路a。内 =偶數移位暫存器623接收偶數掃描訊號643後，依序將 第2 4 6、8·.·至480條閘極驅動線613致能，讓顯示 訊號607顯示影像於顯示面板610之偶數條掃描線上。、 f另外由於父錯式顯示訊號必須由奇數條之顯示訊 號訊框與偶數條顯示訊號訊框合起來才是一個完整的影 像，因此假使本實施例中之影像更新頻率為60Hz，但Ϊ 面顯示器顯示給予人眼看到的晝面更新率僅為6〇/2=3〇 =由於頻率減半，而會讓人眼感受到閃爍(flicker)的現 —。因此於本實施例中例如將定標電路之晝面更新頻率設 1至—120HZ以上，因此讓人眼看到的晝面更新率至少為 60 Hz，才能讓人眼感受不到閃爍現象。 〃、不上所述，本發明因在平面顯示器的閘極驅動器中 不同之祕_訊號將奇紐之卩雜軸線或偶數條 較其缝’所料數錯摘錢號依照其 今伤'、帚描線或偶數條掃描線的顯示方式將訊號輸出顯示 不需事先經由其他方式將交錯式顯示訊號轉為非 曰^員不！Kf虎，因此不但可以降低裝置電路的成本 %決習知技術巾平面顯示器接收交錯式訊號後所顯示 之晝面失真與解析度減半之缺點。對於平面哭要 永畫質與價格兼顧的今日有實質上的幫助。 4 以然本發明已以較佳實施例揭露如上，然其並非用 、定本發明，任何熟習此技藝者，在賴離本發明之精 15 神和範當可作些許之更動與潤飾，因此本發明 護範圍當視後附之申請專利範圍所界定者為準。 ’、 【圖式簡單說明】 ^ ° 圖1疋習知技#之將交錯式顯示訊號轉變為非交供 式顯示訊號的轉換電路方塊圖。 曰 圖2為習知液晶顯示器之驅動電路結構的方塊圖。 圖3為售知技術之將父錯式顯示訊號轉變為非交錯 式顯示訊號的概念圖？ 9 圖4為另-種習知技術之將交錯式顯示訊號轉變為 非交錯式顯示訊號的概念圖。 圖5疋再一種習知技術之將交錯式顯示訊號轉變為 非父錯式顯示?虎的轉換電路方塊圖。 一圖6係依照本發明一較佳實施例所繪示的一種平面 顯示1§之驅動電路結構的方塊圖。 【主要元件符號說明】 100、 107、207、500、507、607 :顯示訊號 101、 501 :影像解碼器 103、503、537 :數位顯示訊號 105、505 :定標電路 110、510 :同步動態隨機存取記憶體(sdram) 200、600 :源極驅動電路 210、610 :顯示面板 213、613 :閘極驅動線 215、615 :源極線 12877¾ 69twf.doc 220、620 :閘極驅動電路 221 :移位暫存器 240、640 :時序控制器 243 :掃描訊號 245、645 :水平同步訊號 247、847 :像素顯示訊號 310、320、330、340、410、420、430、440 :顯示 訊號訊框 . 530 :解交錯電路(De-interlace 1C)128771* IX. Description of the Invention: [Technical Field] The present invention relates to a driving circuit for a display, and more particularly to a gate driving circuit for a liquid crystal display. [Prior Art] With the advancement of flat panel display technology and the gradual breakthrough of size restrictions, televisions (TV) have evolved from conventional cathode ray tube (CRT) televisions to various panels (f]at Panel display, FPD) TV, more commonly known as LCD TV (liqUid crystal display, LCD) and plasma display panel (PDP), flat panel TV due to its light size, bright colors, etc., it gradually replaced the past The cathode ray image tube TV. In the above various types of FPD, the principle mostly uses the scanning (gate) signal of the plurality of transistors to cooperate with the data (source) signal to facilitate the display of the pixel driven by the transistor or the like. And merged into an image. The display signal transmitted by the conventional cathode ray image tube display is an interlaced signal. That is to say, when the yin ray line display wants to receive and display a picture of the face, it will first display the signal. In a frame gamma (4), the odd-numbered scan lines of the fourth, third, fifth, seventh, etc. are sequentially connected (four), and the odd-numbered lines are not poor. After receiving the scan, the display data of the even scan lines of the second, fourth, sixth, eighth, etc. are received in the second frame to be displayed as a complete face. The display signal is a non-interlaced signal. That is, when I want to receive and display the image of the screen, I287lM., ^ received the i, 2, 3, 4, etc. The scan line displays the data signal and displays it directly. Therefore, if the cathode image tube TV display signal is input to the liquid day display to display the image, the interlaced display of the display signal must first be converted to non-interlaced. The signal can be displayed on the liquid crystal display. Figure 1 is a block diagram of a conventional conversion circuit for converting an interlaced display signal into a non-interlaced display signal. Referring to Figure i, the circuit includes a shirt image decoder. 1. A scaler circuit 1〇5 and a synchronous dynamic random access memoiy (SDRAM) 110. The image decoder ιοί converts the analog display signal 丨(8) into a digital display signal 103. The synchronous dynamic random access memory 11 is a calibration circuit (scalar 1C)1〇5 used for frame rate control (Fr_coffee contrd, FRC), due to the National Television System Committee (National Television System Committee) , NTSC) The 60Hz scanning frequency standard of the interlaced signal is different from the 50Hz sampling frequency of the interlaced signal developed by the European National Television Standard (PAL). This uses SDRAM, 11〇 and calibration circuit 1〇5 The above two frequencies are unified to 60 Hz' as a display signal of a uniform frequency, so 110 is required as a temporary storage. The calibration circuit 1 () 5 can adjust the resolution of the interlaced signal 103 so that the display signal becomes the same as the display surface: "Some conventional calibration circuits 105 can also use some of the =5 interleaved digital display signals. 103 is converted into a non-interlaced number two, and the number 107 is output to display the image on the liquid crystal display. The moxibustor shows a few LCD displays H, please refer to (4) 2. ",, more clearly, 12877?! 9twf.doc Figure 2 is a block diagram of the structure of the circuit on the liquid crystal display panel 2H) in the conventional liquid crystal display. The line and the source driving line 215 j have a solid crisscross The gate driving drive line 215 intersects with the idle driving line and the source. n ^ ^ is composed of a transistor and a liquid crystal capacitor, and multi-pixels are combined to form an entire image. Among them, 'mother-one, The idle pole of the transistor is connected to the corresponding inter-pole driving line 213, and the source of each pixel transistor is connected with the corresponding middle-source driving line 2i5. When the gate drive line receives the gate signal and is enabled, the transistors of all the pixels connected to the secret ___ are tuned (tum(10)), and the pixels are transmitted from the respective source drive lines through the transistor. The input pixel age controller calls the control liquid timing controller 240 to receive the digital display signal 207 generated by FIG. 1 (shown as a digital display signal 1〇7 in FIG. 1), and generates a scan signal 243, a horizontal synchronization signal 245, and Display data 247. The source driver 200 receives the horizontal synchronization signal 245, The data 247 is generated to generate the pixel display signal 215 according to the timing. When the shift register 221 in the gate driving circuit 220 receives the scanning signal 243, the scanning signal is gradually transferred to make the first gate. The driving line 213 to the last gate driving line 213 are sequentially enabled (enabie). In practice, the source driver 200 and the gate driving circuit 220 respectively drive the integrated circuit and the plurality of gates by multiple sources. According to the above, the conventional flat panel display needs to convert the interlaced digital display signal 103 into a non-interlaced digital display signal Ι2877^9ίλνί (ΐ0ς 107/207 ' and then display one by one in the display. There are two ways to convert the interlaced signal of the displayed image into a non-interlaced signal. The following is a brief introduction. Figure 3 shows the conventional technique of converting the interlaced display signal into a non-interlaced signal. Interlace ^ display:, the conceptual diagram of the number. Please refer to Figure 3, the display signal frame of the number of scan lines transmitted by the frame on the upper left of Figure 3, the upper right of Figure 3, the box transmits an even number of sweeps The display signal frame 320 of the trace line, since the display signal of each liquid reception must be a complete display signal frame, the calibration circuit (105 of FIG. 1) will be the data of each scan line. Line dQuble, so that the display data of the frame 310 which is originally an odd scan line can become an image coffee signal frame 330, 320 1 but the number of scan lines is enough to become an image. ::Synthesis scan twice' so the picture, the cow and the kneading surface will be jagged. Non-six ^1 shirts - the technique of knowing the technology will turn the word into a non-conformity! Figure. Please scan the line twice to make the analytical sound read Putian in the strip, so another kind of conventional conversion circuit 7 uses the internal difference method and other software calculation methods to 4 = two: poor material f out - even number of scan lines data of. Because of == such a push. The even number of sweeps are smeared (1) to read the prison's Beko, according to the 4, sr = line of the simulation, the 1, 2', 3, • the scan of the square of the scan line (four) bet. Figure 4 at the top right Frame 42〇 simulates an odd number of data with even scan lines, and so on. Simulate the data of even scan lines using the first, second, third, fourth, fifth, sixth, and The method scans into a display data frame 44. This prior art has the disadvantage of picture distortion due to the signal simulated by the software, especially when the image is still. Figure 5 is another conventional technique that will be interleaved. A block diagram of a conversion circuit for converting a signal into a non-interlaced display signal. Referring to FIG. 5, in addition to the image decoder 5〇1, the scaling circuit 505, and the SDRAM 510, the circuit is compared with the circuit architecture of FIG. Adding a de-interlace IC 530 and a second SDRAM 54. When the digital interleaved display signal 503 is sent to the deinterleaving circuit 53, the deinterleaving circuit 53 first scans the first odd number. Line frame and second even scan line = signal The data is temporarily stored in the second SDRAM 54G, and the two frames 3 are combined into a complete frame, and the complete display data frame is transmitted to the driving circuit of the liquid crystal display to display the image. Although the quality of the flat panel display can be made clear and undistorted, the cost of the deinterlacing circuit 53A and the second SDRAM 540 must be increased. [Invention] It is an object of the present invention to provide a flat panel display. Solving the problem that the father's wrong display signal is converted into a non-interlaced display signal, and allowing the flat display to display a clear image. Another object of the present invention is to provide a gate driving circuit for solving the father's wrong display signal conversion The problem of non-interlaced display of the signal, and the display panel can display a clear image. I2877§i9twf.doc ! - Another purpose of the 疋 — - a kind of gate drive method for the display panel to solve The problem of interlaced display of signal-transmission signals allows the flat-panel display to display a clear image. The present invention proposes a flat-panel display. The receiving display includes a timing controller, a display panel, a source driving circuit, and a gate driving circuit. The timing control receives an interlaced display signal and generates an odd scanning signal. The even-numbered scanning signal, the display data and the horizontal synchronization signal, wherein the odd-numbered scanning signal and the even-numbered scanning signal are sequentially enabled according to the interlaced display signal for the odd frame and the even frame. a gate driving line and a plurality of source driving lines, wherein the source driving line in the display panel receives the pixel display signal and cooperates with the interpole driving line to display an image. The source driving circuit receives the display data and the horizontal synchronization signal for Horizontally output the pixel display signal in sequence with the timing of ^^. The inter-polar drive circuit is connected, the odd-numbered signal and the even-numbered scan are shouted. When the odd-numbered scan signal is enabled, the odd-numbered gate drive lines are sequentially enabled. When the even-numbered scan signals are enabled, the even-numbered gate drive lines are used. In order to enable. In accordance with a preferred embodiment of the present invention, the interpole drive circuit includes an odd shift register and an even homing register. The odd-numbered shift is used to receive the odd-numbered scan signals. When the odd-numbered scans are enabled, the odd-numbered inter-polar drive lines are sequentially enabled. The even shift memory is used to receive the even scan signal, and when the even scan signal is enabled, the even gate drive lines are sequentially enabled. According to a flat panel display according to a preferred embodiment of the present invention, the flat panel display of the above-mentioned 12 877 9 twf.doc is a liquid crystal display. According to a preferred embodiment of the present invention, the planar display state has an update frequency greater than or equal to 120 MHz. The present invention provides another gate drive circuit for a display panel having a plurality of gate drive lines. The axis circuit includes an odd shift temporary storage = and an even shift temporary suppression. The odd homing temporary storage ϋ receives the odd scanning signal ^ 'When the odd scanning signal is enabled, the odd gate driving lines are enabled. Even shifting The register receives the even-numbered scan signal, and when the even-numbered signal is scaled, the even-numbered gate drive lines are sequentially enabled. ^Invented again, a gate drive method is used for having multiple ask if lines The display panel. Firstly, according to the interlaced display signal system, the corresponding odd-numbered scanning signal is generated separately from the even-numbered frame. When the odd-numbered scanning signal is enabled, the sequence is enabled. To:: 傜Li drive line. And 'When the even-numbered scan signal is enabled, the even-numbered gate drive lines are sequentially arranged. The odd-numbered display is based on the interlaced display signal in the flat panel display. Even news Different gates or odd-numbered gates are sequentially enabled, so you can directly input signals to the panel driver circuit to display images without ^t ί» For non-interlaced display: 2 = but can reduce the cost of the device circuit, but also can solve the shortcomings of the ash 2: distortion and resolution halving. For the flat display price considerations today, there is substantial help. The above and the other (four), features and advantages of the present invention can better clarify the I2877 § 〇 Lfdoc schema, and the detailed description of the second embodiment is exemplified in the following, and the accompanying [embodiment] circuit learning ^^^" Add some conversion techniques in front of the (4) circuit structure;; interlaced signals. This and the sister..., picking up R causes the problem of unclear, distorted, sinusoidal, or increased cost. The gate of the invention (4) is electrically __, _ mode, so that the display signal is displayed on the flat display and in the wrong way, so that the image quality can be maintained and the cost of the conversion circuit can be reduced. For LCD TVs The cost reduction and the maintenance of image quality have substantial effects. Here is a preferred embodiment to illustrate the present invention, please refer to both FIG. 1 and FIG. 6. FIG. 6 is a diagram of a preferred embodiment of the present invention. A block diagram of a driving circuit structure of a flat panel display. The circuit of Fig. 1 includes a video decoder 1〇1, a scaling circuit 1〇5, and a synchronous dynamic random access memory (SDRAM) lio The video decoder 101 converts the analog interleaved display signal 100 into a digital interlaced display signal 103. The synchronous dynamic random access memory 110 is a scaling circuit (scalar 1C) 105 for frame rate control (Frame rate). Control, FRC) is based on the 60Hz sampling frequency standard of the interlaced signal developed by the National Television System Committee (NTSC) and the interlaced signal of the European National Television Standard (PAL) 50 Hz. Since the scanning frequencies are different from each other, the SDRAM 110 and the scaling circuit 105 are used to unify the above two frequencies into 60 Hz as a display signal of a uniform frequency. 12 1287781 140o9twf.doc SDRAM 110 is required as a scratch. It should be emphasized here that the scaling circuit 105 is only used to adjust the resolution of the interleaved digital display signal 103 in this embodiment, and has no function of converting the interlaced display signal into a non-interlaced display signal. Therefore, the scaling circuit 105 appropriately adjusts the interleaved digital display signal 103 to output an interlaced digital display signal 107. In this embodiment, the resolution of one face is 640 χ 480, that is, 640 x 480 = 307200 pixels, and these pixels are arranged in 64Q rows and 480 columns to form an image of a display panel. The timing controller 640 in the driving circuit structure of the flat panel display of FIG. 6 receives the interlaced digital display signal 607 (shown as the digital display signal 107 in FIG. 1) from FIG. 1 and generates an odd scanning signal 641 according to the timing. The even scan signal 643, the horizontal sync signal 645, and the display data 647. The odd scan signal 641 or the even scan signal 643 is generated because the received display signal frame (607) transmitted by the interleaved digital display signal 607 is an odd number of scan lines or an even number of scan lines. The source driver 600 and the display panel 610 are similar to the source driver 200 and the display panel 210 of FIG. 2, respectively, and thus are not described herein. The pixel display signal 615 at this time is provided by the source driver 600. To facilitate the description of the present invention, display panel 610 has 480 gate drive lines 613 and 640 source lines 615, and gate drive circuit 620 is illustrated with only two sets of shift registers. Those skilled in the art can modify the circuit of Figure 6 in light of the teachings of this embodiment and should not limit the scope of the invention. The odd shift register 621 controls the odd gate drive lines 613 according to the I2877?l9twfd〇c odd scan signal 641 generated by the timing controller 64, and the even shift register 621 is generated according to the timing controller 640. The even scan signal 643 controls the even gate drive lines 613. When the odd-numbered shift register 621 in the gate driving circuit 62 receives the odd-numbered scanning signal 641, the first, third, fifth, seventh, and 479 gate driving lines 613 are sequentially enabled (enable). In order to display the display signals of the odd-numbered scan lines of the interdigitated digital display signals 6〇7 one by one on the odd-numbered scan lines of the display panel 610. When the even-numbered shift register 623 in the gate driving circuit 620 receives the odd-numbered scanning signal 643, the second, fourth, sixth, eighth, ..., 480 gate driving lines 613 are sequentially enabled to facilitate interleaving. The display signal frames of the even number of scan lines in the digital display signal 6〇7 are displayed one by one on the even scan lines of the display panel 610. Therefore, when an interlaced display signal 100 is to be displayed on the display panel 610, the analog interleave display=唬100 is first converted into a digital interlaced display signal 1〇3 via the image decoder 1〇1, and then Calibration, way 105 (does not have the function of changing the interlaced signal to non-interlaced signal 2), the digital interlaced 1G3 adjustment resolution becomes 640χ, and the output is the father's wrong display signal 1〇7 ( That is, the display signal signal received by the timing controller 640 in FIG. 6 and transmitted in accordance with the interleaved display H607 is an odd number of scans, and the even number of scan lines are divided into The occupational odd-numbered scanning signal 641 and the even number: the tiger 643' and the horizontal synchronization signal 645 and the pixel display signal. The odd-numbered shift register in the inter-pole driving circuit 620, 621 receives the countable scanning signal 641, and then sequentially Bu 3, 5, 7··· to 479 14 1287781^ Gate drive, 613 enable, display signal 6G7 display image on the scan line of display panel 610. Conversely, gate drive circuit a. = even shift register 623 receives even scan After the number 643, the second 4 6th, 8th, and 480th gate driving lines 613 are sequentially enabled, so that the display signal 607 displays the image on the even-numbered scanning lines of the display panel 610. The display signal must be combined with the odd-numbered display signal frame and the even-numbered display signal frame to be a complete image. Therefore, if the image update frequency in this embodiment is 60 Hz, the face display display is given to the human eye. The facet update rate is only 6〇/2=3〇=Because the frequency is halved, it will make people feel the flicker. So in this embodiment, for example, the face update frequency of the calibration circuit is used. Set 1 to -120HZ or above, so the eye surface update rate is at least 60 Hz, so that the flicker phenomenon can not be seen. 〃, not mentioned, the present invention is in the gate driver of the flat panel display. Different secrets_Signal will display the signal output of the odd-nosed axis or even-numbered strips according to the display of the current injury', the drawing line or the even-numbered scanning lines. Other ways will be interlaced The number is changed to non-曰^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The present invention has been substantially assisted by the combination of quality and price. 4 As a matter of course, the present invention has been disclosed in the preferred embodiments as above, but it is not intended to be used in the invention, and anyone skilled in the art may 15 God and Fan Dang can make some changes and refinements. Therefore, the scope of protection of this invention is subject to the definition of the patent application scope attached to it. ', [Simple description of the figure] ^ ° Figure 1 The interleaved display signal is converted into a block diagram of the conversion circuit of the non-delivery display signal. Figure 2 is a block diagram showing the structure of a driving circuit of a conventional liquid crystal display. FIG. 3 is a conceptual diagram of a technique for converting a father's wrong display signal into a non-interlaced display signal. 9 Figure 4 is a conceptual diagram of another conventional technique for converting an interlaced display signal into a non-interlaced display signal. Fig. 5 is a block diagram of a conventional conversion circuit for converting an interlaced display signal into a non-parent display. FIG. 6 is a block diagram showing the structure of a driving circuit of a flat display 1 § according to a preferred embodiment of the present invention. [Main component symbol description] 100, 107, 207, 500, 507, 607: display signal 101, 501: video decoder 103, 503, 537: digital display signal 105, 505: calibration circuit 110, 510: synchronous dynamic random Access memory (sdram) 200, 600: source drive circuit 210, 610: display panel 213, 613: gate drive line 215, 615: source line 128773⁄4 69twf.doc 220, 620: gate drive circuit 221: Shift register 240, 640: timing controller 243: scan signal 245, 645: horizontal sync signal 247, 847: pixel display signal 310, 320, 330, 340, 410, 420, 430, 440: display signal frame . 530: Deinterlace Circuit (De-interlace 1C)
540 :第二 SDRAM 621 :奇數移位暫存器 623 :偶數移位暫存器 641 ··奇數掃描訊號 643 :偶數掃描訊號540: second SDRAM 621: odd shift register 623: even shift register 641 · odd scan signal 643: even scan signal
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