TWI287297B - Method of manufacturing nano crystals and application of the same - Google Patents

Method of manufacturing nano crystals and application of the same Download PDF

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TWI287297B
TWI287297B TW094130426A TW94130426A TWI287297B TW I287297 B TWI287297 B TW I287297B TW 094130426 A TW094130426 A TW 094130426A TW 94130426 A TW94130426 A TW 94130426A TW I287297 B TWI287297 B TW I287297B
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substrate
film
semiconductor structure
grains
nano
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TW200713585A (en
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Chih-Wei Chao
Mao-Yi Chang
I-Chang Tsao
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Au Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

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Description

•1287297 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種奈米級晶粒之製造方法及其應用，且特 別是關於一種可在低溫下形成奈米級晶粒之製造方法。 • 【先前技術】 具有奈米級尺寸之晶粒，其優點之一是可以作為量子井 (Quantum well)，以作為應用於記憶體元件陷住電子的機制，優 點之二是由於具有較高的吸光效率，而可成為優異的吸光材料。 • 以矽晶粒而言，一般尺寸的矽晶粒可以吸收約30%的光，而奈米 級尺寸的矽晶粒則可吸收約50%〜60%的光。 傳統製作奈米級晶粒之方法是利用化學氣相沈積（Chemjca| vapor deposition ’ CVD)直接在基板上沈積出奈米級晶粒，其中 製私zm度至少約650 C ;或是利用離子佈植（|on jmp|antatj〇n^^ 半導體如矽或鍺植入二氧化矽内，經過約8〇(rc或更高的溫度退 火後在一氧化砍内形成奈米級晶粒。無論是前者或後者，都需要 使用同皿製私，並不符合現有之低溫多晶矽薄膜電晶體（LTps TFT)之製作程序。 & 【發明内容】 、有鑑於此，本發明的目的就是在提供一種奈米級晶粒之製造 2及其應用，利用薄膜和低溫#射退火的方式形成奈米級晶粒 的製造方法，特別符合低溫多晶石夕薄膜電晶體（ltpstf丁)之製作 根據本發明之目的，係提出一 括步驟如下： 種製作奈米級晶粒之方法 包 提供一基板； 形成一薄膜於基板上，薄膜 對薄膜施以一雷射退火處理 TW2429PA , 之厚度係小於等於約50 A ;及 ，且雷射光之一波長係小於等於 •1287297 、、勺500 nm，以在基板上形成複數個奈米晶粒（Nan〇 c「ySta丨）。 根據本發明之目的，係提出一種具奈米級晶粒之半導體結 構，包括一基板，及複數個奈米晶粒；且該些奈米晶粒係以一低 溫結晶方法於基板上，其平均粒徑約在10 nm以下。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文 特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】
請參照第1A、1B圖，其繪示依照本發明一較佳實施例之奈 米級晶粒製作方法之示意圖。首先，提供一基板仞。基板彳彳係 較佳地為一不吸收雷射光的材質，例如玻璃、塑膠、二氧化矽甚 至金屬都可作為本發明之基板”。接著，形成—薄膜13於基板 ^上，且薄膜13之厚度係等於或小於約5〇Α，較佳地約在 〜25 Α之間’如第1Α圖所示。至於薄膜13的材料並沒有特別 限制’視所需形成的晶體材質而定，常見的薄膜13材料例如是 包括石夕（silicon，Si)，錯（germanium，Ge)或石夕化錯⑸以）。 之後’對薄膜13施以-雷射退火處理，且使用的雷射 =係小於科約__，以在基板^上形成複數個奈米晶粒 (Nan〇crystal)131。另外，雷射光之波長範圍係較佳地在約期 :〜約__之間；所形成的該些奈米晶粒131其平均粒 達10 n m以下。 工 另外，在形成薄膜13之步驟前，亦可先 0 示)於基板11上。、_㈣包括：㈣4二層二顯 然而，絕緣層的存在與否係視應用元件之需 ° 並不多做限制。 & ’本發明在此 /值得注意的是，本發明之雷射退火處理步驟可 仃，例如是室溫。換句話說，應用本發明之方法可於三級下進 生奈米晶粒131於基板糾上。因此，本發 於一室溫下產 X 示米級晶粒製作
TW2429PA 6 "1287297 溫製作之基板，也符合現有之低溫多晶” 胺包曰曰體（LTPSTFT)之製作程序。 ^專 結構(ΓΓ/Γ—較佳實施例之製作方法所產生的奈米級晶粒 elect_ •圖所不）’係以穿透式電子顯微鏡(Transmission Γ。^，TEM)進行材料分析，其結果如第2圖所 而日#、，果清楚W該些微小㈣之尺寸㈣為奈米級尺寸， 而且確實為結晶性顆粒。
β依^本發明之製作方法所產生的奈米級晶粒結構，至少具有 =乍為好井（QUantum we丨丨)和具有較高的吸光效率等優點。以 、糸根據這兩項優點，分別提出兩種相關之應用例。當然，具有 通常知識者當可理解··本發明之應料分廣泛，以下僅說明立中 兩種可施行之應用例。 〃 i用例一：記愔鍊 、請參照第3A〜3C圖，其繪示應用本發明—較佳實施例之方 法製作一種具有奈米級晶粒的記憶體之示意圖。首先，提供一基 板30,例如是一透明玻璃；於基板3〇上先形成一多晶矽層&。 而形成多晶矽層的方法例如是：先形成一具有一定厚度的^晶矽 層，再利用傳統方法例如準分子雷射退火（Excimer Laser Annealing，ELA)技術，連續結晶（Continu〇us Grain Si|ic〇n， CGS)技術，雷射橫向結晶（SeqUentia丨 Latera丨 s〇丨idifjcatj〇n， SLS)技術或金屬誘發橫向結晶（Meta丨丨nduced Crystallization’ MILC)技術等，將非晶矽層轉換為多晶矽層31。 之後，於多晶矽層31上方形成一不吸收雷射光之第一絕緣層 32，其材質例如包括二氧化矽、氮化矽或其組合。接著於第一絕 緣層32上方’形成一薄膜33(例如是非晶石夕薄膜），且薄膜33 TW2429PA 7 1287297 如 之厚度係等於或小於約50 A，較佳地約在15 A〜25 第3A圖所示。 之後，對薄膜33施以一雷射退火處理，以在第一絕 個奈米晶粒331，如第3B圖所示。使用的雷射曰光波 二大'〜4於約5〇〇 _，較佳地約200 〜約500 _ 的，米晶粒如其平均粒徑可達1〇 _以下。接著，形成一 1 ^巴緣層35於第—絕緣層32上並覆蓋住奈米晶粒331;最後於 弟-絕緣層35上再形成金屬閘極師丨以華，如第％圖所 :。其中’第二絕緣層35和第一絕緣層32的材質可以相同或相 第3C圖中之奈米晶粒331可作為量子井ww)， =為記憶體元件陷住電子的機制。第4圖為應用本發明方法所 I作之具奈米級晶粒的記憶體元件之電性曲線圖。從第4圖之電 性曲線可驗證奈米級晶粒的確具有量子井的功能。 陽能雷池 由於具有優異的吸光效率，奈米級晶粒亦可應用在太陽能電 :的製作。第5A〜5D圖其㈣應料發明—較佳實施例之方法 ?作-種具有奈米級晶粒的太陽能電池之示意圖。首先，提供一 第一金屬基板51 ’並形成-㈣膜（p_typesine〇nthin _)53於第-金屬基板51上，如第5A圖所示。薄膜53的厚度 係等於或小於約50 A ’較佳地約在15A〜25八之間。接著，利 用波長係小於等於約500 nm(較佳地約·瞧〜約5〇〇 的雷 射光對薄膜53施以雷射退火處理，以在第一金屬基板51上形成 複數個P型奈米石夕晶粒531，如第5B圖所示。之後，形成__ N ㈣膜55於第-金屬基板51上’並覆蓋於該些「型奈米石夕晶粒
TW2429PA 8 Ί287297
531，如第5C圖所示。最後，於N 基板57，.如第5D圖所示，55上形成一第二金屬 口 m 以凡成太陽能電池的 在太陽能電池的受光過程中， 晶粒531和N型薄膜55所^、你田电蛛6.由P型奈米石夕 I核55所建立)作用，帶正電的載子會往p型 奈米石夕晶粒531移動’帶負電的載子會往N型薄膜55曰移動，而 產生電流。而P型奈㈣晶粒531優異的吸光效率，可提升太陽 能電池的光電特性。 綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 Θ
TW2429PA 9 1287297 【圖式簡單說明】 作方法 圖繪示依照一 電子4=二較佳實施例之奈米㈣ 具有奈米級= 實施例之方法製作-種 第4圖為應用本發明方法所 元件之電性曲線圖。 、不未級晶粒的記憶體 第5A~5D圖其㈣應用本翻—較佳實_ 種具有奈米級晶粒的太陽能電池之示意圖。 万法製作一 【主要元件符號說明】 11、3 0 ·基板 13、33、53 :薄膜 131、331、531 :奈米晶粒 31 :多晶梦層 32 :第一絕緣層 35 :第二絕緣層 37 ·金屬間極 51 :第一金屬基板 55 : N型薄膜 57 :第二金屬基板 TW2429PA 10

Claims (1)

  1. ί?87297 丄 . Ρ年f月//日修(曼)正本 十、申請專利範圍·· L—一一―一一___j 1 · 一種製作奈米級晶粒之方法，包括步驟： 提供一基板； 形成一薄膜於該基板上，該薄膜之一厚度係小於等於约50 A ;及 對該薄膜施以一雷射退火處理，且該雷射光之一波長係小於 等於、々500 nm ’以在該基板上形成複數個奈米晶粒（Nano crystal)，其中該些奈米晶粒的一平均粒徑約在’〇 nm以下。 I 2·如申請專利範圍第1項所述之方法，其中該基板為一玻 璃基板。 3_如申請專利範圍第1項所述之方法，其中該基板為一塑 膠基板。 4_如申請專利範圍第1項所述之方法，其中該基板為一金 屬基板。 5.如申请專利範圍第1項所述之方法，其中該薄膜之厚度 範圍約在15 Α〜25 Α之間。 6·如中睛專㈣圍第]項所述之方法，其中該薄膜之材料 包括石夕（silicon，Si)，_e_nium，叫或石夕化錯⑸叫。 a 7·如申請專利範圍第巧項所述之方法，其中該雷射光之波 長犯圍約在200 nm〜500 nm之間。 8.如申請專職圍第1項所述之方法，其巾係在形成該薄 膜之步驟前，先形成一絕緣層於該基板上。 5如中請專利範圍第8項所述之方法，其中該絕緣層係包 括一氧化石夕、氮化石夕或其組合。 1〇· —種具奈米級晶粒之半導體結構，包括： 一基板；及 TW2429(060713)CRF.doc 11 ,^287297 複數個奈米晶粒（Nano crystal)，係以一低溫雷射結晶方法 也成於該基板上，且該些奈米晶粒之一平均粒徑約在10 nm以 下。 11_如申請專利範圍第1〇項所述之半導體結構，其中該基 板為一玻璃基板。 12·如申請專利範圍第1〇項所述之半導體結構，其中該基 板為一塑膠基板。 太、> 13·如申請專利範圍第項所述之半導體結構，其中該些 ® τ'米日日粒之材料為矽（silicon，Si),鍺（germanium，Ge)或矽化 鍺(SiGe)。 14.如申請專利範圍第10項所述之半導體結構，其中該基 ’、有絕緣層，而該些奈米晶粒係形成於該絕緣層上。 •如申請專利範圍第14項所述之半導體結構，其中該絕 緣層：包括二氧化矽、氮化矽或其組合。 •如申請專利範圍第1〇項所述之半導體結構，其中該些 不、未晶粒係於-室溫下結晶於該基板上。 TW2429(060713)CRF.d〇c
TW094130426A 2005-09-05 2005-09-05 Method of manufacturing nano crystals and application of the same TWI287297B (en)

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