1286259 13130twf.d〇c/〇〇6 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種顯示面板及其製作方法，且特 別是有關於一種薄膜電晶體陣列基板及其製作方法。 【先前技術】 隨著電腦性能的大幅進步以及網際網路、多媒體技 術的高度發展，目前影像資訊的傳遞大多已由類比轉為數 位傳輸。為了配合現代生活模式，視訊或影像裝置之體積 日漸趨於輕薄。傳統的陰極射線管（Cathode Ray Tube， CRT)顯示器因具有優異的顯示品質與其經濟性，一直獨 佔近年來的顯示器市場。然而，對於個人在桌上操作多數 :=機/顯示器裝置的環境，或是以環保的觀點切入，若 =郎省能源的潮流加以預測，陰極射線管因空間利用以及 月b=w肖耗上仍存在很多問題，而對於輕、薄、短、小以及 低消耗功率的需求無法有效提供解決之道。 ▲因，，近年來隨著光電技術與半導體製造技術之成 二、也f動了平面顯示器（Flat Panel Display)之蓬勃發 展其中液晶顯示器（Liquid Crystal Display，LCD)基 於其低電壓操作、無輻射線散射、重量輕以及體積小等優 點’更逐漸取代傳統的陰極射線管顯示器而成為近年來顯 不器產品之主流。 ” 考圖1，其繪示為習知之一種液晶顯示器模組的 ^不思圖’其中為求簡化圖示，圖1僅繪示說明所須之 。液晶顯示器模組至少包括薄膜電晶體陣列基板 1286259 13130twf.doc/006 110、彩色濾光膜基板120、黑矩陣層122、框膠130、液 晶層140、偏光板152、154以及外框160。其中，黑矩陣 層122係配置於彩色濾光膜基板120上，框膠130係配置 於彩色濾光膜基板120與薄膜電晶體陣列基板11〇之間， 而液晶層140係配置在彩色濾、光膜基板120與薄膜電晶體 陣列基板110與框膠130所形成的封閉空間中。此外，偏 光板152、154係個別配置在薄膜電晶體陣列基板11()與 彩色濾光膜基板120之未配置液晶層140的另一側表面 上，而外框160則配置在偏光板152上。另外，薄膜電晶 體陣列基板110可分為畫素區ll〇a與周邊線路區ii〇b， 其中周邊線路區ll〇b内係配置有多條引線112以作為顯 示器作動之用。 承接上述，習知形成液晶層140的方式，係先由框 膠130於薄膜電晶體陣列基板110與彩色濾光膜基板12〇 之間圍出一封閉區域，之後再利用毛細管原理藉由外部的 大氣慢慢將液晶注入薄膜電晶體陣列基板110與彩色濾光 膜基板120所圍成的封閉區域内。由於此注入過程費時， 為了因應未來大尺寸液晶面板的量產需求，近來更提出一 種液晶滴下（One Drop Fill，ODF)的技術。所謂的液晶 滴下技術係先在薄膜電晶體陣列基板11〇或彩色濾光膜基 板120上形成框膠13〇，接著將液晶滴入框膠13〇所圍的 區域中，然後再將薄膜電晶體陣列基板11〇與彩色濾光膜 基板120貼合，並藉由紫外光的照射使框膠13〇硬化以黏 合兩基板。 I2862^?0tw,doc/006 值得一提的是，習知為使框膠130均勻受到紫外光 照射，以避免因框膠130硬化不完全而污染部分的液晶 140,所以通常會將彩色濾光膜基板110上的黑矩陣層122 朝面板中心内縮一定距離。然而，由於黑矩陣層122之内 縮’使得黑矩陣層122與框膠130之間產生一可能漏光之 區域170，且更因為周邊線路區i1〇b中的引線112之間 亦無遮光之屏障，所以背光模組所發出的光線18〇便可能 通過引線112間的間隙，而在外框16〇與薄膜電晶體陣列 基板110之交界處發生直視漏光或斜視漏光等問題。 【發明内容】 有鑑於此，本發明的目的就是在提供一種薄膜電晶 體陣列基板及其製作方法，轉決周邊線賴造成的漏光 問題。 基於上述目的，本發明提出一種薄膜電晶體陣列基 才f，其具有一晝素區以及位於晝素區外圍之一周邊線路 ^此薄膜電晶體p車列基板例如包括一透明基板、一薄膜 =體陣列、多條第—引線、多條第二引線以及一第一遮 ,I其，，薄膜電晶體陣列係配置於晝素區内的透明基 =導雷ΐ薄膜電晶體陣列至少包括—第—導電層以及一第 Α, 此外，第一引線係配置於周邊線路區内的透明 i係配置一導電層係同一膜詹，而第二引 二莫^周邊線⑽透縣板上，且第二引線與第 區内的卜，第一遮光層係位於周邊線路 土扳上，其中第一遮光層係對應相鄰第一引線 I2862^i?0tw,doc/006 …间_己置’且第一遮光層與第二導電層係同一膜 層。 基於上述目的，本發明更提出一種薄膜電晶體陣列 基板的H作方法。首先，提供—透明基板，且此透明基板 具有-晝素區與-周邊線路區。接著，在畫素區形成一圖 案化之閘極層，並且同時在周邊線路區形成多條第一引線 以及連接於第-引線的多個第—触。然後，在透明基板 上形成:絕緣層，以使絕緣層覆蓋住閘極層以及第一引 線。接著，在閘極層上方的絕緣層上形成一圖案化之通道 層—a之後，在通道層上形成一圖案化之源極/汲極層，並 且同時在周邊線路區形❹條第二引線以及連接於第二弓丨 線的多個第二触，其中在形成源極級極層的同時，更 包括在相鄰第一引線的間隙上方形成一第一遮光層。 基於上述目的，本發明更提出另一種薄膜電晶體陣 列基板的製作方法。首先，提供一透明基板，且此透明基 板八有I素區與一周邊線路區。接著，在畫素區形成一 圖案化之閘極層，並且同時在周邊線路區形成多條第一弓丨 線以及連接於第一引線的多個第一接墊。然後，在透明基 板上形成一絕緣層，以使絕緣層覆蓋住閘極層以及第一^ 線。接著，在閘極層上方的絕緣層上形成一圖案化之通道 層:之後，在通道層上形成一圖案化之源極/汲極層，= 且同時在周邊線路區形成多條第二引線以及連接於第二引 線的多個第二接墊。其中，在形成閘極層的同時，更包括 在預定形成之相鄰第二引線的間隙下方形成一遮光層。 1286259 13130twf.doc/006 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 請參考圖2與3，其分別繪示本發明之一種薄膜電晶 體陣列基板的上視示意圖及其局部剖面示意圖。薄膜電晶 體陣列基板210例如可分為一晝素區2l〇a以及位於晝素 區210a外圍之一周邊線路區2i〇b，其中畫素區210a内 之透明基板202上例如配置有多個薄膜電晶體構成的薄膜 電晶體陣列212以及晝素電極(未繪示出），而週邊線路區 210b内之透明基板2〇2上例如配置有連接薄膜電晶體陣 列的多條引線，其例如可以是閘極配線232或源極配線 234。此外，閘極配線232與源極配線234末端更分別對 應連接有用以與外界電路接合的多個第一接墊232a與多 個第二接墊234a。另外，如圖3所示，薄膜電晶體陣列212 例如包括一閘極層214、一絕緣層216、一通道層218、 一源極/汲極層220以及一保護層222等膜層，其中周邊 線路區210b内之閘極配線232與閘極層214係同一膜層。 如圖3所示，本發明為避免閘極配線232之間產生 漏光的現象，係於閘極配線232上方形成有一圖案化之第 一遮光層242，其中此第一遮光層.242至少覆蓋相鄰問極 配線232之間的間隙，且此第一遮光層242例如可以是與 源極/汲極層220同時形成，其詳細結構請參考圖4 會 示之閘極配線232處的局部剖面放大圖。同理，本發明在 1286259 13130twf.doc/006 源極配線234處亦可同樣形成有遮光層，請參考圖$所示 之源極配線234處的局部剖面放大圖，其巾—圖案化之第 二遮光層244例如位於源極配線234之下方，並對應相鄰 源極配線234之__配置，而第二遮光層244例如可 以是與閘極層214同時形成。 ^承上所述，本發明之薄膜電晶體陣列基板210可藉 由第-遮光層242與第二遮光層244遮蔽相鄰閘極配線 232或相鄰源極配線234之間隙，其中本發明可在形成薄 膜電晶體陣列212的同時，對第一遮光層242與第二遮光 層244進行圖案化的動作，以使第一遮光層242與第二^遮 光層244僅對應相鄰閘極配線232或相鄰源極配線2料的 ，隙配置。因此，本發明與其他遮光層全面覆蓋引線的設 計相較之下，可大幅降低電阻_電容遲滯（RC dday)的 現象。當然，在考慮實際製程可能造成的誤差之下，亦可 使遮光層（第一遮光層242與第二遮光層244)與漏光區 域（相鄰閘極配線232與相鄰源極配線234之間隙）有部 分重疊。 ° 々在本發明之另一實施例中，上述之第一遮光層242 與第一遮光層244更可分別延伸至第一接墊242a與第二 接墊244a處，以避免可能發生之斜視漏光的問題。請參 考圖6與7，其分別繪示本發明之另一實施例之第一接墊 處與第二接墊處的上視示意圖。如圖6所示，第一遮光層 242除覆蓋相鄰閘極配線232的間隙之外，更延伸覆蓋相 鄰第一接墊232a的間隙。此外，如圖7所示，第二遮光 1286259 13130twf.doc/006 層244除覆蓋相鄰源極配線说的間 相鄰第二接墊234a的間隙。 更I伸覆盍 另外，依照本糾之特徵，本發日収可藉 接墊而對上述之第-遮光層242與第二遮光層Μ 穩定之，如此將可有效改善 2、 源極配線234)之相互干捧而道劫批」職配線232或 中抓m t干擾而*致顯不晝質不佳的問題。 逸/-雪:於,/加電虔’更有助於在對薄膜電晶體陣列 進灯電性檢檢查㈣線與遮光層之間是否短 路0 為了詳細說明本發明之特徵，下文係針對上述之 膜電晶體陣列基板210的製作方法加以說明。請參考圖8a 〜8E，其依序繪示本發明之薄膜電晶輯列基板的 流程示意圖。 首先，如8A所示，提供一透明基板2〇2，其十透明 基板202上具有一晝素區212a與一周邊線路區212b，且 透明基板202例如是一玻璃基板或一塑膠基板。 接著，如圖8B所示，在畫素區212a形成一金屬層 (未繪不），並圖案化此金屬層以於晝素區212a内定義 出一圖案化之閘極層214,並且於周邊線路區212b内定 義出多條閘極配線232與連接閘極配線232的多個第一接 墊（未繪示）。其中，形成此金屬層之方法例如是濺鍍法。 接著，如圖8C所示，在透明基板202上形成一絕緣 層216，以使絕緣層216覆蓋住閘極層214以及閘極配線 232。其中，形成絕緣層216的方法例如是以電漿化學氣 1286259 13130twf.doc/006 相沈積法沈積一氮化矽層或是一氧化矽層。 然後’如@ 8D所示，在絕緣層216上形成形成一通 道材質層（未繪示），並圖案化此通道材質層，以於閘極 212上方的絕緣層216上定義出一通道層218。其中，通 道層218的材質例如是非晶矽（a_si)。 ’ 之後，如圖8E所示，在透明基板2〇2上形成另一金 屬層（未繪示），並圖案化此金屬層，以於晝素區212& 内疋義出一圖案化之源極/没極層220，並且於周邊線路 區212b内定義出多條源極配線234以及連接於源極配線 234的多個第二接墊（未繪示）。此外，本發明更同時在 相鄰閘極配線232的間隙上方定義出一第一遮光層242, 而依照本發明之特徵，第一遮光層242更可延伸遮蓋相 第一接墊的間隙。 當然，在基板202上更包括形成其他諸如保護層 (如圖3所示）、電極膜（未繪示）及配向膜（未繪示） 等膜層，然其相關製作流程已為此技術領域者所熟知，本 發明在此不再詳細敘述。 承上述，在本發明之一實施例中，更可在形成閘極 層214的同時，定義出一第二遮年層244 (如圖5與7所 示），其中所形成之第二遮光層244係對應於預定形成之 相鄰源極配線234的間隙下方，而.依照本發明之特徵，第 二遮光層244亦可延伸遮蓋預定形成之相鄰第二接墊242 的間隙。 綜上所述，本發明之薄膜電晶體陣列基板及其製作 12 1286259 13130twf.doc/〇〇6 方法係於製作薄膜電晶體的同時，在周邊線路區内可能發 生漏光的區域形成遮光層，其中與閘極層同時形成之遮光 層可用以遮蔽源極配線及其接墊間之漏光，而與源極/汲 極層同時形成之遮光層可用以遮蔽閘極配線及其接墊間之 漏光。當然，在不脫離本發明的精神範圍内，本發明之薄 膜電晶體陣列基板及其製作方法亦可僅於閘極配線處或源 極配線處其中之一，或較可能產生漏光現象之部分周邊線 路區形成遮光層，以節省製作成本與製程時間。值得一提 的是，雖然上述實施例之遮光層係與薄膜電晶體之閘極層 或源極/汲極層同時形成，但在不考慮製程時間與成本之 前提下，本發明之遮光層亦可以與閘極層或源極/汲極層 分開製作，而遮光層之材質除了金屬之外，苴更可 樹脂或其他具遮光效果之材質。 ....... 本發明之薄膜電晶體陣列基板及其製作方法至少具 有下列特徵及優點： μ J ^對遮光層進行圖案化，以減少遮光層與引線 之重且區目而可有效降低遮光層與引線間之電阻電容 遲滞（RC delay)的現象。 ，因此更有助於改 (二）遮光層可延伸至接墊之間 善斜視漏光的問題。 C三）遮光層上可外加一穩定電壓，用以 間的訊號干擾程度，因而有助於顯示品質的提昇。 (四）遮光層上具有外加之穩定電壓，因此可在 膜電晶體陣列進行電性檢測時，同時檢出引線與遮光層 I286259_6 間是否短路 神和範圍内，當可作忒:=二不=:= ==Γ請專細所界定者為準 圖 圖 —為習知之—種液晶顯示器模組的剖面示意 之一種薄膜電晶體陣列 思圖。 剖面放大圖。 剖面放大圖。 之另一實施例之第一接 圖2與3分別緣示為本發明 基板的上視示意圖及其局部剖面示 圖4繪示為閘極配線處的局部 圖5繪示為源極配線處的局部 圖6與7分別緣示為本發明 墊處與第二接墊處的上視示意圖。 之薄膜電晶體陣列基板 圖8Α〜8Ε依序緣示為本發明 的製作流程示意圖。 【主要元件符號說明】 110 :薄膜電晶體陣列基板 UOa :畫素區 110b :周邊線路區 112 :引線 1286259 13130twf.doc/006 120 :彩色濾光膜基板 122 :黑矩陣層 130 :框膠 140 :液晶層 152、154 :偏光板 160 :外框 170 :可能漏光之區域1286259 13130twf.d〇c/〇〇6 IX. Description of the Invention: [Technical Field] The present invention relates to a display panel and a method of fabricating the same, and more particularly to a thin film transistor array substrate and a method of fabricating the same . [Prior Art] With the dramatic advancement of computer performance and the high development of Internet and multimedia technologies, most of the current image information transmission has been converted from analog to digital. In order to cope with the modern lifestyle, the size of video or video devices is becoming thinner and lighter. Conventional cathode ray tube (CRT) displays have always dominated the display market in recent years due to their superior display quality and economy. However, for the majority of individuals operating on the table: = the environment of the machine / display device, or from the perspective of environmental protection, if the trend of = Lang energy, to predict, the cathode ray tube due to space utilization and monthly b = w Xiao consumption There are still many problems, and the need for light, thin, short, small, and low power consumption cannot effectively provide a solution. ▲Because, in recent years, with the combination of optoelectronic technology and semiconductor manufacturing technology, the flat panel display has been flourishing. Liquid crystal display (LCD) is based on its low voltage operation and no radiation. The advantages of line scattering, light weight and small volume have gradually replaced the traditional cathode ray tube display and become the mainstream of recent products. FIG. 1 is a schematic diagram of a conventional liquid crystal display module. For simplicity of illustration, FIG. 1 only illustrates the description. The liquid crystal display module includes at least a thin film transistor array substrate. 1286259 13130twf.doc/006 110, color filter film substrate 120, black matrix layer 122, sealant 130, liquid crystal layer 140, polarizing plates 152, 154 and outer frame 160. The black matrix layer 122 is arranged in color filter. On the film substrate 120, the sealant 130 is disposed between the color filter film substrate 120 and the thin film transistor array substrate 11B, and the liquid crystal layer 140 is disposed on the color filter, the light film substrate 120 and the thin film transistor array substrate 110. The polarizing plates 152 and 154 are disposed on the other side surface of the unconfigured liquid crystal layer 140 of the thin film transistor array substrate 11 and the color filter film substrate 120, respectively. The outer frame 160 is disposed on the polarizing plate 152. In addition, the thin film transistor array substrate 110 can be divided into a pixel area lla and a peripheral line area ii 〇 b, wherein the peripheral line area ll 〇 b is configured with a plurality of leads 112 to act as a display In order to form the liquid crystal layer 140, a closed region is first formed between the thin film transistor array substrate 110 and the color filter film substrate 12 by the sealant 130, and then the capillary principle is utilized. The external atmosphere slowly injects the liquid crystal into the enclosed area surrounded by the thin film transistor array substrate 110 and the color filter film substrate 120. Since this injection process is time consuming, in order to cope with the mass production demand of the future large-size liquid crystal panel, it has recently been proposed. A technique of liquid crystal dropping (ODF). The so-called liquid crystal dropping technique first forms a frame seal 13 on a thin film transistor array substrate 11 or a color filter film substrate 120, and then drops the liquid crystal into the sealant 13 In the region surrounded by the crucible, the thin film transistor array substrate 11 is then bonded to the color filter film substrate 120, and the frame adhesive 13 is hardened by ultraviolet light to bond the two substrates. I2862^?0tw, Doc/006 It is worth mentioning that, in order to make the sealant 130 uniformly exposed to ultraviolet light to avoid contamination of part of the liquid crystal 140 due to incomplete curing of the sealant 130, color filtering is usually performed. The black matrix layer 122 on the film substrate 110 is recessed a certain distance toward the center of the panel. However, due to the indentation of the black matrix layer 122, a region 170 of possible light leakage is generated between the black matrix layer 122 and the sealant 130, and more because There is no light-shielding barrier between the leads 112 in the peripheral circuit area i1〇b, so the light 18 emitted by the backlight module may pass through the gap between the leads 112, and the outer frame 16〇 and the thin film transistor array substrate 110 SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a thin film transistor array substrate and a method of fabricating the same, which can solve the problem of light leakage caused by the surrounding lines. Based on the above object, the present invention provides a thin film transistor array substrate having a halogen region and a peripheral circuit located at a periphery of the halogen region. The thin film transistor p train substrate includes, for example, a transparent substrate and a film. a body array, a plurality of first leads, a plurality of second leads, and a first cover, wherein the thin film transistor array is disposed in the transparent region of the halogen region; the thunder-lead thin film transistor array includes at least - - a conductive layer and a second layer, in addition, the first lead is disposed in the peripheral line region, the transparent i-series is arranged in a conductive layer of the same film, and the second lead is in the peripheral line (10) through the county plate, and The first lead layer is located on the peripheral line soil, and the first light shielding layer corresponds to the adjacent first lead I2862^i?0tw, doc/006 ... A light shielding layer and a second conductive layer are the same film layer. Based on the above object, the present invention further provides a method for performing a film on a thin film transistor array substrate. First, a transparent substrate is provided, and the transparent substrate has a halogen region and a peripheral wiring region. Next, a patterned gate layer is formed in the pixel region, and at the same time, a plurality of first leads and a plurality of first touches connected to the first leads are formed in the peripheral line region. Then, an insulating layer is formed on the transparent substrate such that the insulating layer covers the gate layer and the first wiring. Then, after forming a patterned channel layer-a on the insulating layer above the gate layer, a patterned source/drain layer is formed on the channel layer, and at the same time, the second lead is formed in the peripheral line region. And a plurality of second contacts connected to the second bow line, wherein a source layer is formed, and a first light shielding layer is formed over the gap of the adjacent first leads. Based on the above object, the present invention further proposes a method of fabricating another thin film transistor array substrate. First, a transparent substrate is provided, and the transparent substrate has an I-region and a peripheral wiring region. Next, a patterned gate layer is formed in the pixel region, and at the same time, a plurality of first bow lines and a plurality of first pads connected to the first leads are formed in the peripheral line region. Then, an insulating layer is formed on the transparent substrate so that the insulating layer covers the gate layer and the first line. Next, a patterned channel layer is formed on the insulating layer above the gate layer: afterwards, a patterned source/drain layer is formed on the channel layer, and at the same time, a plurality of second leads are formed in the peripheral line region. And a plurality of second pads connected to the second lead. Wherein, while forming the gate layer, a light shielding layer is further formed under the gap of the adjacent second lead which is to be formed. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] Please refer to Figs. 2 and 3, which are respectively a top view of a thin film transistor array substrate of the present invention and a partial cross-sectional view thereof. The thin film transistor array substrate 210 can be, for example, divided into a halogen region 2l〇a and a peripheral line region 2i〇b located at a periphery of the pixel region 210a, wherein a plurality of thin films are disposed on the transparent substrate 202 in the pixel region 210a, for example. a thin film transistor array 212 composed of a transistor and a halogen electrode (not shown), and a plurality of leads connected to the thin film transistor array are disposed on the transparent substrate 2〇2 in the peripheral line region 210b, for example, Gate wiring 232 or source wiring 234. In addition, the gate wiring 232 and the end of the source wiring 234 are respectively connected to a plurality of first pads 232a and a plurality of second pads 234a for bonding with external circuits. In addition, as shown in FIG. 3, the thin film transistor array 212 includes, for example, a gate layer 214, an insulating layer 216, a channel layer 218, a source/drain layer 220, and a protective layer 222. The gate wiring 232 in the wiring region 210b and the gate layer 214 are the same film layer. As shown in FIG. 3, in order to avoid the phenomenon of light leakage between the gate wirings 232, a patterned first light shielding layer 242 is formed over the gate wiring 232, wherein the first light shielding layer 242 covers at least the phase. The first light shielding layer 242 may be formed at the same time as the source/drain layer 220. For the detailed structure, please refer to the partial cross-section of the gate wiring 232 shown in FIG. Figure. Similarly, the present invention can also form a light shielding layer at the source wiring 234 of the 1286259 13130 twf.doc/006. Please refer to the partial cross-sectional enlarged view of the source wiring 234 shown in FIG. The second light shielding layer 244 is disposed under the source wiring 234 and corresponding to the adjacent source wiring 234, and the second light shielding layer 244 may be formed at the same time as the gate layer 214. As described above, the thin film transistor array substrate 210 of the present invention can shield the gap between the adjacent gate wiring 232 or the adjacent source wiring 234 by the first light shielding layer 242 and the second light shielding layer 244, wherein the present invention can The first light shielding layer 242 and the second light shielding layer 244 are patterned while the thin film transistor array 212 is formed, so that the first light shielding layer 242 and the second light shielding layer 244 correspond to only the adjacent gate wiring 232. Or adjacent source wiring 2, the gap configuration. Therefore, the present invention can greatly reduce the phenomenon of resistance_capacitance hysteresis (RC dday) as compared with the design in which other light shielding layers cover the entire lead. Of course, under the error that may be caused by the actual process, the light shielding layer (the first light shielding layer 242 and the second light shielding layer 244) and the light leakage region (the gap between the adjacent gate wiring 232 and the adjacent source wiring 234) may also be used. ) There is a partial overlap. In another embodiment of the present invention, the first light shielding layer 242 and the first light shielding layer 244 may extend to the first pad 242a and the second pad 244a, respectively, to avoid possible squint leakage. The problem. Referring to Figures 6 and 7, respectively, a top view of the first pad and the second pad of another embodiment of the present invention is shown. As shown in FIG. 6, the first light shielding layer 242 extends beyond the gap covering the adjacent gate wiring 232 to extend over the gap of the adjacent first pads 232a. Further, as shown in Fig. 7, the second light-shielding 1286259 13130 twf.doc/006 layer 244 covers the gap between the adjacent second pads 234a of the adjacent source wiring. In addition, according to the characteristics of the present modification, the first day of the present invention can be stabilized by the above-mentioned first-light-shielding layer 242 and the second light-shielding layer 借 by the pad, so that the source wiring 234 can be effectively improved. ) The mutual support and the robbery of the "provisional wiring 232 or in the middle of the mt interference and * caused by poor quality problems.逸/-雪:在,/电电虔' is more helpful in whether or not to short-circuit between the (4) line and the light-shielding layer in the photo-electrical crystal array. In order to explain the features of the present invention in detail, the following is directed to the above A method of fabricating the film transistor array substrate 210 will be described. Referring to Figures 8a-8E, a schematic flow chart of the thin film electro-crystal array substrate of the present invention is sequentially illustrated. First, as shown in Fig. 8A, a transparent substrate 2 is provided, and the ten transparent substrate 202 has a halogen region 212a and a peripheral wiring region 212b, and the transparent substrate 202 is, for example, a glass substrate or a plastic substrate. Next, as shown in FIG. 8B, a metal layer (not shown) is formed in the pixel region 212a, and the metal layer is patterned to define a patterned gate layer 214 in the pixel region 212a. A plurality of gate wirings 232 and a plurality of first pads (not shown) connecting the gate wirings 232 are defined in the line region 212b. Among them, a method of forming the metal layer is, for example, a sputtering method. Next, as shown in Fig. 8C, an insulating layer 216 is formed on the transparent substrate 202 so that the insulating layer 216 covers the gate layer 214 and the gate wiring 232. The method of forming the insulating layer 216 is, for example, depositing a tantalum nitride layer or a hafnium oxide layer by a plasma chemical gas deposition method of 1286259 13130 twf.doc/006. Then, as shown in @8D, a channel material layer (not shown) is formed on the insulating layer 216, and the channel material layer is patterned to define a channel layer 218 on the insulating layer 216 above the gate 212. . The material of the channel layer 218 is, for example, amorphous germanium (a_si). After that, as shown in FIG. 8E, another metal layer (not shown) is formed on the transparent substrate 2〇2, and the metal layer is patterned to form a patterned source in the pixel region 212& The pole/no-pole layer 220 defines a plurality of source wirings 234 and a plurality of second pads (not shown) connected to the source wirings 234 in the peripheral line region 212b. In addition, the present invention further defines a first light shielding layer 242 over the gap of the adjacent gate wiring 232. According to the features of the present invention, the first light shielding layer 242 is further extendable to cover the gap of the first spacer. Of course, the substrate 202 further includes other layers such as a protective layer (as shown in FIG. 3), an electrode film (not shown), and an alignment film (not shown), but the related manufacturing process has been the technical field. As is well known, the invention will not be described in detail herein. In one embodiment of the present invention, a second opaque layer 244 (shown in FIGS. 5 and 7) may be defined while forming the gate layer 214, wherein the second light shielding layer is formed. 244 is below the gap of the adjacent source wiring 234 that is to be formed. According to a feature of the present invention, the second light shielding layer 244 may also extend to cover a gap of the adjacent second pads 242 that are to be formed. In summary, the thin film transistor array substrate of the present invention and the method for fabricating the same are used to form a thin film transistor, and a light shielding layer is formed in a region where light leakage may occur in a peripheral line region, wherein A light shielding layer formed simultaneously with the gate layer can be used to shield light leakage between the source wiring and its pads, and a light shielding layer formed simultaneously with the source/drain layer can be used to shield light leakage between the gate wiring and its pads. Of course, the thin film transistor array substrate of the present invention and the method of fabricating the same may be used only at one of the gate wiring or the source wiring, or a portion of the portion where the light leakage phenomenon is more likely to occur, without departing from the spirit of the present invention. A light shielding layer is formed in the line area to save manufacturing cost and process time. It is worth mentioning that although the light shielding layer of the above embodiment is formed simultaneously with the gate layer or the source/drain layer of the thin film transistor, the light shielding layer of the present invention is also raised before considering the process time and cost. It can be made separately from the gate layer or the source/drain layer, and the material of the light-shielding layer is made of resin or other light-shielding material in addition to metal. The thin film transistor array substrate of the present invention and the manufacturing method thereof have at least the following features and advantages: μ J ^ patterning the light shielding layer to reduce the weight and area of the light shielding layer and the lead wire can be effective Reduce the RC delay between the light shielding layer and the leads. Therefore, it is more helpful to change (2) the problem that the light shielding layer can extend to the good squint light leakage between the pads. C3) A stable voltage can be applied to the light-shielding layer for the degree of signal interference, which contributes to the improvement of display quality. (4) The externally applied stable voltage on the light-shielding layer, so that when the film transistor array is electrically detected, it is simultaneously detected whether the lead wire and the light-shielding layer I286259_6 are short-circuited within the range and the range, when it can be used as: 二==== := == Γ Please define the details of the thin-film transistor array as a cross-section of a liquid crystal display module. An enlarged view of the section. An enlarged view of the section. 2 and 3 respectively show a top view of the substrate of the present invention and a partial cross-sectional view thereof. FIG. 4 shows a portion of the gate wiring. FIG. 5 shows the source wiring. Partial Figures 6 and 7 respectively show the top view of the pad and the second pad of the present invention. The thin film transistor array substrate is shown in Fig. 8Α~8, which is a schematic diagram of the manufacturing process of the present invention. [Description of main component symbols] 110: Thin film transistor array substrate UOa: pixel area 110b: peripheral line area 112: lead 1286259 13130twf.doc/006 120: color filter film substrate 122: black matrix layer 130: sealant 140: Liquid crystal layer 152, 154: polarizing plate 160: outer frame 170: area where light may leak
180 :光線 202 :透明基板 210 :薄膜電晶體陣列基板 210a :晝素區 210b :周邊線路區 212 :薄膜電晶體陣列 214 :閘極層 216 :絕緣層180: Light 202: Transparent substrate 210: Thin film transistor array substrate 210a: Alizarin region 210b: Peripheral wiring region 212: Thin film transistor array 214: Gate layer 216: Insulation layer
218 :通道層 220 :源極/汲極層 222 :保護層 232 :閘極配線 232a :第一接墊 234 :源極配線 234a :第二接墊 242 :第一遮光層 244 :第二遮光層 15218: channel layer 220: source/drain layer 222: protective layer 232: gate wiring 232a: first pad 234: source wiring 234a: second pad 242: first light shielding layer 244: second light shielding layer 15