WO2014205904A1

WO2014205904A1 - Array substrate and manufacturing method therefor, and display device

Info

Publication number: WO2014205904A1
Application number: PCT/CN2013/081718
Authority: WO
Inventors: 袁剑峰; 冯玉春; 林承武
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2013-06-28
Filing date: 2013-08-19
Publication date: 2014-12-31
Also published as: CN103336396B; CN103336396A

Abstract

An array substrate, comprising a substrate (11), and a pixel electrode (14), a common electrode (16), a thin-film transistor (13) and a signal line (12) which are arranged on the substrate (11). The signal line (12) comprises a gate line, a data line and a common electrode line. The array substrate further comprises: an insulation layer (15) arranged between the pixel electrode (14) and the common electrode (16). The insulation layer (15) comprises: a first part (151) corresponding to a display area, and a second part (152) corresponding to a non-display area. The non-display area comprises: an area corresponding to the thin-film transistor (13) and the cabling of the signal line (12). The dielectric constant of the first part (151) is greater than a first critical value (ε1), the dielectric constant of the second part (152) is smaller than a second critical value (ε2), and the first critical value (ε1) is greater than the second critical value (ε2). The array substrate can not only reduce the stray capacitance at the cabling of the signal line, but can also solve the problem in the prior art that the drive voltage is higher due to the fact that an organic insulation film is arranged between the pixel electrode and the common electrode. Also provided are a manufacturing method for an array substrate and a display device.

Description

Array substrate, manufacturing method thereof and display device

The present invention relates to the field of display, and in particular to an array substrate, a method of manufacturing the same, and a display device. Background technique

Liquid crystal molecules of conventional liquid crystal displays (LCDs) generally switch between vertical-parallel states, and there are problems of angular anisotropy and narrow viewing angle. At present, many solutions have been proposed for this problem, such as In-Plane Switching (IPS) technology and Fringe Field Switching (FFS) technology.

The common feature of the IPS technology and the FFS technology is that the pixel electrode and the common electrode are disposed on the array substrate. Therefore, an insulating layer (usually a resin layer, or a passivation layer) or an insulating layer is required between the pixel electrode and the common electrode. a two-layer film structure of a resin layer and a passivation layer), the insulating layer is initially made of a silicon nitride insulating film, and the silicon nitride has a large dielectric constant (7 to 8), and a large pixel storage capacitor can be obtained, which contributes to driving reduction. Voltage, but the silicon nitride insulating film is difficult to fabricate, and the surface flatness of the array substrate cannot be ensured (flatness is advantageous for reducing the incidence of defects such as polyimide (PI) coating and rubbing alignment), and Due to the large dielectric constant of silicon nitride, there is often a large parasitic capacitance at the data lines, gate lines, and the like. Therefore, the insulating layer between the existing pixel electrode and the common electrode is generally an organic insulating film such as a resin layer. The dielectric constant (3 to 4) of the resin is smaller than that of silicon nitride, and the fabrication is simple. The introduction of the array substrate can charge the LCD. Reduced time (reduced parasitic capacitance at the trace), guaranteed charging rate, increased LCD aperture ratio and surface flatness of the array substrate, but also due to the small dielectric constant of the resin, the pixel storage capacitor is relatively small, and there is a driving voltage bias. High problem. Summary of the invention

The invention provides an array substrate, a manufacturing method thereof and a display device, which can reduce the parasitic capacitance at the signal line trace and solve the driving problem caused by the organic insulating film disposed between the pixel electrode and the common electrode in the prior art. The problem of high voltage.

In order to achieve the above object, the present invention provides the following technical solutions: An array substrate comprising a substrate and a pixel electrode, a common electrode, a thin film transistor and a signal line disposed on the substrate, the signal line comprising a gate line, a data line and a common electrode line, the array substrate further comprising:

An insulating layer disposed between the pixel electrode and the common electrode, the insulating layer including a first portion corresponding to the display region and a second portion corresponding to the non-display region, the non-display region including the thin film transistor and The area corresponding to the signal line trace,

The dielectric constant of the first portion is greater than a first threshold, the dielectric constant of the second portion is less than a second threshold, and the first threshold is greater than the second threshold.

Preferably, the material of the insulating layer has the following characteristics: After ultraviolet light irradiation, the dielectric constant becomes large.

Specifically, the first portion of the insulating layer is subjected to ultraviolet light irradiation during the manufacturing process, and the second portion of the insulating layer is not subjected to ultraviolet light irradiation during the manufacturing process.

Optionally, the insulating layer is an organic insulating film.

Further, the array substrate further includes a passivation layer;

The present invention further provides a display device in which the passivation layer is disposed closer to the surface of the array substrate than the insulating layer, comprising: the array substrate described above.

Correspondingly, the present invention further provides a method for fabricating an array substrate, comprising the steps of: forming an insulating layer on a substrate on which a first electrode is formed, wherein the insulating layer is made of a material having a higher dielectric constant after being irradiated with ultraviolet light; production;

Forming a second electrode on the substrate on which the first electrode and the insulating layer are formed;

The array substrate is subjected to ultraviolet light from a side of the non-face to face of the array substrate.

Optionally, the first electrode is a pixel electrode, and the second electrode is a common electrode.

Alternatively, the first electrode is a common electrode, and the second electrode is a pixel electrode. Alternatively, after the second electrode is formed on the substrate on which the first electrode and the insulating layer are formed, the method further includes the step of: forming a passivation layer on the substrate on which the insulating layer is formed.

The array substrate provided by the present invention, the manufacturing method thereof and the display device are provided with an insulating layer between the pixel electrode and the common electrode. On the one hand, the dielectric constant of the first portion corresponding to the display region on the insulating layer is greater than the first critical value. The purpose of increasing the pixel storage capacitance and lowering the driving voltage can be achieved; on the other hand, the dielectric constant of the second portion corresponding to the non-display area on the insulating layer is less than the second critical value (the first critical value is greater than The second critical value) can reduce the parasitic capacitance existing in the non-display area (the area corresponding to the thin film transistor and the signal line trace), ensure the charging rate, and ensure the display effect. DRAWINGS

1 is a schematic plan view showing a planar structure of an array substrate according to Embodiment 1 of the present invention;

2 is a cross-sectional structural view of the array substrate of FIG. 1 taken along line A-A';

3 is a schematic view of an array substrate fabricated by irradiating a substrate with ultraviolet light according to Embodiment 1 of the present invention;

4 is a schematic structural diagram of an optional array substrate according to Embodiment 1 of the present invention; FIG. 5(a) is a schematic diagram showing the position of a passivation layer in an array substrate according to an embodiment of the present invention; Embodiment 1 is a schematic diagram of a position of a passivation layer in an array substrate; FIG. 6 is a flow chart 1 of a method for manufacturing an array substrate according to Embodiment 2 of the present invention;

7 is a second flowchart of a method for manufacturing an array substrate according to Embodiment 2 of the present invention;

FIG. 8 is a schematic view showing a manufacturing process corresponding to the method of manufacturing the array substrate shown in FIG. 7. FIG.

Reference numeral

10-array substrate, 11-substrate, 12-signal line, 13-thin film transistor, 14-pixel electrode, 15-insulation layer, 151-first part of insulating layer, 152-second part of insulating layer,

153-silicon nitride layer, 154-resin layer, 16-common electrode, 17-passivation layer,

20-color film substrate, 22-color film color resistance, 23-black matrix, 30-ultraviolet light. Specific real The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Embodiment 1

An embodiment of the present invention provides an array substrate. As shown in FIG. 1 and FIG. 2 , the array substrate includes a substrate 11 and a thin film transistor 13 , a pixel electrode 14 , a common electrode 16 , a signal line 12 , and a signal line disposed on the substrate 11 . 12 includes a gate line, a data line, and a common electrode line. The array substrate further includes: an insulating layer 15 disposed between the pixel electrode 14 and the common electrode 16. The insulating layer 15 includes: a first portion 151 corresponding to the display area, and A second portion 152 corresponding to the display area, the second portion 152 includes a region corresponding to the trace of the thin film transistor 13 and the signal line 12; the dielectric constant of the first portion 151 is greater than the first critical value ε ΐ , and the dielectric constant of the second portion 152 Less than the second critical value ε2, the first critical value εΐ is greater than the second critical value ε2.

The pixel electrode 14 and the common electrode 16 in this embodiment are both disposed on the substrate 11. The array substrate and the color filter substrate are filled with liquid crystal after the box, and the liquid crystal molecules are located above the common electrode 16 in FIG. 2, and the display signal is loaded through the thin film transistor 13. The driving electric field formed between the pixel electrode 14, the pixel electrode 14 and the common electrode 16 drives the liquid crystal molecules to be deflected, thereby displaying an image.

In the present embodiment, an insulating layer 15 is disposed between the pixel electrode 14 and the common electrode 16, the first portion 151 of the insulating layer 15 corresponds to the display region, and the second portion 152 corresponds to the non-display region. Referring to FIG. 3, the display area, that is, the area through which the backlight is permeable on the array substrate (also referred to as a light-transmitting area) and the color film color resist 22 (refer to FIG. 3, generally located on the color filter substrate 20) Corresponding to the position; the non-display area, that is, the area corresponding to the trace of the thin film transistor 13 and the signal line 12, the backlight cannot be emitted due to the occlusion of the metal layer or the metal trace, and the non-display area and the black matrix after the pair of boxes 23 (the general position on the color filter substrate 20) corresponds to the position.

The first portion 151 corresponds to the display area, and since the display area substantially corresponds to the pixel electrode 16, it can be obtained by the capacitance formula Cst=sSA^kd (k, π is a constant): Positive at the electrode (collectively referred to as the pixel electrode and the common electrode) In the case where the area d and the pitch d of the electrodes do not change, the pixel storage capacitance Cst increases as the dielectric constant ε of the first portion 151 increases. Further, from the formula Q=UC=IAt, the driving voltage Vop (Vop=IAt/Cst) decreases as the pixel storage capacitor Cst increases. And second The portion 152 corresponds to the non-display area (the thin film transistor 13 and the signal line 12 routing area). In order to prevent the parasitic capacitance in the non-display area from affecting the liquid crystal driving, thereby affecting the display effect, the technical solution provided in this embodiment ensures insulation. On the other hand, on the one hand, the dielectric constant of the second portion 152 is kept at a lower level (less than the second critical value ε2) to reduce the parasitic capacitance; on the other hand, the dielectric constant of the first portion 151 is increased as much as possible (greater than the first The threshold value ε1 ) increases the pixel storage capacitor Cst to lower the driving voltage Vop to ensure the display effect.

In the embodiment, the dielectric constant of the first portion 151 is greater than the first critical value ε1. In the specific implementation, the first portion 151 is made of a material having a large dielectric constant as much as possible under the premise of satisfying other conditions such as insulation and preparation processes. In general, the value of the first critical value ε 满足 satisfies ε1 ≥ 4.5; the dielectric constant of the second portion 152 is smaller than the second critical value ε2, and the first critical value ε ΐ is greater than the second critical value ε 2 , and the second portion 152 Under the premise of satisfying other conditions such as insulation and preparation process, a material having a small dielectric constant is selected as much as possible. Generally, the value of the second critical value ε2 satisfies ε2 ≤ 3.

It should be noted that the insulating layer 15 in this embodiment may be a single layer or a composite layer. For example, silicon nitride has a dielectric constant of 7 to 8, and a resin has a dielectric constant of 3 to 4. In an alternative embodiment, as shown in FIG. 4, patterned nitride is formed using silicon nitride. The silicon layer 153, the silicon nitride layer 153 is only distributed in the display region; then the resin is coated to form the resin layer 154 to ensure the flatness of the surface of the array substrate. The silicon nitride layer 153 and the resin layer 154 together constitute the insulating layer 15 in this embodiment. The first portion 151 of the insulating layer 15 includes a silicon nitride layer 153 and a resin layer 154. The dielectric constant of the first portion 151 is understood to be nitriding. The silicon layer 153 and the resin layer 154 have an equivalent dielectric constant, and the resin layer 154 of the first portion 151 is generally thin, so that the equivalent dielectric constant of the first portion 151 is close to 7 to 8; the second portion 152 of the insulating layer 15 is only The resin layer 154 is included, and therefore, the dielectric constant of the second portion 152 is the dielectric constant of the resin layer 154.

Therefore, in the preparation of the insulating layer 15, the insulating layer 15 can be formed in steps, and the first portion 151 and the second portion 152 which finally form the insulating layer 15 can be formed through a preparation step as in the prior art. The following embodiments are a preferred embodiment of the present embodiment, and the specific embodiments described herein are merely illustrative of the embodiments and are not intended to be limiting.

In the preferred embodiment of the embodiment, the material of the insulating layer 15 has the following characteristics: Point: The dielectric constant becomes larger after irradiation with ultraviolet light. And for better display, insulation

The dielectric constant of the selected material is generally not less than the dielectric constant of the prior art insulating layer material such as the resin layer.

Specifically, as shown in FIG. 3, the insulating layer 15 is prepared by using the material having a large dielectric constant after ultraviolet light irradiation, and of course, the insulating requirements and the process preparation requirements are also required, and then the array substrate 10 is prepared according to a conventional procedure. Before the array substrate 10 is placed on the cassette, the array substrate 10 is irradiated with ultraviolet light 30 from the side of the non-opposing surface of the array substrate 10. The side of the non-opposing surface described herein refers to the side of the array substrate 10 that is close to the backlight. The display area (light-transmitting area) is permeable to light, and the first portion 151 corresponding to the display area is subjected to ultraviolet light 30 irradiation during the manufacturing process, and the ultraviolet light 30 is irradiated to make the dielectric constant of the first portion 151 large; the non-display area and the film The transistor 13 and the signal line 12 are correspondingly routed. Due to the occlusion of the metal layer or the metal trace, the second portion 152 corresponding to the non-display area is not subjected to the ultraviolet light 30 during the manufacturing process, and the dielectric constant remains unchanged.

The structure of the array substrate provided in this embodiment is substantially the same as that of the prior art, except that the insulating layer selects a material whose dielectric constant is sensitive to ultraviolet light irradiation, and after the preparation process of the array substrate is completed, the ultraviolet light irradiation step is added to make the insulating layer 15 The first portion 151 (corresponding to the electrode region) undergoes a physical or chemical change, thereby increasing the dielectric constant of the first portion 151, thereby increasing the pixel storage capacitance Cst and lowering the driving voltage Vop.

Preferably, the insulating layer is an organic insulating film. The organic insulating film is simple to manufacture (usually coated with a film), and the surface flatness of the array substrate can be ensured, which is advantageous for reducing the incidence of defects such as PI coating and rubbing orientation.

Further, as shown in FIG. 5(a) and FIG. 5(b), the array substrate further includes: a passivation layer 17; the passivation layer 17 is disposed closer to the array substrate than the insulating layer 15 One side of the face. The array substrate is opposite to the surface of the array substrate on the array substrate near the color filter substrate. Since the passivation layer 17 is disposed on the side closer to the face of the array substrate, the introduction of the passivation layer 17 does not affect the intensity of the ultraviolet light to the insulating layer 15. Specifically, as shown in FIG. 5(a), the passivation layer 17 may be disposed above the insulating layer 15 below the common electrode 16; or as shown in FIG. 5(b), the passivation layer 17 may be used. It is disposed above the common electrode 16. It is to be noted that, in the drawings of the present embodiment, only the case where the pixel electrode 14 is closer to the substrate 11 than the common electrode 16 is shown, but the present invention can be applied even if the positions of the pixel electrode and the common electrode are interchanged.

The array substrate provided by the invention can reduce the parasitic capacitance at the signal line trace and solve the problem of high driving voltage caused by the organic insulating film disposed between the pixel electrode and the common electrode in the prior art. The present invention also provides a display device comprising any of the above array substrates. The display device has a small driving voltage, saves energy and saves power, and at the same time, reduces the influence of parasitic capacitance on the display effect, thereby obtaining higher display quality. The display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Embodiment 2

The present invention also provides a method of fabricating an array substrate. As shown in FIG. 6, the method includes the following steps:

101: forming an insulating layer on a substrate on which the first electrode is formed, the insulating layer being made of a material having a large dielectric constant after being irradiated with ultraviolet light;

102: forming a second electrode on the substrate on which the first electrode and the insulating layer are formed, completing a conventional manufacturing process of the array substrate;

103: UV-illuminating the array substrate from a side of the non-face to face of the array substrate.

Optionally, when the first electrode is a pixel electrode, the second electrode is a common electrode; and when the first electrode is a common electrode, the second electrode is a pixel electrode.

The manufacturing method of the array substrate provided by the present invention is substantially the same as that of the prior art, except that the insulating layer selects a material whose dielectric constant is sensitive to ultraviolet light irradiation, and after the preparation process of the array substrate is completed, the ultraviolet light irradiation step is added to make the insulation. The first portion of the layer (corresponding to the electrode region) undergoes a physical or chemical change to increase the dielectric constant of the first portion, thereby increasing the pixel storage capacitance Cst and lowering the driving voltage Vop. Preferably, the insulating layer is an organic insulating film.

Further, after the second electrode is formed on the substrate on which the first electrode and the insulating layer are formed, or after the second electrode is formed on the substrate on which the first electrode and the insulating layer are formed, : a step of forming a passivation layer on a substrate on which the insulating layer is formed.

In order to enable those skilled in the art to better understand the method of fabricating the array substrate provided by the present invention, as shown in FIGS. 7 and 8, the method for fabricating the array substrate provided by the present invention will be briefly described below by way of specific embodiments.

Fig. 7 is a flow chart showing the manufacturing method of the array substrate shown in the cross-sectional view taken along line A-A' in Fig. 1, that is, an Array process flow. A schematic diagram of the manufacturing process corresponding to the Array process flow is depicted in Figure 8, which is substantially similar to the conventional array (Array) process, namely: Glass→Gate→SDT→ 1 st Organic→Pixel ITO→2nd Organic→Common ITO, except that 2nd Organic is an insulating layer interposed between the pixel electrode and the common electrode as described in the embodiment, and an organic insulating film whose dielectric constant ε is controlled by ultraviolet (UV) light is used.

The array substrate manufacturing method shown in FIG. 7 includes the following steps:

201: forming a gate metal layer (Gate) on the substrate (Glass), forming a gate and a gate line of the thin film transistor by a patterning process;

202: forming a gate insulating layer, a semiconductor layer, and a source/drain metal layer, and forming a thin film transistor 13 and a data line by a patterning process;

203: forming an interlayer insulating layer and a drain via on the substrate on which the thin film transistor and the data line are formed;

204: forming a transparent conductive layer on the substrate formed with the interlayer insulating layer, forming a pixel electrode 14 by a patterning process;

205: forming an insulating layer on the substrate on which the pixel 14 is formed. The insulating film 15 is preferably an organic insulating film whose dielectric constant ε can be controlled by ultraviolet (UV) light;

206: forming a transparent conductive layer on the substrate on which the insulating layer 15 is formed, forming a common electrode 16 by a patterning process;

207: performing ultraviolet light irradiation on the array substrate formed from one side of the non-aligned surface of the array substrate The ultraviolet light causes the dielectric constant ε of the organic insulating film corresponding to the light-transmitting region to increase.

The embodiment provides a method for fabricating an array substrate by irradiating a substrate with UV light. In this embodiment, the dielectric constant ε of the organic insulating film in the light-transmitting region is changed by UV light irradiation to achieve the purpose of increasing the pixel storage capacitor Cst. Thereby, the driving voltage Vop of the LCD to which the organic insulating film technology is applied is lowered. In the embodiment of the present invention, the FFS mode array substrate is taken as an example, but the application of the present invention is not limited thereto. The technical solution of the present invention is applicable to an application scenario in which an insulating layer needs to be disposed between all the pixel electrodes and the common electrode.

It should be noted that the technical features described in the embodiments of the present invention can be used in combination with each other without conflict.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

Claim

An array substrate comprising a substrate, a pixel electrode, a common electrode, a thin film transistor, and a signal line disposed on the substrate, wherein the signal line includes a gate line, a data line, and a common electrode line, and further includes:

An insulating layer disposed between the pixel electrode and the common electrode, the insulating layer including a first portion corresponding to the display region and a second portion corresponding to the non-display region, the non-display region including the thin film transistor and The area corresponding to the signal line trace;

2. The array substrate according to claim 1, wherein

The material of the insulating layer becomes large in dielectric constant after being irradiated with ultraviolet light.

3. The array substrate according to claim 2, wherein

The first portion of the insulating layer is subjected to ultraviolet light illumination during the manufacturing process, and the second portion of the insulating layer is not exposed to ultraviolet light during the manufacturing process.

The array substrate according to any one of claims 1 to 3, wherein

The insulating layer is an organic insulating film.

The array substrate according to any one of claims 1 to 4, wherein

Also includes a passivation layer,

The passivation layer is disposed closer to the surface of the array substrate than the insulating layer

6. A display device, characterized in that

The array substrate according to any one of claims 1 to 5, comprising:

A method of manufacturing an array substrate, comprising the steps of:

Forming an insulating layer on the substrate on which the first electrode is formed, the insulating layer being made of a material having a large dielectric constant after being irradiated with ultraviolet light;

Forming a second electrode on the substrate on which the first electrode and the insulating layer are formed; The array substrate is subjected to ultraviolet light from a side of the non-face to face of the array substrate.

8. The manufacturing method according to claim 7, wherein

The first electrode is a pixel electrode, and the second electrode is a common electrode.

9. The manufacturing method according to claim 7, wherein

The first electrode is a common electrode, and the second electrode is a pixel electrode.

The manufacturing method according to any one of claims 7 to 9, characterized in that

The insulating layer is an organic insulating film.

11. The manufacturing method according to claim 7, wherein

Before forming the second electrode on the substrate on which the first electrode and the insulating layer are formed, the method further includes the following steps:

A passivation layer is formed on the substrate on which the insulating layer is formed.

12. The manufacturing method according to claim 7, wherein

After the second electrode is formed on the substrate on which the first electrode and the insulating layer are formed, the method further includes the step of: forming a passivation layer on the substrate on which the insulating layer is formed.