TWI439778B - Pixel array substrate and display panel - Google Patents

Description

Pixel array substrate and display panel

The present invention relates to a pixel array substrate and a display panel, and more particularly to a pixel array substrate and a display panel having a double layer trace.

With the rapid development of display technology, display panels have been applied to display devices of various sizes, such as televisions, computer screens, notebook computers, mobile phones, and the like. Taking mobile phones as an example, in addition to the display performance of the display panel, such as resolution, contrast, and viewing angle, the requirements for the aesthetic appearance of the display panel are also increasing. Therefore, the display panel related manufacturers have mostly invested in the ranks of the slim boarder display panels, so that the display panels having the same display quality are more light, thin and short to meet the needs of consumers.

In order to realize a narrow-frame display panel, the operator needs to reduce the area of the surrounding traces to reduce the width of the border. In the prior art, a fine yellow light process technology is generally used to shorten the spacing between the peripheral traces, and a narrow bezel display panel is realized. However, with the development of smart phones, the resolution of the display panel is getting higher and higher, and the number of peripheral wires is also increasing, resulting in the frame width of the display panel being not easily reduced.

In a conventional narrow framed technique, a technique of double layer trace (Double Layer Trace) is proposed. The adjacent two peripheral traces adopt different film layers and overlap each other on the substrate, thereby reducing the width of the display panel degree. However, in the conventional two-layer routing technology, the problem of electrostatic destruction often occurs in two adjacent peripheral traces, and because the spacing between the peripheral traces is extremely different, the substrate has a difference in wiring of the peripheral traces. Different light transmittances lead to different degrees of hardening of the UV curing sealant applied to the peripheral traces in the subsequent sealant process, which makes the display panel susceptible to liquid crystal contamination and cannot pass the tensile test. (tensile test) and other issues.

In view of this, the present invention provides a pixel array substrate which can realize narrow frame and improve the problem of electrostatic destruction of adjacent two peripheral traces in a conventional pixel array substrate.

In addition, the present invention provides a display panel, which can realize a narrow frame, and can effectively solve the problem that the degree of hardening of the sealant in the prior art is too large (or the frame rubber hardening is incomplete) due to the excessive difference in the distance between the peripheral traces. .

The invention provides a pixel array substrate, which comprises a substrate, a plurality of pixel structures, a plurality of first traces and a second trace. The substrate includes a display area and a peripheral circuit area, and the peripheral circuit area is located outside the display area. The pixel structure array is arranged in the display area. A plurality of first traces and a second trace are located in the peripheral circuit area. The first trace and the second trace are electrically connected to the corresponding pixel structure respectively. The second trace is located above the first trace and is electrically insulated from the first trace. The first trace and the second trace extend from the display area in the column direction and are alternately arranged in the row direction. The projection of one of the first traces and the adjacent second trace on the substrate intersects each other by the inclined portion having the same slope Overlapping to form a set of double-layered traces.

The invention provides a display panel comprising the above pixel array substrate, a counter substrate and a display medium. The opposite substrate is opposed to the pixel array substrate. The display medium is located between the pixel array substrate and the opposite substrate.

In an embodiment of the present invention, the inclined portion includes a first inclined portion and a second inclined portion, and a length of the first inclined portion of each of the first wires is greater than a length of the second inclined portion of each of the second wires. And each of the second traces overlaps with a portion of the first inclined portion of the adjacent first trace by the second inclined portion thereof.

In an embodiment of the present invention, in each of the sets of double-layered wires, the first inclined portion has a first leading end and a first end, and the second inclined portion has a second leading end and a second end, the first The end overlaps the second end, and the second inclined portion overlaps the first inclined portion from the second leading end.

In an embodiment of the invention, each of the first traces and the second traces respectively have a first signal output portion and a second signal output portion extending from the display region in the column direction. The first signal output portion and the second signal output portion are parallel to each other and alternately arranged in the row direction. Among the two sets of double-layered wires, the second wire is fed into the second head end of the second inclined portion by the second signal output portion.

In an embodiment of the present invention, the second signal output portion of each of the second traces has an angle θ with the first inclined portion of the adjacent first trace, and the angle θ is substantially greater than or equal to 45 degrees and less than Equal to 90 degrees.

In an embodiment of the invention, the spacing between the inclined portions of the first traces is substantially equal.

In an embodiment of the invention, each of the pixel structures described above includes an active component and a pixel electrode. The active components include a source gate and a drain. painting The element electrode is electrically connected to the active element.

In an embodiment of the invention, the first trace and the second trace are respectively electrically connected to the gate of the active device.

In an embodiment of the invention, the first trace and the second trace are respectively electrically connected to a source of the active device.

In an embodiment of the present invention, the pixel array substrate may further include a plurality of sets of driving die pad sets, wherein the peripheral circuit area has adjacent frontal edge regions and terminal regions, and the first set of double layer traces The trace and the second trace extend from the display area to the front edge area, and each of the driving chip pad sets is located in the terminal area, and each driving chip pad group and the corresponding one of the two sets of double-layered wires are firstly routed and second Electrical connection.

In an embodiment of the invention, each of the sets of double-layered wires may further include an overlapping extension extending from the inclined portion. Each of the first traces and each of the second traces has a first signal receiving portion and a second signal receiving portion, and one end of the overlap extending portion is connected to the inclined portion, and each of the first traces and each of the second traces overlaps the extension portion. The other end is separated into a first signal receiving unit and a second signal receiving unit.

In an embodiment of the invention, the display panel may further include a sealant. The sealant is located between the pixel array substrate and the opposite substrate and surrounds the display medium, and the sealant is located in the peripheral circuit area and covers the inclined portion.

In an embodiment of the invention, the sealant comprises a light-curing frame sealant and a composite frame sealant.

Based on the above, in the pixel array substrate and the display panel of the present invention, one of each of the first traces and the adjacent second trace is on the substrate. The projection system intersects and overlaps each other by the inclined portions having the same slope. Therefore, the angle between the second signal output portion of each second trace and the inclined portion of the adjacent first trace can be designed to be a large angle, and the first The probability of static damage occurring on a trace or a second trace. In addition, the difference in the spacing between the traces can be optimized, so that it has higher process compatibility with the subsequent sealant process, and avoids the problem of different degrees of hardening of the frame sealant.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a top view of a pixel array substrate according to an embodiment of the invention. Referring to FIG. 1A , the pixel array substrate 100 of the embodiment includes a substrate 110 , a plurality of pixel structures 120 , a plurality of first traces L1 , and a plurality of second traces L2 .

The substrate 110 of this embodiment includes a display area R1 and a peripheral circuit area R2, and the peripheral circuit area R2 is located outside the display area R1. In this embodiment, the display area R1 is, for example, a rectangular area, and the peripheral circuit area R2 has an adjacent front edge area R2 _A and a terminal area R2 _B corresponding to the adjacent two sides S1 and S2 of the display area R1, respectively. The edge region R2 _{A is} connected to the terminal region R2 _B. In this embodiment, the substrate 110 is used for carrying components, and the material thereof may be glass, quartz, organic polymer, opaque/reflective material (for example, conductive material, wafer, ceramic, etc.) or other materials. Applicable materials.

The array of pixel structures 120 of this embodiment is arranged in the display area R1. In detail, the pixel structure 120 of the embodiment includes an active component T and a pixel. The pole PE is electrically connected to the corresponding scan line SL and the data line DL. The active device T includes a source S, a gate G, and a drain D. The pixel electrode PE is electrically connected to the active device T. In this embodiment, the active device T may be a thin film transistor (TFT), such as an amorphous silicon (a-Si) TFT, or a low temperature polycrystalline silicon transistor (Low Temperature Poly Silicon). (LTPS) TFT), metal oxide transistor (Oxide TFT), organic thin film transistor (OTFT), and the like.

As shown in FIG. 1A, the first trace L1 and the second trace L2 are located in the peripheral circuit region R2, and the first trace L1 and the second trace L2 are electrically connected to the corresponding pixel structure 120, respectively. Further, the first trace L1 and the second trace L2 extend from the display region R1 in the column direction D1, respectively, and are alternately arranged in the row direction D2. Specifically, the first trace and the second trace are respectively electrically connected to the gate G of the pixel structure 120, and the first trace L1 and the second trace L2 are alternately and respectively in the display region R1. Each scan line SL is electrically connected. For example, in the present embodiment, each scan line SL in the display area R1 extends, for example, along the column direction D1, and the scan line SL of the nearest terminal area R2 _B is used as the first a scan line, the first trace L1 of the embodiment extends from the end of the even-numbered scan lines SL from the display region R1 in the column direction D1 to the peripheral circuit region R2, and the second trace L2 is from the odd-numbered strips The end of the scanning line SL extends from the display region R1 in the column direction D1 to the peripheral circuit region R2, and the first trace L1 and the second trace L2 are alternately arranged along the row direction D2. The present invention is not limited thereto. In other embodiments, the first trace L1 and the second trace L2 may be electrically connected to the source S of the pixel structure 120, respectively. 1B, FIG. 1B is a schematic top view of a pixel array substrate according to an embodiment of the present invention. The first trace L1 may also be compared with the source S of the even-numbered pixel structure 120 from the terminal region R2 _B. The second trace L2 is also electrically connected to the source S of the odd-numbered pixel structure 120.

In this embodiment, the second trace L2 is located above the first trace L1 and is electrically insulated from the first trace L1. In other words, the second trace L2 and the first trace L1 belong to different layers. For example, the first trace L1 can belong to the same layer as the gate G of the active device T, and the second trace L2 can be The source S and the drain D above the gate G belong to another film layer, wherein the first trace L1 and the second trace L2 are electrically insulated from each other by a gate insulating layer sandwiched therebetween. The first trace L1 and the second trace L2 of the embodiment are used for transmitting signals. Based on the conductivity considerations, the first trace L1 and the second trace L2 are generally made of a metal material. However, the present invention is not limited thereto, and the first trace L1 and the second trace L2 may also use other conductive materials such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or A stacked layer of metallic material and other conductive materials.

In order to clearly illustrate the layout of the first and second traces of the pixel array substrate and the display panel of the present invention, the first trace and the second trace are respectively divided into different portions, and are matched with FIG. 1A. 2A and 2B are explained in detail. In detail, the first trace L1 and the second trace L2 are electrically connected to the signal line (scan line SL or data line DL) in the display area R1 and the drive chip (scan drive chip or data drive chip). Between the pads, in actual operation, the driving chip is mounted on the driving chip pad group, and the corresponding driving signals of the driving chip output are respectively via corresponding corresponding wires (the first wire L1 and the second wire L2) And input to the corresponding signal line in the display area R1, and thereby drive each pixel structure 120 in the display area R1. Therefore, in the following description, a section connecting the first trace L1 and the second trace L2 to the driving wafer pad group is referred to as a signal receiving portion L1 _I , L2 _I , and the first trace L1 and the first trace A section of the second trace L2 connected to the signal line in the display area R1 is referred to as a signal output section L1 _O , L2 _O . In addition, the overlapping area of the second trace L2 from the signal output portion L2 _O to the first trace L1 to become the double trace is defined as the inclined portion, and the region of the double-layer trace L different from the inclined portion is defined. Defined as overlapping extensions.

The details are as follows. The projection of one of the first traces L1 and the adjacent second traces L2 on the substrate 110 intersects and overlaps each other by the inclined portions Ls having the same slope to form a set of double-layer traces L. Referring to FIG. 2A and FIG. 2B, the projection of the second inclined portion L2 _{S of the} second trace L2 on the substrate 110 completely overlaps the projection of the first inclined portion L1 _S of the portion of the first trace L1 on the substrate 110. Therefore, the first inclined portion L1 _S and the second inclined portion L2 _S are collectively referred to as the inclined portion Ls. In detail, the inclined portion includes the first inclined portion L1 _S and the second inclined portion L2 _S extending in a direction different from the column direction D1 and the row direction D2, and the length of the first inclined portion L1 _S of each of the first traces L1 is larger than each a length of the second inclined portion L2 _S of the second trace L2, and each of the second traces L2 overlaps with the first inclined portion L1 _{S of the} adjacent first trace L by the second inclined portion L2 _{S thereof} , wherein The second inclined portion L2 _{S of} each of the second traces L2 coincides with a portion of the first inclined portion L1 _{S of the} adjacent first trace L. Further, in each set of double-layered traces L, the first inclined portion L1 _S has a first leading end L1 _SA and a first end L1 _SB , and the second inclined portion L2 _S has a second leading end L2 _SA and a The second end L2 _SB , the first end L1 _SB coincides with the second end L2 _SB , and the second head end L2 _SA is located between the first head end L1 _SA and the first end L1 _SB .

Further, each of the first traces L1 and the second traces L2 has a first signal output portion L1 _O and a second signal output portion L2 _{O , respectively} . The first signal output portion L1 _O and the second signal output portion L2 _O extend from the display region R1 in the column direction D1, and the first signal output portion L1 _O and the second signal output portion L2 _O are parallel to each other and alternate in the row direction D2. arrangement.

It is worth mentioning that in each set of double-layered lines L, the second line L2 is merged into the second head end L2 _{SA of the} second inclined portion L2 _S by the second signal output portion L2 _O. In other words, the second signal output portion L2 _O extending in the column direction D1 is connected to the second inclined portion between the first end L1 _SA of the first inclined portion and the first end L1 _SB of the first inclined portion. Headend L2 _SA . In this way, the angle θ between the second signal output portion L2 _O of each of the second traces L2 and the first inclined portion L1 _S of the adjacent first trace L1 is larger in design range. For example, the angle θ between the second signal output portion L2 _{O of} each second trace L2 and the first inclined portion L1 _S of the adjacent first trace L1 is not limited to an acute angle with a small angle, and the angle θ may be Selectively designed to be any angle greater than or equal to 45 and less than or equal to 90 degrees, the probability that the two traces generate electrostatic discharge due to the gradual reduction of the spacing when forming the double-layer trace can be avoided, thereby effectively reducing the first trace L1 or the second trace L2 has a probability of electrostatic damage.

In addition, it should be particularly noted that in the present embodiment, the pitch P between the first inclined portions L1 _{S of the} first trace L1 is substantially equal. In other words, the loss of light transmittance caused by the first trace L1 and the second trace L2 at any position along the row direction D2 is maintained constant, for example, the first trace L1 and the second trace L2 are in the figure. The loss of light transmittance caused at any position in the middle region B is maintained constant. In this way, in the subsequent seal process, when the sealant is applied to the first trace L1 and the second trace L2 along the row direction D2, since the first trace L1 and the second trace L2 are The loss of light transmittance caused at any position along the row direction D2 is maintained constant, and thus is applied to the region B by ultraviolet light from the outer surface of the substrate 110 (i.e., the surface containing no pixel structure 120). When the sealant is applied, the degree of hardening of the sealant in the region B can be substantially the same, so that the light penetration of the conventional first trace L1 and the second trace L2 at any position along the row direction D2 can be improved. The problem of inconsistent rate of frame rubber hardening (or incomplete hardening). As a result, the adhesion strength between the upper and lower substrates of the display panel having the pixel array substrate 100 of the present embodiment can be effectively improved, and the problem of contamination of the display medium and the frame glue is less likely to occur in subsequent processes.

In addition, referring to FIG. 1A , the pixel array substrate 100 of the embodiment may further include a plurality of sets of driving die pad sets 130 . The first trace L1 and the second trace L2 of each set of double-layer traces L extend from the display area R1 to the front edge area R2 _A , and each of the drive wafer pad sets 130 is located in the terminal area R2 _B , and each drive wafer is connected. The driving chip pads 132 of the pad group 130 are electrically connected to the first wire L1 and the second wire L2 of the corresponding one of the two-layer wires L to transmit the driving signals.

In detail, the first trace L1 and the second trace L2 of each set of double-layer traces L respectively include a first overlap extension L1 _E extending from the first inclined portion L1 _S and a second slope portion L2 _S An extended second overlapping extension L2 _E , wherein the first overlapping extension L1 _E coincides with the second overlapping extension L2 _E , thereby moving the overlapping area of the first routing L1 and the second routing L2 to the adjacent side The drive wafer pad set 132 extends. Further, the first trace L1 and the second trace L2 of each set of double-layer traces L have a first signal receiving portion L1 _I and a second signal receiving portion L2 _I , respectively, for connection with the driving wafer pad group 132. In detail, one end of the first overlap extending portion L1 _E and one end of the second overlap extending portion L2 _E are respectively connected to the first inclined portion L1 _S and the second inclined portion L2 _S , and each of the first traces L1 and each The two traces L1 are separated from the other end of the first overlap extending portion L1 _{E and} the other end of the second overlap extending portion L2 _E into a first signal receiving portion L1 ₁ and a second signal receiving portion L2 _{I , respectively} . The first trace L1 and the second trace L2 of each of the two-layer traces L are electrically connected to the respective driver die pad sets 130 by the first signal receiving portion L1 ₁ and the second signal receiving portion L2 _I, respectively. In this manner, the driving chip 140 electrically connected to each of the driving die pad sets 130 can drive the pixel structure 120 through the first routing line L1 and the second routing line L2, thereby enabling the pixel array of the embodiment. The display panel of the substrate 100 can display a variety of different screens.

3 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 1A and FIG. 3 simultaneously, the display panel 1000 of the present embodiment includes the above pixel array substrate 100, the opposite substrate 200 with respect to the pixel array substrate 100, and the pixel array substrate 100 and the opposite substrate 200. Display medium 300 between. In the present embodiment, the opposite substrate 200 is, for example, a color filter, and the display medium 300 is, for example, a liquid crystal, but the invention is not limited thereto.

In addition, the display panel 1000 of the present embodiment further includes a sealant 400 disposed between the pixel array substrate 100 and the opposite substrate 200 and surrounding the display medium 300, and simultaneously located in the peripheral circuit region R2 and covering the first trace L1. The first inclined portion L1 _S and the second inclined portion L2 _{S of the} second trace L2. In the present embodiment, the sealant 400 is, for example, a light-curing type sealant or a composite type sealant (that is, a sealant that can be hardened by light and heat).

Similarly, in the display panel 1000 of the present embodiment, since the light transmittance loss caused by the first trace L1 and the second trace L2 at any position along the row direction D2 is maintained constant, when When the ultraviolet ray is irradiated from the outer surface 110a of the substrate 110 (ie, the surface containing the pixel structure 120) to the sealant 400 applied to the region B, the degree of hardening of the sealant in the region B can be substantially the same, so The problem that the degree of hardening of the sealant is not uniform (or incompletely hardened) due to the inconsistent light transmittance of the conventional first trace L1 and the second trace L2 at any position along the row direction D2 is improved. As a result, the adhesion strength between the pixel array substrate 100 and the opposite substrate 200 of the display panel 1000 of the present embodiment can be effectively improved, and the problem of contamination of the display medium 300 and the sealant 400 is less likely to occur in subsequent processes.

In addition, in the display panel 1000 of the present embodiment, the angle θ between the second signal output portion L2 _{O of} each second trace L2 and the first inclined portion L1 _S of the adjacent first trace L1 is selectively Designed to be any angle greater than or equal to 45 degrees and less than or equal to 90 degrees, the probability that the two traces L1, L2 generate electrostatic discharge due to the gradual reduction of the spacing when forming the double-layer trace can be avoided, thereby effectively reducing the first trace L1 or the second trace L2 has a probability of electrostatic damage.

In summary, in the pixel array substrate and the display panel of the present invention, since the projection of one of the first traces and the adjacent second trace on the substrate is performed by the inclined portions having the same slope The intersections overlap and overlap. Therefore, the angle between the second signal output portion of each second trace and the inclined portion of the adjacent first trace can be designed to be a large angle, so as to avoid the two traces in forming the double-layer trace The probability of electrostatic discharge is gradually reduced by gradually reducing the pitch, whereby the probability of electrostatic damage to the first trace or the second trace can be effectively reduced.

In addition, in the pixel array substrate and the display panel of the present invention, since the pitch between the first inclined portions of the first trace is substantially equal, that is, the first trace and the second trace are arbitrarily along the row direction. The loss of light transmittance caused by the position is maintained constant. In this way, when the outer surface of the pixel array is to be irradiated with the sealant applied to the first trace and the second trace along the row direction, the first trace and the second trace are along the row. The problem of inconsistent degree of hardening of the sealant (or incomplete hardening) caused by inconsistent light transmittance at any position in the direction can be improved. As a result, the display panel of the pixel array substrate of the embodiment can improve the adhesion strength between the pixel array substrate and the opposite substrate, and the display medium and the frame glue are less likely to be contaminated in subsequent processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

1000‧‧‧ display panel

100‧‧‧ pixel array substrate

100a‧‧‧ pixel surface of the array substrate

110‧‧‧Substrate

120‧‧‧ pixel structure

130‧‧‧Drive wafer pad set

132‧‧‧Drive wafer pads

140‧‧‧Drive chip

200‧‧‧ opposite substrate

300‧‧‧Display media

400‧‧‧Box glue

L, L1, L2‧‧‧ trace

Ls, L1 _S , L2 _S ‧‧‧ inclined section

L1 _SA , L2 _SA ‧‧‧ the leading end of the inclined section

L1 _SB , L2 _SB ‧‧‧End of the inclined section

L1 _O , L2 _O ‧‧‧ signal output

L1 _E , L2 _E ‧‧‧Overlap extension

L1 _I , L2 _I ‧‧‧Signal Receiving Department

R1‧‧‧ display area

Side of S1, S2‧‧‧ display area

R2‧‧‧ peripheral circuit area

R2 _A ‧‧‧ frontal area

R2 _B ‧‧‧Terminal area

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

PE‧‧‧ pixel electrode

T‧‧‧ active components

D1, D2‧‧‧ direction

Θ‧‧‧ angle

P‧‧‧ spacing

B‧‧‧Area

SL‧‧‧ data line

DL‧‧‧ scan line

1A and FIG. 1B are schematic diagrams showing a top view of a pixel array substrate according to an embodiment of the invention.

Fig. 2A is an enlarged view of a partial area of Fig. 1A.

Fig. 2B is a schematic cross-sectional view of the inclined portion taken along the line AA' of Fig. 2A.

3 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.

100‧‧‧ pixel array substrate

110‧‧‧Substrate

120‧‧‧ pixel structure

130‧‧‧Drive wafer pad set

132‧‧‧Drive wafer pads

140‧‧‧Drive chip

L, L1, L2‧‧‧ trace

L1 _S , L2 _S ‧‧‧ inclined section

L1 _SA ‧‧‧The first end of the inclined section

L1 _SB , L2 _SB ‧‧‧End of the inclined section

L1 _O , L2 _O ‧‧‧ signal output

L1 _E , L2 _E ‧‧‧Overlap extension

L1 _I , L2 _I ‧‧‧Signal Receiving Department

R1‧‧‧ display area

R2‧‧‧ peripheral circuit area

R2 _A ‧‧‧ frontal area

R2 _B ‧‧‧Terminal area

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

PE‧‧‧ pixel electrode

T‧‧‧ active components

D1, D2‧‧‧ direction

P‧‧‧ spacing

B‧‧‧Area

Side of S1, S2‧‧‧ display area

DL‧‧‧ data line

SL‧‧‧ scan line

Claims (9)

A pixel array substrate comprising: a substrate comprising a display area and a peripheral circuit area, the peripheral circuit area being located outside the display area, the substrate having a first edge and a second edge connected perpendicularly and connected The peripheral circuit area has an adjacent marginal area and a terminal area, the terminal area is located between the display area and the first edge, the fore edge area is located between the display area and the second edge; a pixel structure, the array is arranged in the display area; the plurality of first traces and the plurality of second traces are located in the peripheral circuit area, and the first traces and the second traces respectively correspond to the corresponding pixels Electrically connecting, the second traces are located above the first traces and electrically insulated from the first traces, and the first traces and the second traces are respectively separated from the display area The column direction extends and is alternately arranged in a row direction perpendicular to the column direction, and the projection of each of the first trace and the adjacent one of the second traces on the substrate is inclined by the same slope Intersect and overlap each other to form a set of double-layered lines, of which The inclined portion is inclined with respect to the row direction and the column direction and located in the front edge region; and a plurality of sets of driving wafer pad groups are disposed in the terminal region, and each of the driving wafer pad groups and the corresponding group of double-layer wires The first trace and the second trace are electrically connected, and an orthographic projection of the inclined portion on the first edge is separated from an orthographic projection of the driving wafer pad set on the first edge, the inclined portion An orthographic projection on the second edge is separated from an orthographic projection of the plurality of driving wafer pads on the second edge, wherein the inclined portion includes a first inclined portion and a second inclined portion, each of the first walking The length of the first inclined portion of the line is greater than the length of the second inclined portion of each of the second traces, and each of the second traces is separated from the adjacent portion of the first trace by the second inclined portion thereof The first inclined portion overlaps, wherein in each of the set of double-layered wires, the first inclined portion has a first leading end and a first end, and the second inclined portion has a second leading end and a second An end, the first end coincides with the second end, and the second inclined portion is from the first The first end overlaps with the first inclined portion, and each of the first traces and each of the second traces respectively have a first signal output portion and a second signal output portion extending from the display region in the column direction. The first signal output portion and the second signal output portions are parallel to each other and alternately arranged in the row direction. In each of the two sets of two-layer traces, the second trace is fed by the second signal output portion. The second head end of the second inclined portion, the second signal output portion of each of the second traces has an angle θ with the first inclined portion of the adjacent first trace, 45 ⁰ <θ< 90 ⁰ . The pixel array substrate of claim 1, wherein the spacing between the inclined portions of the first traces is substantially equal. The pixel array substrate of claim 1, wherein each of the pixel structures comprises: an active component comprising a source, a gate and a drain; and a pixel electrode, and the active component Electrical connection. The pixel array substrate of claim 3, wherein the first traces and the second traces are electrically connected to the gates of the active components. The pixel array substrate of claim 3, wherein the first traces and the second traces respectively correspond to the active components The source is electrically connected. The pixel array substrate of claim 1, wherein each of the two-layered traces further comprises an overlapping extension extending from the inclined portion, and each of the first traces and each of the second traces respectively Having a first signal receiving portion and a second signal receiving portion, one end of the overlapping extending portion is connected to the inclined portion, and each of the first routing lines and each of the second routing lines are separated from the other end of the overlapping extending portion The first signal receiving unit and the second signal receiving unit. A display panel comprising: a pixel array substrate comprising: a substrate comprising a display area and a peripheral circuit area, the peripheral circuit area being located outside the display area, the substrate having a first edge that is perpendicular and connected And a second edge, the peripheral circuit area has an adjacent marginal area and a terminal area, the terminal area is located between the display area and the first edge, the fore edge area is located in the display area and the second Between the edges; a plurality of pixel structures arranged in the display area; a plurality of first traces and a plurality of second traces located in the peripheral circuit area, the first traces and the second traces Each of the second traces is electrically connected to the first traces and electrically insulated from the first traces, and the first traces and the second traces are electrically connected to the corresponding traces. Extending from the display area in the column direction, and alternately arranged in a row direction perpendicular to the column direction, the projection of each of the first traces and the adjacent ones of the second traces on the substrate Intersect and overlap each other by inclined portions with the same slope a set of double-layered wires, wherein the inclined portion is inclined with respect to the row direction and the column direction and located in the frontal edge region; and a plurality of sets of driving die pad groups disposed in the terminal region, each of the driving wafer pad sets Electrically connecting the first trace and the second trace of the corresponding set of double-layer traces, the orthographic projection of the inclined portion on the first edge and the driving wafer pad set at the first edge The front projection is separated, the orthographic projection of the inclined portion on the second edge is separated from the orthographic projection of the driving wafer pad group on the second edge, wherein the inclined portion includes a first inclined portion and a first portion a second inclined portion, a length of the first inclined portion of each of the first traces is greater than a length of the second inclined portion of each of the second traces, and each of the second traces is separated by a second inclined portion thereof The first inclined portion overlaps the portion of the first trace adjacent to the first trace, wherein the first inclined portion has a first leading end and a first end, and the second inclined portion has a second end end and a second end, the first end coincides with the second end, The second inclined portion overlaps the first inclined portion from the second leading end, and each of the first traces and each of the second traces further has a first signal output portion and a second signal output portion. The first signal output portion and the second signal output portions are parallel to each other and alternately arranged in the row direction. In each of the two sets of two-layer traces, the second trace is borrowed. The second signal output unit merges with the second first end of the second inclined portion, and the second signal output portion of each of the second traces and the first inclined portion of the adjacent first trace An angle θ, 45 ⁰ < θ < 90 ⁰ ; a pair of substrates, relative to the pixel array substrate; and a display medium between the pixel array substrate and the opposite substrate. The display panel of claim 7, further comprising a sealant between the pixel array substrate and the opposite substrate and surrounding the display medium, wherein the sealant is located in the peripheral circuit area and covers the cover Some inclined parts. The display panel of claim 8, wherein the sealant comprises a light hardening type frame glue or a composite type frame glue.