TWI284946B - Power chip scale package - Google Patents

Power chip scale package Download PDF

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Publication number
TWI284946B
TWI284946B TW091109996A TW91109996A TWI284946B TW I284946 B TWI284946 B TW I284946B TW 091109996 A TW091109996 A TW 091109996A TW 91109996 A TW91109996 A TW 91109996A TW I284946 B TWI284946 B TW I284946B
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pad
source
gate
package
leadframe
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TW091109996A
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Maria Cristina B Estacio
Ruben Madrid
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Fairchild Semiconductor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

1284946 A7 ----------B7_____ 五、發明説明（T^ —- 發明的背景 1·發明領域 本發明是關於用於半導體元件的封裝，更特別的是， 關於再提供優異的熱效 〃能以及非常低的封裝電阻之晶片等級封裝體中之金屬 氧化物半導體場效電晶體（MOSFET)元件的封裝，以及其 製造方法。 2.先前技藝的說明 半導體元件，特別是金屬氧化物半導體場效電晶體元 件’通常需要非常低的 封裝電阻（RDSon)以及良好的熱效能。對於該晶片， 匕通#也需要有盡可能小的封裝。因此，許多封裝概念與 方法在先前的技藝中已經被發展。 發明的摘要 本發明提供一種半導體元件，其包含具有一源極墊 (source pad)、至少兩個在該源極墊周邊的源極導線軌道、 相鄰於.該源極墊的閘極墊與在該閘極墊周邊的閘極導線軌 道的導線框。一加強肋被耦合在該導線框，並且與其電氣 絕緣。 依據本發明的一個概念，該加強肋包含一銅嵌條。 依據本發明的另一個概念，利用提供電氣絕緣的聚醯 胺膠帶，將該加強肋耦合在該導線框。 依據本發明的再一個概念，該導線框至少包含三個源 極導線框。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 4 (請先閲讀背面之注意事項再 ---- 再本頁： 訂· .1284946 五、發明説明（2 A7 因此，本發明提供一用於具有非常低的封裝電阻 (RDSon)以及優異的熱效能之晶片等級封裝體。該封裝體 可能無法完全符合該晶片等級大小定義，因為它的封裝大 小是它的晶片大小的丨.65倍，但這是用於金屬氧化物半導 體場效電晶體電力裝置之最有效的比例之一。 本發明的其他特徵與優點，在閱讀並瞭解下面之較佳 實施例的詳細說明，以及伴隨的參考圖式之後，將可立即 了解’其中類似的數字代表類似的元件。 圖式之概要說明 第1圖是依據本發明用於金屬氧化物半導體場效電晶 體裝置之封裝配置的底部透視圖； 第2圖是在第1圖中說明的其上貼附一晶片之封裝配置 的底部透視圖； 第3圖是說明於第丨圖中之封裝配置的部份分解圖式； 第4圖是說明於第丨圖中之封裝配置的頂部透視圖； 第5圖是一凸塊晶片之側截面圖式。 較佳示，範實施例之說明 第4圖說明用於半導體元件的封裝體ι〇。該封裝體包含 一具有源極導線12與閘極導線13的導線框丨丨。該封裝體較 好包含和邊些導線電氣絕緣的加強肋14。黏著劑或膠帶^ 5 被用於電氣絕緣該加強肋。在一較佳的實施例中，該膠帶 包含一聚醯胺膠帶。 於第1圖與及第3圖中可見，該導線框包含一源極墊2〇 和一閘極塾21。該源極墊2〇至少包含三個在該源極墊2〇周 本紙辦（CNS) M規格（2獻29
....................攀… (請先閲讀背面之注意事項再填寫本頁) 、一-T— :線- 1284946 五、發明説明（3 邊而被轉β其上的源極導線執道i 2a、b、。。可能有四個源 極^線，但較好是僅有三㈣，以切排流接點較輕易地按 規疋路線至泫主機板。該閘極墊較好緊鄰該源極墊，並且 較好是藉由一間隙22而與其電氣絕緣。 該加強肋有助於將該閘極導線保留在一穩固的位置。 該加強肋較好包含一銅嵌條。 使用黏著劑或膠帶（不導電膠帶）層15將該加強肋耦合 =該導線框，以使該絕緣肋與該導線框電氣絕緣。如上面 長:及的在車乂佳貫施例中，層1 5包含一聚醯亞胺膠帶。 當該加強肋是如說明的，實質上與該源極塾和該問極塾組 合^相同的尺寸時，那些熟悉該技藝者將會瞭解該加強肋 可能有各種不同的形狀與大小，只要它的形狀與大小符合 作為一支撐該閘極墊的加強肋，而且該閘極導線是在該導 線框之正下方側，因為它需要使該閘極導線與該相鄰的源 極導線維持一直線。 如第1圖所見，晶片3〇是一貼附在該源極與閘極墊上之 覆晶晶，片。該覆晶晶片貼附較好是以焊料凸塊進行，因此 該晶片是該技藝中所謂之凸塊晶片（bumped㈣）。凸塊 片通常是一件式的。如第5圖所見，-凸塊晶片包含該 片、焊料凸塊40、作為在該晶片之頂端表面之間的中間層 之“下凸塊”材料41。該下凸塊材料是嫣化鈦、銅、金或相 等物。在第5圖說明的實施例中，該下凸塊材料被分成三層 -銅電鍍41a、濺鍍銅41b與濺鍍鈦4ie。 該晶片被放置在該源極與閘極墊上，使得該晶片的暴 本紙張尺度適财_家標準（_ A4^^I()x297 6 - (請先閲讀背面之注意事項再
曰a BB
1284946 五、發明説明（4 路表面51與該源極與閘極導線共平面。所以，當該半導體 2件被放置在-印刷電路板(pcB)時，該晶片之該暴露的 共平面的表面是作為直接排流連接，而且該源極導線是作 為源極連接，同時該閘極導線是作為閘極連接。 α亥V線框較好包含一銅框。如第2圖所見，該些導線較 好疋預先成形並且穿孔，以利於該些導線的成形。 —該半導體元件的製造與封裝可以由各種不同的方法進 仃。通常，一晶片被提供（通常是鋸開晶圓）而且覆晶晶片 將η亥曰曰片貼附在該導線框上。如上面提及的，該晶片較好 ft塊晶片。如果不是，對於該晶片則需要提供焊料。覆 日日日日片貼附淨王序包含該晶片與該導線框之間焊料的流回， 然後進行每一個元件的切斷（Singulation)，較好是使用雷 射。後進行该半導體元件的電氣測試。該試驗完成之後 P將4半^體元件放置在膠帶上，並且與其他半導體元 件捲繞在一起以供應給消費者。 依據其他的製造程序，一旦該框收到導線之後或覆晶 曰曰片貼，附之後，使該閘極導線與該基材銅線條隔離。這將 可製造條狀物以供測試。 依據其他的製造程序，封裝物的應用可提升剛性，並 且促進该覆晶晶片貼附與雷射切口之間的固化。該半導體 元件可以自動地被測試，並且被放置在該膠帶上以及捲 % ’或者’閘極隔離與條狀物測試可以在雷射切割之前被 進行，然後該半導體元件被放置在膠帶上並捲繞。 因此’本發明提供一種在具有優異熱效能之晶片等級 本紙張尺度適用巾g[國家標準（哪）規格（2獻297公爱） (請先閱讀背面之注意事項再填窝本頁) 訂· :線丨 1284946
的 ί裝體中帛於半導體％件，特別是金屬氧化物半導體場 效電晶體元件’而且符合非常低的封裝電阻(RDs〇n)的封 裝體。依據本發明的封裝概念，符合封裝體大小是它的晶 片大t之1·8倍的晶片等較義。該導線框被設計成該凸塊 晶片是覆晶晶片，藉此該晶片的背面(排流)與該延伸預成 形的源極與閘極塾共平面。因此，在基板安裝期間該晶片 的背侧被直接焊接在該印刷t路板上以㈣排流連接，而 且該源極與閘極導線同時在它們的每-個指定位置處與其 焊接。該最後的封裝結構中可使用該加強肋，而在該導線 框與該加強肋之間利用不導電的膠帶，額外支撐該源極與 閘極導線，以使該閘極與源極導線的連接電氣絕緣。 雖然本發明已經參考特定的示範實施例而被說明，應 忒領會的是再附錄的申請專利範圍的領域中將包含所有 修正與相等物。 (請先閲讀背面之注意事项再 — 丹本頁. 二-T— 本紙張尺度適用中國國家標準（CNS) A4規格（21〇χ297&^) 1284946 A7 , B7五、發明説明（6 ) 元件標號對照 10…封裝體 22…間隙 : 11...導線框 30…晶片 • 12···源極導線 40…焊料凸塊 12 a、b、c…源極導線執道 41…下凸塊材料 41a...銅電鍍 41 b.. J賤錢銅 41c...濺鍍鈦 51...晶片暴露表面 13.. .閘極導線 14.. .加強肋 15.. .接著劑或膠帶 20.. .源極墊 21.. .閘極墊 (請先閲讀背面之注意事項再填寫本頁) «· 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 9

Claims (1)

1284946
六、申請專利範圍 第91109996號專利再審查案申請專利範圍修正本 修正日期：95年12月 1· 一種半導體元件封襞體，包含： a· —導線框，其含有： i.源極墊； 11·在該源極墊的周邊至少兩個源極導線； iii·相鄰於該源極墊並且與其電氣絕緣之閘極墊；和 IV.在該閘極墊的周邊之閘極導線； b.—搞合在該源極墊和該閘極墊的晶片；和 c· 一耦合在該導線框並與其電氣絕緣的加強肋。 2·如申請專利範圍第1項的半導體元件封裝體，其中該加 強肋包含一銅嵌條。 3·如申請專利範圍第1項的半導體元件封裝體，其中該加 強肋是以提供電氣絕緣之聚醯亞胺膠帶耦合在該導線 框。 4·如申請專利範圍第2項的半導體元件封裝體，其中該加 強肋包含一銅嵌條。 5·如申請專利範圍第4項的半導體元件封裝體，包含至少 三個源極導線。 6· 一種製造半導體元件封裝體的方法，該方法包含： 提供一導線框，其含有： a·源極塾； b·在該源極墊的周邊至少兩個源極導線； 1 1284946 f%i >月％日修(更)正替換頁 、申請專利範圍 c·相鄰於該源極墊並且與其電氣絕緣之閘極墊；和 d·在該閘極墊的周邊之閘極導線； 翻覆一包含多數焊料凸塊之凸塊晶片於該等源極 與閘極塾上； 迴焊該焊料凸塊；且 將一加強肋連接至該導線框，其中該加強肋係和該 導線框電氣絕緣。 •如申睛專利範圍第6項的方法，進一步包含： 進行雷射切割； 測試該半導體元件封裝體；和 將該半導體封裝體放置在捲軸上的膠帶上。 8·如申請專利範圍第6項的方法，其中該測試包含在進行 雷射切割之前隔離該閘極墊與試驗條狀物。 9·如申請專利範圍第6項的方法，進一步包含在流回該些 焊料凸塊之後，進行底層充填塗佈與固化。 如申明專利範圍第9項的方法，其中該測試包含在進行 雷射切割之前隔離該閘極墊與試驗條狀物。 11·一種半導體元件，包含： a·含有第一與第二表面的導線框； b·麵合在該第一表面的晶片；和 c·輕合在該第二表面並與其電氣絕緣的加強肋。 12.如申請專利範圍第11項的半導體元件，其中該加強肋是 以提供電氣絕緣之聚醯胺膠帶耦合在該導線框。 13·如申請專利範圍第11項的半導體元件，其中該加強肋包 2 1284946
日修(更)正替換頁 六、申請專利範圍 含一銅般條。 14. 一種製造半導體元件的方法，該方法包含： 提供包含一第一表面與一第二表面的導線框； 將一加強肋連接至該導線框，其中該加強肋係和該 導線框電氣絕緣， 以焊料將一晶片耦合在該第一表面；和 迴焊該焊料。
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