TWI284371B - Semiconductor processing method for selectively forming thin film in low pressure - Google Patents
Semiconductor processing method for selectively forming thin film in low pressure Download PDFInfo
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1284371 案號 92102066 修正1284371 Case No. 92102066 Amendment
五、發明說明（1) 發明所屬之技術領域 本發明係提供一種半導體製程方法，尤指—種 於記憶體中多晶矽（含金屬矽化物如wsix)蝕刻後回^ ―用 的製程，具有選擇性氧化之功效。 久氣化 先前技術 在半導體製程中，由於二氧化矽具有適當的介# 數並與碎表面具有良好的結合能力，因此其應用十2令 泛’ 一般用來作為閘極乳化膜（g a t e ο X i d e )、區技1^廣 巧隔離 氧化層（local oxidation of silicon，LOCOS)或場: 層（field oxide)、層間介電層（interlayer 努氣化 dielectric)以及墊氧化層（pad oxide)等等。目前較常 用來於半導體晶片表面上形成二氧化矽薄膜的方法主^ 有三種：（1 )化學氣相沈積法，（2 )熱氧化法，以及（3 )旋 轉塗佈法。其中又以熱氧化法所生成之二氧化矽薄膜的 電性以及物性最佳。習知的熱氧化法依反應爐以及昇溫 模式的不同可區分為快速熱氧化法（rapid thermal oxidation，RT0)以及爐管氧化法（furnace oxidation)。相較於爐管氧化法，由於快速熱氧化法的 昇溫速率快、反應時間短、加熱均勻、製程潔淨以及熱 預算小，因此已經漸漸取代爐管氧化法而成為目前形成 二，化矽薄膜的主流。若依反應氣體的種類而言，快速 熱氧化法又可被細分為乾式氧化（dry oxidation)以及濕V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention provides a semiconductor process method, in particular, a process for etching polycrystalline germanium (containing metal halides such as wsix) in a memory, which is selective. The effect of oxidation. The gasification of the prior art in the semiconductor process, because the cerium oxide has the appropriate number of the number and has a good ability to combine with the broken surface, so its application of the ubiquitous 'usually used as a gate emulsifying film (gate ο X Ide ), area technology 1 ^ local oxidation of silicon (LOCOS) or field: field oxide, interlayer dielectric layer (interlayer gasification dielectric) and pad oxide (pad oxide), etc. . At present, there are three main methods for forming a hafnium oxide film on the surface of a semiconductor wafer: (1) chemical vapor deposition, (2) thermal oxidation, and (3) spin coating. Among them, the cerium oxide film formed by the thermal oxidation method is optimal in electrical properties and physical properties. Conventional thermal oxidation methods can be distinguished by rapid thermal oxidation (RT0) and furnace oxidation depending on the reaction furnace and the temperature rise mode. Compared with the furnace tube oxidation method, due to the rapid heating rate of the rapid thermal oxidation method, short reaction time, uniform heating, clean process and small thermal budget, it has gradually replaced the furnace tube oxidation method and has become the second formation of bismuth film. Mainstream. According to the type of reaction gas, rapid thermal oxidation can be subdivided into dry oxidation and wet
第7頁 1284371 , __案號 921Q2066_色 五、發明說明（2) 式氧化（wet oxidation)兩種 (1 )以及式（2 )所示： 月 修正 其主要的反應式分別如式 S i (S) + 〇 2(g) — S i 0 2(s) ( 1 )Page 7 1284773, __ Case No. 921Q2066_Color V, invention description (2) Wet oxidation two (1) and formula (2): monthly correction of the main reaction formula respectively as the formula S i (S) + 〇2(g) — S i 0 2(s) ( 1 )
Si (s) + 2H20(g) — Si02(s) + 2H2(g) (2) 其中，在式（2)中的水蒸氣（steam)—般係由高熱蒸 >'气產生器（pyrogen i c steam genera tor )戶斤產生。由於水 蒸氣在進行矽氧化的過程中具有較氧氣高的線性速率常 數（linear rate const ant)以及拋物線速率常數 (parabolic rate constant)，因Jt以濕、式氧4匕；^去進行氧 化會得到較大的氧化速率。 請參閱圖一至圖三，圖一至圖三為習知製作罩幕式 唯讀記憶體5 0的剖面示意圖。如圖一所示，罩幕式唯讀 記憶體50包含有一基底5卜其上被場氧化層55a區隔為一 周邊電路區（periphery circuit region)52以及一記憶 單元區（ROM cell region)54。於周邊電路區52中，罩幕 式唯讀記憶體50表面包含有至少一 pm〇S元件區域以及一 N Μ 0 S元件區域’由一場氧化層5 5 b所隔離。基底51的表面 上已預先利用離子佈植形成N型井5 3以及P型井5 7，並利 用化學氣相沈積法於基底5 1表面上沈積一氮化矽層5 8， 作為後續離子佈植的罩幕（mask)。接著利用一黃光及蝕 刻製程進行記憶單元區54中BDF離子佈植的定義。接著進 行離子佈植60，以於記憶單元區54中基底51表面上形成Si (s) + 2H20(g) — Si02(s) + 2H2(g) (2) wherein the steam in the formula (2) is generally composed of a high heat steaming > 'gas generator (pyrogen) Ic steam genera tor). Since water vapor has a higher linear rate const ant and a parabolic rate constant in the process of ruthenium oxidation, it is obtained by oxidation of Jt with wet oxygen. Larger oxidation rate. Referring to FIG. 1 to FIG. 3, FIG. 1 to FIG. 3 are schematic cross-sectional views of a conventional read-only memory 50. As shown in FIG. 1, the mask-type read-only memory 50 includes a substrate 5, which is partitioned by a field oxide layer 55a into a peripheral circuit region 52 and a ROM cell region 54. . In the peripheral circuit region 52, the surface of the mask-type read-only memory 50 includes at least one pm 〇 S element region and an N Μ 0 S device region ' is isolated by a field oxide layer 5 5 b. An N-type well 5 3 and a P-type well 5 7 have been previously formed on the surface of the substrate 51 by ion implantation, and a tantalum nitride layer 5 8 is deposited on the surface of the substrate 5 1 by chemical vapor deposition as a subsequent ion cloth. The mask of the plant. The definition of BDF ion implantation in memory cell region 54 is then performed using a yellow light and etching process. Ion implantation 60 is then performed to form on the surface of the substrate 51 in the memory cell region 54.
1284371 一_ 案號92102066 年月口 ----- ~~~-~~— 五、發明說明（3) 複數個BDF區域56。 如圖二所示，接著去除氮化石夕層58。 的清洗及乾燥程序後，於基底5 1表面上形 層6 2。形成閘極氧化層6 2的方法一般係以 行。接著於閘極氧化層6 2表面依序沈積一 一金屬石夕化層，共同構成一多晶石夕化金屬 用光阻層66於PMOS區域，NMOS區域，以及 定義出閘極72，74以及75的位置，並利用 進行閘極7 2，7 4以及7 5的形成。隨後去除 著，如圖三所示，繼續進行一回火氧化製 矽化金屬層6 4的多晶矽層側壁表面上形成 右之二氧化矽薄膜層76。 然而，習知的回火氧化製程會使金屬 形成缺陷，並且降低良率。因此，需要有 方法，可結合應用於上述記憶體製作過程 發生，並且提高製程良率與產品可靠度。 發明内容 因此’本發明之主要目的在於提供一 法，包含採用濕式快速熱氧化法，而^以 蒸汽產生器，進而避免影響到產品之如接 (junction depth)、電晶體元件的啟始電 修正 在經過一連串 成一閘極氧化 熱氧化法進 多晶秒層以及 層64。接著利 ROM ce11區域 一乾蝕刻製程 光阻層6 6。接 程，以於多晶 一厚度75埃左 石夕化物氧化， 一更好的氧化 中，減少缺陷 種記憶體的製 不必使用高熱 合深度 壓（threshold 1284371 --_92102066_年月日 __ 五、發明說明（4) voltage)、防止貫穿（anti-punch through)等的特性， 使產品製作具有較大的製程空間（process window)。 本發明之另一目的在於提供一種罩幕式唯讀記憶體 的製法，包含採用低壓（< 2 0Tor r )濕式快速熱氧化法， 以於一半導體晶片表面上或在罩幕式唯讀記憶體的多晶 矽側壁上形成一具有高品質網狀結構之二氧化石夕薄膜。 本發明之另一目的在於提供一種罩幕式唯讀記憶體 的製法，包含採用濕式快速熱氧化法，以於低壓下（< 2 0Torr)快速地於一多晶矽化金屬層的多晶矽層表面形成 一高品質二氧化矽薄膜，而不氧化該多晶矽化金屬層的 金屬矽化層。 本發明之另一目的在於提供一種罩幕式唯讀記憶體 的製法，包$採用低壓濕式快速熱氧化法，以反應氣體 總流量以及塵力控制二氧化矽薄膜的成長速率（growth rate)以及膜厚均一性（oxide thickness uniformity)。 本發明係，供一種於一半導體晶片表面選擇性形成 一高品質之二^化矽薄膜的方法。該半導體晶片表面被 定義有一記憶單元區以及一周邊電路區，而該周邊電路 區中包含有至少一多晶矽化金屬層，且該多晶矽化金屬 層係由一多晶矽層以及一金屬矽化層上下堆疊而成。該 方法係包含以濕式低壓氧化將該半導體晶片置於一壓力1284371 a _ case number 92102066 year month mouth ----- ~~~-~~- five, invention description (3) a plurality of BDF areas 56. As shown in Figure 2, the nitride layer 58 is subsequently removed. After the cleaning and drying process, a layer 62 is formed on the surface of the substrate 51. The method of forming the gate oxide layer 62 is generally carried out. Then, a metal ruthenium layer is sequentially deposited on the surface of the gate oxide layer 62 to form a polysilicon photo-resist layer 66 in the PMOS region, the NMOS region, and the gates 72, 74 are defined. The position of 75 is utilized to form the gates 7 2, 7 4 and 7 5 . Subsequently, as shown in Fig. 3, the ruthenium oxide thin film layer 76 is formed on the surface of the side wall of the polysilicon layer of the bismuth metal layer 64. However, conventional tempering oxidation processes can cause defects in the metal and reduce the yield. Therefore, there is a need for a method that can be applied in combination with the above-described memory fabrication process, and improves process yield and product reliability. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method comprising using a wet rapid thermal oxidation method and a steam generator to avoid affecting the junction depth of the product and the initiation of the transistor element. The correction is followed by a series of gated oxidative thermal oxidation processes into the polycrystalline seconds layer and layer 64. Then, the ROM ce11 region is internally etched to the photoresist layer 66. The process is to oxidize polycrystalline-thickness 75 angstroms, a better oxidation, and reduce the memory of defects. It is not necessary to use high heat sealing depth (threshold 1284371 --_92102066_月日日__五The invention (4) voltage), anti-punch through, etc., make the product have a large process window. Another object of the present invention is to provide a mask-type read-only memory method comprising using a low pressure (<20Torr) wet rapid thermal oxidation method for reading on a semiconductor wafer surface or in a mask type. A side wall of a polycrystalline silicon oxide having a high quality network structure is formed on the sidewall of the polycrystalline crucible of the memory. Another object of the present invention is to provide a mask-type read-only memory method comprising using a wet rapid thermal oxidation method to rapidly degranize a polycrystalline germanium layer on a polycrystalline metal layer at a low pressure (<20 Torr). A high quality ruthenium dioxide film is formed without oxidizing the metal ruthenium layer of the polycrystalline ruthenium metal layer. Another object of the present invention is to provide a mask-type read-only memory method, which uses a low-pressure wet rapid thermal oxidation method to control the growth rate of a cerium oxide film by the total flow rate of the reaction gas and the dust power. And oxide thickness uniformity. SUMMARY OF THE INVENTION The present invention is directed to a method of selectively forming a high quality bismuth film on a semiconductor wafer surface. The semiconductor wafer surface is defined with a memory cell region and a peripheral circuit region, and the peripheral circuit region includes at least one polycrystalline germanium metal layer, and the polycrystalline germanium metal layer is stacked on top of each other by a polysilicon layer and a metal germanium layer. to make. The method comprises placing the semiconductor wafer at a pressure by wet low pressure oxidation
第10頁 1284371 修正 曰 五、發明說明（5) 小於20 Torr的壓* 0入士 #、s λ 卜产 體。盆中曰K、w /鈿中，亚通入一氬氣/氧氣混合氣 tF)i 8〇〇~115〇°C，氫氣流量比率 UH2 of 16SLM，g卩άτ、，乳以及氧氣之總氣體流量（TGF)為8〜 卢約為30 °qnt 5〜45秒鐘内於該多晶矽層表面上形成一厚 度為30〜90埃之二氧化矽層’而不氧化該金屬矽化層。 隊，ΐΐίϊ明之上述目的、特徵、和優點能更明顯易 憧下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下。 ' 實施方式 本毛明係關於一種半導體製程方法，可選擇性地快 速在多晶石夕上長出薄膜，其重要特色是反應時間短、採 快速升降溫（RTP)製程，對於薄的氧化層厚度，可藉由改 變Η #來達到’因此可應用於許多半導體產品製程上，例 如罩幕式唯讀記憶體（mask ROM)、可電抹除且可程式唯 讀記憶體（electrically erasable programmable read only memory，EEPROM)、或動態隨機存取記憶體（dram) 等等，而不會影響到產品之如接合深度（j u n c t i ο η depth)、電晶體元件的啟始電壓（threshold voltage)、 防止貫穿（anti-punch through)等的特性，使產品製作 具有較大的製程空間（Process window)。 現以罩幕式唯讀記憶體5 0為例做說明。請參閱圖四Page 10 1284371 Correction 曰 V. Inventive Note (5) Pressure less than 20 Torr* 0 士士士#, s λ 卜 产. In the basin K, w / 钿, Yatong into an argon / oxygen mixture tF) i 8 〇〇 ~ 115 〇 ° C, hydrogen flow ratio UH2 of 16SLM, g 卩ά τ,, milk and oxygen total gas The flow rate (TGF) is 8 to about 30 ° qnt to form a ceria layer having a thickness of 30 to 90 angstroms on the surface of the polycrystalline germanium layer for 5 to 45 seconds without oxidizing the metal deuterated layer. The above objects, features, and advantages of the team are more apparent and will be described in detail below with reference to the accompanying drawings. The present invention relates to a semiconductor process method for selectively and rapidly growing a film on a polycrystalline stone. The important feature is a short reaction time, rapid rise and fall temperature (RTP) process, and a thin oxide layer. Thickness can be achieved by changing Η # so it can be applied to many semiconductor product processes, such as mask ROM, erasable programmable read read memory (electrically erasable programmable read memory) Only memory, EEPROM), or dynamic random access memory (dram), etc., without affecting the product such as junction depth (juncti ο η depth), threshold voltage of the transistor element, preventing penetration Characteristics such as (anti-punch through) make the product have a large process window. Now, the mask-type read-only memory 50 is taken as an example for illustration. Please refer to Figure 4
1284371 ____案號92102066__年月 修正__ 五、發明說明（6) 至圖六，圖四至圖六為本發明較佳實施例的剖面示意 圖’其中與圖一至圖三中相同之元件在此仍以相同之標 號表示。如圖四所示，罩幕式唯讀記憶體5 〇包含有一基 底5 1 ’其上被場氧化層5 5 a區隔為一周邊電路區1284371 ____ Doc. No. 92102066 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Still indicated by the same reference numerals. As shown in FIG. 4, the mask-type read-only memory 5 〇 includes a substrate 5 1 ' on which a field oxide layer 5 5 a is partitioned into a peripheral circuit region.
(periphery circuit region)52以及一記憶單元區（ROM 〇611^81〇1〇54。而於周邊電路區5 2中，罩幕式唯讀記 憶體50表面包含有至少一 PM0S元件區域以及一 NM〇s元件 區域’由一場氧化層55b所隔離。基底51的表面上已預先 利用離子佈植形成N型井5 3以及P型井5 7，並利用化學氣 相沈積法於基底5 1表面上沈積一氮化石夕層5 8，作為後續 離子佈植的罩幕（mask)。接著利用一黃光及蝕刻製程進 行記憶單元區54中BDF離子佈植的定義。接著進行離子佈 植60，以於記憶單元區54中基底51表面上形成複數個bDF 區域56。隨著元件的微小化，bDF區域5 6的接合深度也隨 著縮小。因此完成BDF區域56之後，應盡量避免長時間的 高溫熱製程，以免影響到BDF區域5 6的接合界面輪磨。 如圖五所示，接著去除氮化矽層5 8。在經過一連串 的β洗及乾燥程序後，於基底5 1表面上形成一閘極氧化 層62。形成閘極氧化層62的方法係在一 RTp反應器中通入 總流量（TGF)為10 SLM的氫氣以及氧氣，其中氫氣流量比 率（別2 of TGF)為1〜33%。RTP反應器的壓力被控制在8〜 12Torr。基底51被加熱至8〇〇〜115〇它，並且維持在此溫 度約5〜7 0秒。在其他實施例中，閘極氧化層6 2亦可由一 般爐管氧化製程形成。接著於閘極氧化層6 2表面依序沈(periphery circuit region) 52 and a memory cell region (ROM 〇 611 ^ 81 〇 1 〇 54. In the peripheral circuit region 52, the surface of the mask-type read-only memory 50 includes at least one PMOS component region and an NM The 〇s element region 'is isolated by a field oxide layer 55b. The surface of the substrate 51 has been previously implanted with ions to form an N-type well 5 3 and a P-type well 57, and is chemically vapor deposited on the surface of the substrate 5 1 . A nitridium layer 5 8 is deposited as a mask for subsequent ion implantation. The definition of BDF ion implantation in the memory cell region 54 is then performed using a yellow light and etching process. A plurality of bDF regions 56 are formed on the surface of the substrate 51 in the memory cell region 54. As the components are miniaturized, the bonding depth of the bDF regions 56 is also reduced. Therefore, after completing the BDF region 56, long-term high should be avoided as much as possible. Warm the process so as not to affect the bonding interface wheel grinding of the BDF area 56. As shown in Fig. 5, the tantalum nitride layer 58 is subsequently removed. After a series of β washing and drying procedures, the surface of the substrate 5 1 is formed. a gate oxide layer 62. The method of gate oxide layer 62 is to pass a total flow (TGF) of 10 SLM of hydrogen and oxygen in an RTp reactor, wherein the hydrogen flow ratio (2 of TGF) is 1 to 33%. The pressure of the RTP reactor It is controlled at 8 to 12 Torr. The substrate 51 is heated to 8 Torr to 115 Torr and maintained at this temperature for about 5 to 70 seconds. In other embodiments, the gate oxide layer 62 can also be oxidized by a general furnace tube. The process is formed. Then, the surface of the gate oxide layer 6 2 is sequentially deposited.
第12頁 1284371 _ _921020fi^ 年 月 日__堡至_ 五、發明說明（7) 積一多晶石夕層以及一金屬矽化層，共同構成一多晶矽化 金屬層6 4。接著利用光阻層6 6於PMOS區域、NMOS區域及 ROM cel 1區域54定義出閘極72、74及75的位置，並利用 一乾蝕刻製程進行閘極72、74及75的形成。隨後去除光 阻層6 6。 本發明形成二氧化矽薄膜的方法係於單一晶片RTP反 應器中進行，鶴絲齒素加熱燈管（t u n g s t e n h a 1 〇 g e η lamp)，可以快速將半導體晶片昇溫至所要求之高溫。 接著，如圖六所示，繼續進行一次低壓濕式快速熱 氧化製程，以於多晶石夕化金屬層6 4的多晶矽層表面上回 火氧化形成一厚度7 5埃左右之高品質二氧化矽薄膜層 76。形成二氧化矽薄膜層76的方法係在RTP反應器中通入 總流量（TGF)為10 SLM的氫氣以及氧氣，其中氫氣流量比 率（％H2 of TGF )為1〜3 3 %。R T P反應器4 0的壓力被控制在§〜 12Torr。基底51被加熱至8 0 0〜1150°C，並且維持在此溫 度約5〜7 0秒。由於兩次低壓濕式快速熱氧化製程的反應 時間都很短，因此不會影響BDF區域5 6的接合界面輪廓' 此外，多晶矽化金屬層6 4中的金屬矽化層亦不會被氧 化’而能夠維持字元線（w 〇 r d 1 i n e )的電阻率。 在本發明之較佳實施例中，半導體晶片1 〇係為一 p 型晶格排列方向（100)、電阻值為15-25 ohm-cm的單面抛 光矽晶片。以在半導體晶片表面上氧化生成一厚度約Page 12 1284371 _ _921020fi^ Year Month Day __ Fort to _ V. Invention Description (7) A polycrystalline layer and a metal deuteration layer together form a polycrystalline metallization layer 64. Next, the positions of the gates 72, 74, and 75 are defined by the photoresist layer 66 in the PMOS region, the NMOS region, and the ROM cel 1 region 54, and the gates 72, 74, and 75 are formed by a dry etching process. The photoresist layer 66 is subsequently removed. The method for forming a ruthenium dioxide film of the present invention is carried out in a single wafer RTP reactor, and the lignin heating lamp tube (t u n g s t e n h a 1 〇 g e η lamp) can quickly raise the temperature of the semiconductor wafer to a desired high temperature. Next, as shown in FIG. 6, a low-pressure wet rapid thermal oxidation process is continued to temper and oxidize on the surface of the polycrystalline germanium layer of the polycrystalline lithiated metal layer 64 to form a high-quality dioxide having a thickness of about 75 angstroms.矽 film layer 76. The method of forming the ceria thin film layer 76 is to introduce hydrogen gas having a total flow rate (TGF) of 10 SLM and oxygen in the RTP reactor, wherein the hydrogen flow rate ratio (% H2 of TGF) is 1 to 33%. The pressure of the R T P reactor 40 is controlled at § ~ 12 Torr. The substrate 51 is heated to 800 to 1150 ° C and maintained at this temperature for about 5 to 70 seconds. Since the reaction time of the two low-pressure wet rapid thermal oxidation processes is short, the joint interface profile of the BDF region 56 is not affected. In addition, the metal germanide layer in the polycrystalline germanium metal layer 64 is not oxidized. The resistivity of the word line (w 〇rd 1 ine ) can be maintained. In a preferred embodiment of the invention, the semiconductor wafer 1 is a single-sided polished germanium wafer having a p-type lattice alignment direction (100) and a resistance value of 15-25 ohm-cm. Oxidizing on the surface of the semiconductor wafer to form a thickness
第13頁 1284371 -t月日 修正 五、發明說明（8) ~~Page 13 1284371 - month of the month Amendment 5, invention description (8) ~~
3 的一氧化石夕薄膜為例’先在載有半導體晶片的RTP 反心t中^通入總流量（tota 1 gas f 1 owrate，TGF)為1 0 SLM，負^氣以及氧氣，其中氫氣流量比率（％H2 〇f tgf)為1 3 3 %、較仏為2 %。R τ P反應器4 0的壓力應被控制在低於2 〇For example, the monocrystalline oxide film of 3 is first introduced into the total flow of the RTP anti-center t of the semiconductor wafer (tota 1 gas f 1 owrate, TGF) is 10 SLM, negative gas and oxygen, wherein hydrogen The flow ratio (%H2 〇f tgf) is 1 3 3 %, which is 2%. The pressure of the R τ P reactor 40 should be controlled below 2 〇
Torr以下，較佳則為8〜12Τ〇γγ，更佳為丨〇· 5τ〇π。在反 應的過f中，半導體晶片1 0被加熱至8 0 0〜1 1 5 〇t，較佳 為100 〇C，並且維持在此溫度約5〜70秒，較佳為45秒。 由於反應壓力被控制在2() T〇rr以下的低壓下，因此氧化 反應係在一質量傳輸控制狀態（mass transp〇rt controlled regime)下進行，而壓力的改變會直接影響 到氧化過矛王中②3：傳輸速率（mass transport rate)。 請參閱圖七，圖七為本發明低壓濕式快速熱氧化法 於半導體晶片表面上可能發生之反應式。如圖七所示， 在反應器中，氫氣以及氧氣會先反應生成氫氧自由基（式 (3))，氫氣與氫氧自由基會進一步反應生成水分子以及 ^原子（式（4 ))’氫原子與氧分子則會再進行反應形成氫 氧自由基以及氧原子（式（5))，氧原子與氳分子亦會反應 生成氫氧自由基以及氫原子（式（β))。因此，實際參與二 氧化石夕薄膜乳化反應的活性物種主要包括氫氧自由基、 氧原子以及氫原子。其中，氫氧自由基與氧原子參與氧 化的反應，而氫原子有還原的功能，可以抑制金^ ^夕化 物被氧化造成缺陷。 請參閱圖八’圖八為低壓濕式快速熱氧化法的反應Below Torr, it is preferably 8 to 12 Τ〇γγ, more preferably 丨〇·5τ〇π. In the reaction f, the semiconductor wafer 10 is heated to 800 to 1 15 〇t, preferably 100 〇C, and maintained at this temperature for about 5 to 70 seconds, preferably 45 seconds. Since the reaction pressure is controlled at a low pressure below 2() T〇rr, the oxidation reaction is carried out under a mass transp〇rt controlled regime, and the change in pressure directly affects the oxidized spear king. Medium 23: Mass transport rate. Referring to Fig. 7, Fig. 7 is a reaction equation which may occur on the surface of a semiconductor wafer by the low pressure wet rapid thermal oxidation method of the present invention. As shown in Figure 7, in the reactor, hydrogen and oxygen will first react to form hydroxyl radicals (formula (3)), and hydrogen and hydroxyl radicals will further react to form water molecules and ^ atoms (formula (4)). The hydrogen atom and the oxygen molecule react to form a hydroxyl radical and an oxygen atom (formula (5)), and the oxygen atom and the ruthenium molecule also react to form a hydroxyl radical and a hydrogen atom (formula (β)). Therefore, the active species actually involved in the oxidization reaction of the cerium oxide film mainly include a hydroxyl radical, an oxygen atom, and a hydrogen atom. Among them, the hydroxyl radical and the oxygen atom participate in the oxidation reaction, and the hydrogen atom has a function of reducing, which can suppress the defects caused by the oxidation of the gold compound. Please refer to Figure VIII. Figure 8 shows the reaction of low pressure wet rapid thermal oxidation.
第14頁 1284371 __案號1102066_年月日 修正 _ 五、發明說明（9) 機構示意圖。如圖八所示，影響低壓濕式快速熱氧化法 (主要是薄膜成長速率以及膜厚均一性）的因素可大致被 歸納為以下五個階段： (一） 氣相反應階段（react i on i n gas phase ):在此階段 主要是受到氣體溫度、反應物物種濃度以及RTP反應器中 的氣體流量所影響。 (二） 反應物物種擴散至薄膜表面階段（di f fusion of oxidizing species to oxide surface)：在此階段主要 是受到溫度、反應物物種濃度以及RTP反應器中的氣體流 量所影響。 (二）反應物物種溶入薄膜階段（dissolution in ox i de ):在此階段主要是受到溫度以及反應物物種濃度 所影響。 (四） 反應物物種擴散至半導體晶片表面階段（diffusi〇n of oxidizing speciesto silicon surface):在此階 段主要是受到溫度以及各反應物物種與矽結晶表面的反 應特性影響。 (五） 反應形成二氧化石夕薄膜階段（〇xidat i〇n t〇 f orin ox l de ):在此階段主要是受到溫度以及表面矽結晶排列 方向。 綜上歸納可知’本發明主要的控制因素除了溫度之 外’尚包括有反應物物種濃度以及RTp反應器中的氣體流 量。Page 14 1284371 __ Case No. 1102066_年月日日 Revision _ V. Description of invention (9) Schematic diagram of the organization. As shown in Figure 8, the factors affecting the low-pressure wet rapid thermal oxidation method (mainly film growth rate and film thickness uniformity) can be roughly classified into the following five stages: (1) Gas phase reaction stage (react i on in Gas phase): At this stage, it is mainly affected by the gas temperature, the concentration of the reactant species, and the gas flow rate in the RTP reactor. (ii) Di f fusion of oxidizing species to oxide surface: at this stage, it is mainly affected by temperature, concentration of reactant species, and gas flow in the RTP reactor. (2) Dissolution in ox i de: At this stage, it is mainly affected by temperature and concentration of reactant species. (iv) Diffusi〇n of oxidizing species to silicon surface: at this stage, it is mainly affected by temperature and the reaction characteristics of each reactant species and the crystalline surface of the ruthenium. (5) The reaction forms a thin film phase of cerium oxide (〇xidat i〇n t〇 f orin ox l de ): at this stage, it is mainly subjected to temperature and surface crystallization. In summary, it can be seen that the main control factors of the present invention include, in addition to temperature, the concentration of reactant species and the gas flow in the RTp reactor.
第15頁 1284371 五、發明說明 案號 (10) 92102066Page 15 1284371 V. Description of invention Case No. (10) 92102066
修正 i 清參閱圖九，圖九為本發明二卜 忍圖。如圖九所示 ,^ ^ . 虱化矽薄膜結構3 0示 氧自由基插=在反應過程中，氧原子以及氫 所形成之二氧化矽ί '14反應的關係，所以利用本發明 使其電性以及物& i專胰結構30具有高度網狀結構，進而 type?佳 物性都較習知之過氧化結構（P㈣xicie 相車父於習知技蔽，，么 ^ ^^ ^ 'Λ /(iCorrection i clear refers to Figure IX, and Figure 9 is a second diagram of the present invention. As shown in Fig. 9, the structure of the ruthenium telluride film 30 indicates oxygen radical insertion = the relationship between the oxygen atom and the ruthenium dioxide '14 reaction formed by hydrogen during the reaction, so the present invention is utilized. Electrical and physical & i-specific pancreatic structure 30 has a highly network structure, and then type? good physical properties are better than the conventional peroxidation structure (P (four) xicie phase father father knows the skill, ^ ^ ^ ^ ^ 'Λ / ( i
^ 反應器的氣體總流量（TGF)以及氧化反應時間，來 ^=所要的二氧化矽薄膜的成長及記憶體中金屬矽化物 的軋化抑制。而習知技術則是成長二氧化矽的同時，會 ，成記憶體中金屬矽化物的氧化產生缺陷。本發明於低 壓下，行濕式快速熱氧化法具有以下的特色··（丨）現場產 生水瘵氣（in-si tu steam growth)不需要額外的蒸汽產 生器，（2 )在低壓下進行高溫反應，（3 )氧化反應日^間 短，可避免對半導體元件特性造成改變，（4)較佳品質的 一氧化石夕薄膜（more networked-structured)，以及（5) 藉由壓力以及氣體總流量控制二氧化矽薄膜的成長速 率〇 以上所述僅為本發明之較佳實施例，凡依本發明申 請專利範圍所做之均等變化與修飾，皆應屬本發明專利 之涵蓋範圍。^ The total gas flow rate (TGF) of the reactor and the oxidation reaction time, to the growth of the desired ruthenium dioxide film and the suppression of the rolling of the metal ruthenium in the memory. The conventional technique is to grow cerium oxide at the same time, and it will cause defects in the oxidation of metal bismuth in the memory. The present invention has the following characteristics at low pressure, and the wet-type rapid thermal oxidation method has the following characteristics: (in) on-site tuva steam generation does not require an additional steam generator, and (2) performs at low pressure. High temperature reaction, (3) oxidation reaction is short, avoiding changes in the characteristics of semiconductor components, (4) better quality of the networked-structured, and (5) by pressure and gas The total flow rate control growth rate of the ruthenium dioxide film 〇 is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be covered by the present invention.
第16頁 1284371 ___案號92102066 年月日 修正__ 圖式簡單說明 圖式之簡單說明 圖一以及圖三為習知製作罩幕式唯讀記憶體的剖面 示意圖。 圖四以及圖六為本發明較佳實施例的剖面示意圖。 圖七為本發明低壓濕式快速熱氧化法於半導體晶片 表面上可能發生之反應式。 圖八為本發明低壓濕式快速熱氧化法的反應機構示 意圖。 圖九為本發明二氧化矽薄膜之結構示意圖。 圖式之符號說明Page 16 1284371 ___ Case No. 92102066 Date of revision __ Brief description of the diagram Simple description of the diagram Figure 1 and Figure 3 are schematic cross-sectional views of the mask-type read-only memory. 4 and 6 are schematic cross-sectional views of a preferred embodiment of the present invention. Figure 7 is a flow diagram of a low pressure wet rapid thermal oxidation process of the present invention which may occur on the surface of a semiconductor wafer. Figure 8 is a schematic illustration of the reaction mechanism of the low pressure wet rapid thermal oxidation process of the present invention. Figure 9 is a schematic view showing the structure of a ruthenium dioxide film of the present invention. Symbolic description of the schema
第17頁 50 罩幕式唯讀記憶體 51 基底 5 2 周邊電路區 53 N型井 54 記憶體區 5 5a, b 場氧化層 56 BDF 區 ' 57 P型井 58 氮化矽層 60 離子佈植 62 閘極氧化層 64 多晶石夕金屬層 66 光阻層 72 NMOS閘極 74 P Μ 0 S閘極 76 二氧化矽薄膜 75 R 0 M c e 1 1 閘極Page 17 50 Masked read-only memory 51 Substrate 5 2 Peripheral circuit area 53 N-well 54 Memory area 5 5a, b Field oxide layer 56 BDF area ' 57 P-type well 58 Tantalum nitride layer 60 Ion implantation 62 gate oxide layer 64 polycrystalline stone metal layer 66 photoresist layer 72 NMOS gate 74 P Μ 0 S gate 76 ytterbium oxide film 75 R 0 M ce 1 1 gate
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